arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable_types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/msr.h>
  22 #include <asm/desc_defs.h>
  23 #include <asm/nops.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/init.h>
  31 #include <linux/err.h>
  32
  33 #define HBP_NUM 4
  34 /*
  35  * Default implementation of macro that returns current
  36  * instruction pointer ("program counter").
  37  */
  38 static inline void *current_text_addr(void)
  39 {
  40         void *pc;
  41
  42         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  43
  44         return pc;
  45 }
  46
  47 #ifdef CONFIG_X86_VSMP
  48 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  49 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  50 #else
  51 # define ARCH_MIN_TASKALIGN             16
  52 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  53 #endif
  54
  55 /*
  56  *  CPU type and hardware bug flags. Kept separately for each CPU.
  57  *  Members of this structure are referenced in head.S, so think twice
  58  *  before touching them. [mj]
  59  */
  60
  61 struct cpuinfo_x86 {
  62         __u8                    x86;            /* CPU family */
  63         __u8                    x86_vendor;     /* CPU vendor */
  64         __u8                    x86_model;
  65         __u8                    x86_mask;
  66 #ifdef CONFIG_X86_32
  67         char                    wp_works_ok;    /* It doesn't on 386's */
  68
  69         /* Problems on some 486Dx4's and old 386's: */
  70         char                    hlt_works_ok;
  71         char                    hard_math;
  72         char                    rfu;
  73         char                    fdiv_bug;
  74         char                    f00f_bug;
  75         char                    coma_bug;
  76         char                    pad0;
  77 #else
  78         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  79         int                     x86_tlbsize;
  80 #endif
  81         __u8                    x86_virt_bits;
  82         __u8                    x86_phys_bits;
  83         /* CPUID returned core id bits: */
  84         __u8                    x86_coreid_bits;
  85         /* Max extended CPUID function supported: */
  86         __u32                   extended_cpuid_level;
  87         /* Maximum supported CPUID level, -1=no CPUID: */
  88         int                     cpuid_level;
  89         __u32                   x86_capability[NCAPINTS];
  90         char                    x86_vendor_id[16];
  91         char                    x86_model_id[64];
  92         /* in KB - valid for CPUS which support this call: */
  93         int                     x86_cache_size;
  94         int                     x86_cache_alignment;    /* In bytes */
  95         int                     x86_power;
  96         unsigned long           loops_per_jiffy;
  97 #ifdef CONFIG_SMP
  98         /* cpus sharing the last level cache: */
  99         cpumask_var_t           llc_shared_map;
 100 #endif
 101         /* cpuid returned max cores value: */
 102         u16                      x86_max_cores;
 103         u16                     apicid;
 104         u16                     initial_apicid;
 105         u16                     x86_clflush_size;
 106 #ifdef CONFIG_SMP
 107         /* number of cores as seen by the OS: */
 108         u16                     booted_cores;
 109         /* Physical processor id: */
 110         u16                     phys_proc_id;
 111         /* Core id: */
 112         u16                     cpu_core_id;
 113         /* Compute unit id */
 114         u8                      compute_unit_id;
 115         /* Index into per_cpu list: */
 116         u16                     cpu_index;
 117 #endif
 118 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 119
 120 #define X86_VENDOR_INTEL        0
 121 #define X86_VENDOR_CYRIX        1
 122 #define X86_VENDOR_AMD          2
 123 #define X86_VENDOR_UMC          3
 124 #define X86_VENDOR_CENTAUR      5
 125 #define X86_VENDOR_TRANSMETA    7
 126 #define X86_VENDOR_NSC          8
 127 #define X86_VENDOR_NUM          9
 128
 129 #define X86_VENDOR_UNKNOWN      0xff
 130
 131 /*
 132  * capabilities of CPUs
 133  */
 134 extern struct cpuinfo_x86       boot_cpu_data;
 135 extern struct cpuinfo_x86       new_cpu_data;
 136
 137 extern struct tss_struct        doublefault_tss;
 138 extern __u32                    cpu_caps_cleared[NCAPINTS];
 139 extern __u32                    cpu_caps_set[NCAPINTS];
 140
 141 #ifdef CONFIG_SMP
 142 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 143 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 144 #define current_cpu_data        __get_cpu_var(cpu_info)
 145 #else
 146 #define cpu_data(cpu)           boot_cpu_data
 147 #define current_cpu_data        boot_cpu_data
 148 #endif
 149
 150 extern const struct seq_operations cpuinfo_op;
 151
 152 static inline int hlt_works(int cpu)
 153 {
 154 #ifdef CONFIG_X86_32
 155         return cpu_data(cpu).hlt_works_ok;
 156 #else
 157         return 1;
 158 #endif
 159 }
 160
 161 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 162
 163 extern void cpu_detect(struct cpuinfo_x86 *c);
 164
 165 extern struct pt_regs *idle_regs(struct pt_regs *);
 166
 167 extern void early_cpu_init(void);
 168 extern void identify_boot_cpu(void);
 169 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 170 extern void print_cpu_info(struct cpuinfo_x86 *);
 171 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 172 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 173 extern unsigned short num_cache_leaves;
 174
 175 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 176 extern void detect_ht(struct cpuinfo_x86 *c);
 177
 178 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 179                                 unsigned int *ecx, unsigned int *edx)
 180 {
 181         /* ecx is often an input as well as an output. */
 182         asm volatile("cpuid"
 183             : "=a" (*eax),
 184               "=b" (*ebx),
 185               "=c" (*ecx),
 186               "=d" (*edx)
 187             : "0" (*eax), "2" (*ecx));
 188 }
 189
 190 static inline void load_cr3(pgd_t *pgdir)
 191 {
 192         write_cr3(__pa(pgdir));
 193 }
 194
 195 #ifdef CONFIG_X86_32
 196 /* This is the TSS defined by the hardware. */
 197 struct x86_hw_tss {
 198         unsigned short          back_link, __blh;
 199         unsigned long           sp0;
 200         unsigned short          ss0, __ss0h;
 201         unsigned long           sp1;
 202         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 203         unsigned short          ss1, __ss1h;
 204         unsigned long           sp2;
 205         unsigned short          ss2, __ss2h;
 206         unsigned long           __cr3;
 207         unsigned long           ip;
 208         unsigned long           flags;
 209         unsigned long           ax;
 210         unsigned long           cx;
 211         unsigned long           dx;
 212         unsigned long           bx;
 213         unsigned long           sp;
 214         unsigned long           bp;
 215         unsigned long           si;
 216         unsigned long           di;
 217         unsigned short          es, __esh;
 218         unsigned short          cs, __csh;
 219         unsigned short          ss, __ssh;
 220         unsigned short          ds, __dsh;
 221         unsigned short          fs, __fsh;
 222         unsigned short          gs, __gsh;
 223         unsigned short          ldt, __ldth;
 224         unsigned short          trace;
 225         unsigned short          io_bitmap_base;
 226
 227 } __attribute__((packed));
 228 #else
 229 struct x86_hw_tss {
 230         u32                     reserved1;
 231         u64                     sp0;
 232         u64                     sp1;
 233         u64                     sp2;
 234         u64                     reserved2;
 235         u64                     ist[7];
 236         u32                     reserved3;
 237         u32                     reserved4;
 238         u16                     reserved5;
 239         u16                     io_bitmap_base;
 240
 241 } __attribute__((packed)) ____cacheline_aligned;
 242 #endif
 243
 244 /*
 245  * IO-bitmap sizes:
 246  */
 247 #define IO_BITMAP_BITS                  65536
 248 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 249 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 250 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 251 #define INVALID_IO_BITMAP_OFFSET        0x8000
 252
 253 struct tss_struct {
 254         /*
 255          * The hardware state:
 256          */
 257         struct x86_hw_tss       x86_tss;
 258
 259         /*
 260          * The extra 1 is there because the CPU will access an
 261          * additional byte beyond the end of the IO permission
 262          * bitmap. The extra byte must be all 1 bits, and must
 263          * be within the limit.
 264          */
 265         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 266
 267         /*
 268          * .. and then another 0x100 bytes for the emergency kernel stack:
 269          */
 270         unsigned long           stack[64];
 271
 272 } ____cacheline_aligned;
 273
 274 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 275
 276 /*
 277  * Save the original ist values for checking stack pointers during debugging
 278  */
 279 struct orig_ist {
 280         unsigned long           ist[7];
 281 };
 282
 283 #define MXCSR_DEFAULT           0x1f80
 284
 285 struct i387_fsave_struct {
 286         u32                     cwd;    /* FPU Control Word             */
 287         u32                     swd;    /* FPU Status Word              */
 288         u32                     twd;    /* FPU Tag Word                 */
 289         u32                     fip;    /* FPU IP Offset                */
 290         u32                     fcs;    /* FPU IP Selector              */
 291         u32                     foo;    /* FPU Operand Pointer Offset   */
 292         u32                     fos;    /* FPU Operand Pointer Selector */
 293
 294         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 295         u32                     st_space[20];
 296
 297         /* Software status information [not touched by FSAVE ]:         */
 298         u32                     status;
 299 };
 300
 301 struct i387_fxsave_struct {
 302         u16                     cwd; /* Control Word                    */
 303         u16                     swd; /* Status Word                     */
 304         u16                     twd; /* Tag Word                        */
 305         u16                     fop; /* Last Instruction Opcode         */
 306         union {
 307                 struct {
 308                         u64     rip; /* Instruction Pointer             */
 309                         u64     rdp; /* Data Pointer                    */
 310                 };
 311                 struct {
 312                         u32     fip; /* FPU IP Offset                   */
 313                         u32     fcs; /* FPU IP Selector                 */
 314                         u32     foo; /* FPU Operand Offset              */
 315                         u32     fos; /* FPU Operand Selector            */
 316                 };
 317         };
 318         u32                     mxcsr;          /* MXCSR Register State */
 319         u32                     mxcsr_mask;     /* MXCSR Mask           */
 320
 321         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 322         u32                     st_space[32];
 323
 324         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 325         u32                     xmm_space[64];
 326
 327         u32                     padding[12];
 328
 329         union {
 330                 u32             padding1[12];
 331                 u32             sw_reserved[12];
 332         };
 333
 334 } __attribute__((aligned(16)));
 335
 336 struct i387_soft_struct {
 337         u32                     cwd;
 338         u32                     swd;
 339         u32                     twd;
 340         u32                     fip;
 341         u32                     fcs;
 342         u32                     foo;
 343         u32                     fos;
 344         /* 8*10 bytes for each FP-reg = 80 bytes: */
 345         u32                     st_space[20];
 346         u8                      ftop;
 347         u8                      changed;
 348         u8                      lookahead;
 349         u8                      no_update;
 350         u8                      rm;
 351         u8                      alimit;
 352         struct math_emu_info    *info;
 353         u32                     entry_eip;
 354 };
 355
 356 struct ymmh_struct {
 357         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 358         u32 ymmh_space[64];
 359 };
 360
 361 struct xsave_hdr_struct {
 362         u64 xstate_bv;
 363         u64 reserved1[2];
 364         u64 reserved2[5];
 365 } __attribute__((packed));
 366
 367 struct xsave_struct {
 368         struct i387_fxsave_struct i387;
 369         struct xsave_hdr_struct xsave_hdr;
 370         struct ymmh_struct ymmh;
 371         /* new processor state extensions will go here */
 372 } __attribute__ ((packed, aligned (64)));
 373
 374 union thread_xstate {
 375         struct i387_fsave_struct        fsave;
 376         struct i387_fxsave_struct       fxsave;
 377         struct i387_soft_struct         soft;
 378         struct xsave_struct             xsave;
 379 };
 380
 381 struct fpu {
 382         union thread_xstate *state;
 383 };
 384
 385 #ifdef CONFIG_X86_64
 386 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 387
 388 union irq_stack_union {
 389         char irq_stack[IRQ_STACK_SIZE];
 390         /*
 391          * GCC hardcodes the stack canary as %gs:40.  Since the
 392          * irq_stack is the object at %gs:0, we reserve the bottom
 393          * 48 bytes of the irq stack for the canary.
 394          */
 395         struct {
 396                 char gs_base[40];
 397                 unsigned long stack_canary;
 398         };
 399 };
 400
 401 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
 402 DECLARE_INIT_PER_CPU(irq_stack_union);
 403
 404 DECLARE_PER_CPU(char *, irq_stack_ptr);
 405 DECLARE_PER_CPU(unsigned int, irq_count);
 406 extern unsigned long kernel_eflags;
 407 extern asmlinkage void ignore_sysret(void);
 408 #else   /* X86_64 */
 409 #ifdef CONFIG_CC_STACKPROTECTOR
 410 /*
 411  * Make sure stack canary segment base is cached-aligned:
 412  *   "For Intel Atom processors, avoid non zero segment base address
 413  *    that is not aligned to cache line boundary at all cost."
 414  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 415  */
 416 struct stack_canary {
 417         char __pad[20];         /* canary at %gs:20 */
 418         unsigned long canary;
 419 };
 420 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 421 #endif
 422 #endif  /* X86_64 */
 423
 424 extern unsigned int xstate_size;
 425 extern void free_thread_xstate(struct task_struct *);
 426 extern struct kmem_cache *task_xstate_cachep;
 427
 428 struct perf_event;
 429
 430 struct thread_struct {
 431         /* Cached TLS descriptors: */
 432         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 433         unsigned long           sp0;
 434         unsigned long           sp;
 435 #ifdef CONFIG_X86_32
 436         unsigned long           sysenter_cs;
 437 #else
 438         unsigned long           usersp; /* Copy from PDA */
 439         unsigned short          es;
 440         unsigned short          ds;
 441         unsigned short          fsindex;
 442         unsigned short          gsindex;
 443 #endif
 444 #ifdef CONFIG_X86_32
 445         unsigned long           ip;
 446 #endif
 447 #ifdef CONFIG_X86_64
 448         unsigned long           fs;
 449 #endif
 450         unsigned long           gs;
 451         /* Save middle states of ptrace breakpoints */
 452         struct perf_event       *ptrace_bps[HBP_NUM];
 453         /* Debug status used for traps, single steps, etc... */
 454         unsigned long           debugreg6;
 455         /* Keep track of the exact dr7 value set by the user */
 456         unsigned long           ptrace_dr7;
 457         /* Fault info: */
 458         unsigned long           cr2;
 459         unsigned long           trap_no;
 460         unsigned long           error_code;
 461         /* floating point and extended processor state */
 462         struct fpu              fpu;
 463 #ifdef CONFIG_X86_32
 464         /* Virtual 86 mode info */
 465         struct vm86_struct __user *vm86_info;
 466         unsigned long           screen_bitmap;
 467         unsigned long           v86flags;
 468         unsigned long           v86mask;
 469         unsigned long           saved_sp0;
 470         unsigned int            saved_fs;
 471         unsigned int            saved_gs;
 472 #endif
 473         /* IO permissions: */
 474         unsigned long           *io_bitmap_ptr;
 475         unsigned long           iopl;
 476         /* Max allowed port in the bitmap, in bytes: */
 477         unsigned                io_bitmap_max;
 478 };
 479
 480 static inline unsigned long native_get_debugreg(int regno)
 481 {
 482         unsigned long val = 0;  /* Damn you, gcc! */
 483
 484         switch (regno) {
 485         case 0:
 486                 asm("mov %%db0, %0" :"=r" (val));
 487                 break;
 488         case 1:
 489                 asm("mov %%db1, %0" :"=r" (val));
 490                 break;
 491         case 2:
 492                 asm("mov %%db2, %0" :"=r" (val));
 493                 break;
 494         case 3:
 495                 asm("mov %%db3, %0" :"=r" (val));
 496                 break;
 497         case 6:
 498                 asm("mov %%db6, %0" :"=r" (val));
 499                 break;
 500         case 7:
 501                 asm("mov %%db7, %0" :"=r" (val));
 502                 break;
 503         default:
 504                 BUG();
 505         }
 506         return val;
 507 }
 508
 509 static inline void native_set_debugreg(int regno, unsigned long value)
 510 {
 511         switch (regno) {
 512         case 0:
 513                 asm("mov %0, %%db0"     ::"r" (value));
 514                 break;
 515         case 1:
 516                 asm("mov %0, %%db1"     ::"r" (value));
 517                 break;
 518         case 2:
 519                 asm("mov %0, %%db2"     ::"r" (value));
 520                 break;
 521         case 3:
 522                 asm("mov %0, %%db3"     ::"r" (value));
 523                 break;
 524         case 6:
 525                 asm("mov %0, %%db6"     ::"r" (value));
 526                 break;
 527         case 7:
 528                 asm("mov %0, %%db7"     ::"r" (value));
 529                 break;
 530         default:
 531                 BUG();
 532         }
 533 }
 534
 535 /*
 536  * Set IOPL bits in EFLAGS from given mask
 537  */
 538 static inline void native_set_iopl_mask(unsigned mask)
 539 {
 540 #ifdef CONFIG_X86_32
 541         unsigned int reg;
 542
 543         asm volatile ("pushfl;"
 544                       "popl %0;"
 545                       "andl %1, %0;"
 546                       "orl %2, %0;"
 547                       "pushl %0;"
 548                       "popfl"
 549                       : "=&r" (reg)
 550                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 551 #endif
 552 }
 553
 554 static inline void
 555 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 556 {
 557         tss->x86_tss.sp0 = thread->sp0;
 558 #ifdef CONFIG_X86_32
 559         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 560         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 561                 tss->x86_tss.ss1 = thread->sysenter_cs;
 562                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 563         }
 564 #endif
 565 }
 566
 567 static inline void native_swapgs(void)
 568 {
 569 #ifdef CONFIG_X86_64
 570         asm volatile("swapgs" ::: "memory");
 571 #endif
 572 }
 573
 574 #ifdef CONFIG_PARAVIRT
 575 #include <asm/paravirt.h>
 576 #else
 577 #define __cpuid                 native_cpuid
 578 #define paravirt_enabled()      0
 579
 580 /*
 581  * These special macros can be used to get or set a debugging register
 582  */
 583 #define get_debugreg(var, register)                             \
 584         (var) = native_get_debugreg(register)
 585 #define set_debugreg(value, register)                           \
 586         native_set_debugreg(register, value)
 587
 588 static inline void load_sp0(struct tss_struct *tss,
 589                             struct thread_struct *thread)
 590 {
 591         native_load_sp0(tss, thread);
 592 }
 593
 594 #define set_iopl_mask native_set_iopl_mask
 595 #endif /* CONFIG_PARAVIRT */
 596
 597 /*
 598  * Save the cr4 feature set we're using (ie
 599  * Pentium 4MB enable and PPro Global page
 600  * enable), so that any CPU's that boot up
 601  * after us can get the correct flags.
 602  */
 603 extern unsigned long            mmu_cr4_features;
 604
 605 static inline void set_in_cr4(unsigned long mask)
 606 {
 607         unsigned long cr4;
 608
 609         mmu_cr4_features |= mask;
 610         cr4 = read_cr4();
 611         cr4 |= mask;
 612         write_cr4(cr4);
 613 }
 614
 615 static inline void clear_in_cr4(unsigned long mask)
 616 {
 617         unsigned long cr4;
 618
 619         mmu_cr4_features &= ~mask;
 620         cr4 = read_cr4();
 621         cr4 &= ~mask;
 622         write_cr4(cr4);
 623 }
 624
 625 typedef struct {
 626         unsigned long           seg;
 627 } mm_segment_t;
 628
 629
 630 /*
 631  * create a kernel thread without removing it from tasklists
 632  */
 633 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 634
 635 /* Free all resources held by a thread. */
 636 extern void release_thread(struct task_struct *);
 637
 638 /* Prepare to copy thread state - unlazy all lazy state */
 639 extern void prepare_to_copy(struct task_struct *tsk);
 640
 641 unsigned long get_wchan(struct task_struct *p);
 642
 643 /*
 644  * Generic CPUID function
 645  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 646  * resulting in stale register contents being returned.
 647  */
 648 static inline void cpuid(unsigned int op,
 649                          unsigned int *eax, unsigned int *ebx,
 650                          unsigned int *ecx, unsigned int *edx)
 651 {
 652         *eax = op;
 653         *ecx = 0;
 654         __cpuid(eax, ebx, ecx, edx);
 655 }
 656
 657 /* Some CPUID calls want 'count' to be placed in ecx */
 658 static inline void cpuid_count(unsigned int op, int count,
 659                                unsigned int *eax, unsigned int *ebx,
 660                                unsigned int *ecx, unsigned int *edx)
 661 {
 662         *eax = op;
 663         *ecx = count;
 664         __cpuid(eax, ebx, ecx, edx);
 665 }
 666
 667 /*
 668  * CPUID functions returning a single datum
 669  */
 670 static inline unsigned int cpuid_eax(unsigned int op)
 671 {
 672         unsigned int eax, ebx, ecx, edx;
 673
 674         cpuid(op, &eax, &ebx, &ecx, &edx);
 675
 676         return eax;
 677 }
 678
 679 static inline unsigned int cpuid_ebx(unsigned int op)
 680 {
 681         unsigned int eax, ebx, ecx, edx;
 682
 683         cpuid(op, &eax, &ebx, &ecx, &edx);
 684
 685         return ebx;
 686 }
 687
 688 static inline unsigned int cpuid_ecx(unsigned int op)
 689 {
 690         unsigned int eax, ebx, ecx, edx;
 691
 692         cpuid(op, &eax, &ebx, &ecx, &edx);
 693
 694         return ecx;
 695 }
 696
 697 static inline unsigned int cpuid_edx(unsigned int op)
 698 {
 699         unsigned int eax, ebx, ecx, edx;
 700
 701         cpuid(op, &eax, &ebx, &ecx, &edx);
 702
 703         return edx;
 704 }
 705
 706 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 707 static inline void rep_nop(void)
 708 {
 709         asm volatile("rep; nop" ::: "memory");
 710 }
 711
 712 static inline void cpu_relax(void)
 713 {
 714         rep_nop();
 715 }
 716
 717 /* Stop speculative execution and prefetching of modified code. */
 718 static inline void sync_core(void)
 719 {
 720         int tmp;
 721
 722 #if defined(CONFIG_M386) || defined(CONFIG_M486)
 723         if (boot_cpu_data.x86 < 5)
 724                 /* There is no speculative execution.
 725                  * jmp is a barrier to prefetching. */
 726                 asm volatile("jmp 1f\n1:\n" ::: "memory");
 727         else
 728 #endif
 729                 /* cpuid is a barrier to speculative execution.
 730                  * Prefetched instructions are automatically
 731                  * invalidated when modified. */
 732                 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 733                              : "ebx", "ecx", "edx", "memory");
 734 }
 735
 736 static inline void __monitor(const void *eax, unsigned long ecx,
 737                              unsigned long edx)
 738 {
 739         /* "monitor %eax, %ecx, %edx;" */
 740         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 741                      :: "a" (eax), "c" (ecx), "d"(edx));
 742 }
 743
 744 static inline void __mwait(unsigned long eax, unsigned long ecx)
 745 {
 746         /* "mwait %eax, %ecx;" */
 747         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 748                      :: "a" (eax), "c" (ecx));
 749 }
 750
 751 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 752 {
 753         trace_hardirqs_on();
 754         /* "mwait %eax, %ecx;" */
 755         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 756                      :: "a" (eax), "c" (ecx));
 757 }
 758
 759 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 760
 761 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 762 extern void init_c1e_mask(void);
 763
 764 extern unsigned long            boot_option_idle_override;
 765 extern unsigned long            idle_halt;
 766 extern unsigned long            idle_nomwait;
 767 extern bool                     c1e_detected;
 768
 769 extern void enable_sep_cpu(void);
 770 extern int sysenter_setup(void);
 771
 772 extern void early_trap_init(void);
 773
 774 /* Defined in head.S */
 775 extern struct desc_ptr          early_gdt_descr;
 776
 777 extern void cpu_set_gdt(int);
 778 extern void switch_to_new_gdt(int);
 779 extern void load_percpu_segment(int);
 780 extern void cpu_init(void);
 781
 782 static inline unsigned long get_debugctlmsr(void)
 783 {
 784         unsigned long debugctlmsr = 0;
 785
 786 #ifndef CONFIG_X86_DEBUGCTLMSR
 787         if (boot_cpu_data.x86 < 6)
 788                 return 0;
 789 #endif
 790         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 791
 792         return debugctlmsr;
 793 }
 794
 795 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 796 {
 797 #ifndef CONFIG_X86_DEBUGCTLMSR
 798         if (boot_cpu_data.x86 < 6)
 799                 return;
 800 #endif
 801         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 802 }
 803
 804 /*
 805  * from system description table in BIOS. Mostly for MCA use, but
 806  * others may find it useful:
 807  */
 808 extern unsigned int             machine_id;
 809 extern unsigned int             machine_submodel_id;
 810 extern unsigned int             BIOS_revision;
 811
 812 /* Boot loader type from the setup header: */
 813 extern int                      bootloader_type;
 814 extern int                      bootloader_version;
 815
 816 extern char                     ignore_fpu_irq;
 817
 818 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 819 #define ARCH_HAS_PREFETCHW
 820 #define ARCH_HAS_SPINLOCK_PREFETCH
 821
 822 #ifdef CONFIG_X86_32
 823 # define BASE_PREFETCH          ASM_NOP4
 824 # define ARCH_HAS_PREFETCH
 825 #else
 826 # define BASE_PREFETCH          "prefetcht0 (%1)"
 827 #endif
 828
 829 /*
 830  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 831  *
 832  * It's not worth to care about 3dnow prefetches for the K6
 833  * because they are microcoded there and very slow.
 834  */
 835 static inline void prefetch(const void *x)
 836 {
 837         alternative_input(BASE_PREFETCH,
 838                           "prefetchnta (%1)",
 839                           X86_FEATURE_XMM,
 840                           "r" (x));
 841 }
 842
 843 /*
 844  * 3dnow prefetch to get an exclusive cache line.
 845  * Useful for spinlocks to avoid one state transition in the
 846  * cache coherency protocol:
 847  */
 848 static inline void prefetchw(const void *x)
 849 {
 850         alternative_input(BASE_PREFETCH,
 851                           "prefetchw (%1)",
 852                           X86_FEATURE_3DNOW,
 853                           "r" (x));
 854 }
 855
 856 static inline void spin_lock_prefetch(const void *x)
 857 {
 858         prefetchw(x);
 859 }
 860
 861 #ifdef CONFIG_X86_32
 862 /*
 863  * User space process size: 3GB (default).
 864  */
 865 #define TASK_SIZE               PAGE_OFFSET
 866 #define TASK_SIZE_MAX           TASK_SIZE
 867 #define STACK_TOP               TASK_SIZE
 868 #define STACK_TOP_MAX           STACK_TOP
 869
 870 #define INIT_THREAD  {                                                    \
 871         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 872         .vm86_info              = NULL,                                   \
 873         .sysenter_cs            = __KERNEL_CS,                            \
 874         .io_bitmap_ptr          = NULL,                                   \
 875 }
 876
 877 /*
 878  * Note that the .io_bitmap member must be extra-big. This is because
 879  * the CPU will access an additional byte beyond the end of the IO
 880  * permission bitmap. The extra byte must be all 1 bits, and must
 881  * be within the limit.
 882  */
 883 #define INIT_TSS  {                                                       \
 884         .x86_tss = {                                                      \
 885                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 886                 .ss0            = __KERNEL_DS,                            \
 887                 .ss1            = __KERNEL_CS,                            \
 888                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 889          },                                                               \
 890         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 891 }
 892
 893 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 894
 895 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 896 #define KSTK_TOP(info)                                                 \
 897 ({                                                                     \
 898        unsigned long *__ptr = (unsigned long *)(info);                 \
 899        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 900 })
 901
 902 /*
 903  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 904  * This is necessary to guarantee that the entire "struct pt_regs"
 905  * is accessible even if the CPU haven't stored the SS/ESP registers
 906  * on the stack (interrupt gate does not save these registers
 907  * when switching to the same priv ring).
 908  * Therefore beware: accessing the ss/esp fields of the
 909  * "struct pt_regs" is possible, but they may contain the
 910  * completely wrong values.
 911  */
 912 #define task_pt_regs(task)                                             \
 913 ({                                                                     \
 914        struct pt_regs *__regs__;                                       \
 915        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 916        __regs__ - 1;                                                   \
 917 })
 918
 919 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 920
 921 #else
 922 /*
 923  * User space process size. 47bits minus one guard page.
 924  */
 925 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 926
 927 /* This decides where the kernel will search for a free chunk of vm
 928  * space during mmap's.
 929  */
 930 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 931                                         0xc0000000 : 0xFFFFe000)
 932
 933 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 934                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 935 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 936                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 937
 938 #define STACK_TOP               TASK_SIZE
 939 #define STACK_TOP_MAX           TASK_SIZE_MAX
 940
 941 #define INIT_THREAD  { \
 942         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 943 }
 944
 945 #define INIT_TSS  { \
 946         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 947 }
 948
 949 /*
 950  * Return saved PC of a blocked thread.
 951  * What is this good for? it will be always the scheduler or ret_from_fork.
 952  */
 953 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 954
 955 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 956 extern unsigned long KSTK_ESP(struct task_struct *task);
 957 #endif /* CONFIG_X86_64 */
 958
 959 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 960                                                unsigned long new_sp);
 961
 962 /*
 963  * This decides where the kernel will search for a free chunk of vm
 964  * space during mmap's.
 965  */
 966 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 967
 968 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 969
 970 /* Get/set a process' ability to use the timestamp counter instruction */
 971 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 972 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 973
 974 extern int get_tsc_mode(unsigned long adr);
 975 extern int set_tsc_mode(unsigned int val);
 976
 977 extern int amd_get_nb_id(int cpu);
 978
 979 struct aperfmperf {
 980         u64 aperf, mperf;
 981 };
 982
 983 static inline void get_aperfmperf(struct aperfmperf *am)
 984 {
 985         WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
 986
 987         rdmsrl(MSR_IA32_APERF, am->aperf);
 988         rdmsrl(MSR_IA32_MPERF, am->mperf);
 989 }
 990
 991 #define APERFMPERF_SHIFT 10
 992
 993 static inline
 994 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
 995                                     struct aperfmperf *new)
 996 {
 997         u64 aperf = new->aperf - old->aperf;
 998         u64 mperf = new->mperf - old->mperf;
 999         unsigned long ratio = aperf;
1000
1001         mperf >>= APERFMPERF_SHIFT;
1002         if (mperf)
1003                 ratio = div64_u64(aperf, mperf);
1004
1005         return ratio;
1006 }
1007
1008 /*
1009  * AMD errata checking
1010  */
1011 #ifdef CONFIG_CPU_SUP_AMD
1012 extern const int amd_erratum_383[];
1013 extern const int amd_erratum_400[];
1014 extern bool cpu_has_amd_erratum(const int *);
1015
1016 #define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
1017 #define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
1018 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1019         ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1020 #define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
1021 #define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
1022 #define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
1023
1024 #else
1025 #define cpu_has_amd_erratum(x)  (false)
1026 #endif /* CONFIG_CPU_SUP_AMD */
1027
1028 #endif /* _ASM_X86_PROCESSOR_H */