1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
38 static inline void *current_text_addr(void)
42 asm volatile("mov $1f, %0; 1:":"=r" (pc
));
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
62 __u8 x86
; /* CPU family */
63 __u8 x86_vendor
; /* CPU vendor */
67 char wp_works_ok
; /* It doesn't on 386's */
69 /* Problems on some 486Dx4's and old 386's: */
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
83 /* CPUID returned core id bits: */
85 /* Max extended CPUID function supported: */
86 __u32 extended_cpuid_level
;
87 /* Maximum supported CPUID level, -1=no CPUID: */
89 __u32 x86_capability
[NCAPINTS
];
90 char x86_vendor_id
[16];
91 char x86_model_id
[64];
92 /* in KB - valid for CPUS which support this call: */
94 int x86_cache_alignment
; /* In bytes */
96 unsigned long loops_per_jiffy
;
98 /* cpus sharing the last level cache: */
99 cpumask_var_t llc_shared_map
;
101 /* cpuid returned max cores value: */
105 u16 x86_clflush_size
;
107 /* number of cores as seen by the OS: */
109 /* Physical processor id: */
113 /* Compute unit id */
115 /* Index into per_cpu list: */
118 } __attribute__((__aligned__(SMP_CACHE_BYTES
)));
120 #define X86_VENDOR_INTEL 0
121 #define X86_VENDOR_CYRIX 1
122 #define X86_VENDOR_AMD 2
123 #define X86_VENDOR_UMC 3
124 #define X86_VENDOR_CENTAUR 5
125 #define X86_VENDOR_TRANSMETA 7
126 #define X86_VENDOR_NSC 8
127 #define X86_VENDOR_NUM 9
129 #define X86_VENDOR_UNKNOWN 0xff
132 * capabilities of CPUs
134 extern struct cpuinfo_x86 boot_cpu_data
;
135 extern struct cpuinfo_x86 new_cpu_data
;
137 extern struct tss_struct doublefault_tss
;
138 extern __u32 cpu_caps_cleared
[NCAPINTS
];
139 extern __u32 cpu_caps_set
[NCAPINTS
];
142 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
143 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
144 #define current_cpu_data __get_cpu_var(cpu_info)
146 #define cpu_data(cpu) boot_cpu_data
147 #define current_cpu_data boot_cpu_data
150 extern const struct seq_operations cpuinfo_op
;
152 static inline int hlt_works(int cpu
)
155 return cpu_data(cpu
).hlt_works_ok
;
161 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
163 extern void cpu_detect(struct cpuinfo_x86
*c
);
165 extern struct pt_regs
*idle_regs(struct pt_regs
*);
167 extern void early_cpu_init(void);
168 extern void identify_boot_cpu(void);
169 extern void identify_secondary_cpu(struct cpuinfo_x86
*);
170 extern void print_cpu_info(struct cpuinfo_x86
*);
171 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
172 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
173 extern unsigned short num_cache_leaves
;
175 extern void detect_extended_topology(struct cpuinfo_x86
*c
);
176 extern void detect_ht(struct cpuinfo_x86
*c
);
178 static inline void native_cpuid(unsigned int *eax
, unsigned int *ebx
,
179 unsigned int *ecx
, unsigned int *edx
)
181 /* ecx is often an input as well as an output. */
187 : "0" (*eax
), "2" (*ecx
));
190 static inline void load_cr3(pgd_t
*pgdir
)
192 write_cr3(__pa(pgdir
));
196 /* This is the TSS defined by the hardware. */
198 unsigned short back_link
, __blh
;
200 unsigned short ss0
, __ss0h
;
202 /* ss1 caches MSR_IA32_SYSENTER_CS: */
203 unsigned short ss1
, __ss1h
;
205 unsigned short ss2
, __ss2h
;
217 unsigned short es
, __esh
;
218 unsigned short cs
, __csh
;
219 unsigned short ss
, __ssh
;
220 unsigned short ds
, __dsh
;
221 unsigned short fs
, __fsh
;
222 unsigned short gs
, __gsh
;
223 unsigned short ldt
, __ldth
;
224 unsigned short trace
;
225 unsigned short io_bitmap_base
;
227 } __attribute__((packed
));
241 } __attribute__((packed
)) ____cacheline_aligned
;
247 #define IO_BITMAP_BITS 65536
248 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
249 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
250 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
251 #define INVALID_IO_BITMAP_OFFSET 0x8000
255 * The hardware state:
257 struct x86_hw_tss x86_tss
;
260 * The extra 1 is there because the CPU will access an
261 * additional byte beyond the end of the IO permission
262 * bitmap. The extra byte must be all 1 bits, and must
263 * be within the limit.
265 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
268 * .. and then another 0x100 bytes for the emergency kernel stack:
270 unsigned long stack
[64];
272 } ____cacheline_aligned
;
274 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, init_tss
);
277 * Save the original ist values for checking stack pointers during debugging
280 unsigned long ist
[7];
283 #define MXCSR_DEFAULT 0x1f80
285 struct i387_fsave_struct
{
286 u32 cwd
; /* FPU Control Word */
287 u32 swd
; /* FPU Status Word */
288 u32 twd
; /* FPU Tag Word */
289 u32 fip
; /* FPU IP Offset */
290 u32 fcs
; /* FPU IP Selector */
291 u32 foo
; /* FPU Operand Pointer Offset */
292 u32 fos
; /* FPU Operand Pointer Selector */
294 /* 8*10 bytes for each FP-reg = 80 bytes: */
297 /* Software status information [not touched by FSAVE ]: */
301 struct i387_fxsave_struct
{
302 u16 cwd
; /* Control Word */
303 u16 swd
; /* Status Word */
304 u16 twd
; /* Tag Word */
305 u16 fop
; /* Last Instruction Opcode */
308 u64 rip
; /* Instruction Pointer */
309 u64 rdp
; /* Data Pointer */
312 u32 fip
; /* FPU IP Offset */
313 u32 fcs
; /* FPU IP Selector */
314 u32 foo
; /* FPU Operand Offset */
315 u32 fos
; /* FPU Operand Selector */
318 u32 mxcsr
; /* MXCSR Register State */
319 u32 mxcsr_mask
; /* MXCSR Mask */
321 /* 8*16 bytes for each FP-reg = 128 bytes: */
324 /* 16*16 bytes for each XMM-reg = 256 bytes: */
334 } __attribute__((aligned(16)));
336 struct i387_soft_struct
{
344 /* 8*10 bytes for each FP-reg = 80 bytes: */
352 struct math_emu_info
*info
;
357 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
361 struct xsave_hdr_struct
{
365 } __attribute__((packed
));
367 struct xsave_struct
{
368 struct i387_fxsave_struct i387
;
369 struct xsave_hdr_struct xsave_hdr
;
370 struct ymmh_struct ymmh
;
371 /* new processor state extensions will go here */
372 } __attribute__ ((packed
, aligned (64)));
374 union thread_xstate
{
375 struct i387_fsave_struct fsave
;
376 struct i387_fxsave_struct fxsave
;
377 struct i387_soft_struct soft
;
378 struct xsave_struct xsave
;
382 union thread_xstate
*state
;
386 DECLARE_PER_CPU(struct orig_ist
, orig_ist
);
388 union irq_stack_union
{
389 char irq_stack
[IRQ_STACK_SIZE
];
391 * GCC hardcodes the stack canary as %gs:40. Since the
392 * irq_stack is the object at %gs:0, we reserve the bottom
393 * 48 bytes of the irq stack for the canary.
397 unsigned long stack_canary
;
401 DECLARE_PER_CPU_FIRST(union irq_stack_union
, irq_stack_union
);
402 DECLARE_INIT_PER_CPU(irq_stack_union
);
404 DECLARE_PER_CPU(char *, irq_stack_ptr
);
405 DECLARE_PER_CPU(unsigned int, irq_count
);
406 extern unsigned long kernel_eflags
;
407 extern asmlinkage
void ignore_sysret(void);
409 #ifdef CONFIG_CC_STACKPROTECTOR
411 * Make sure stack canary segment base is cached-aligned:
412 * "For Intel Atom processors, avoid non zero segment base address
413 * that is not aligned to cache line boundary at all cost."
414 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
416 struct stack_canary
{
417 char __pad
[20]; /* canary at %gs:20 */
418 unsigned long canary
;
420 DECLARE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
424 extern unsigned int xstate_size
;
425 extern void free_thread_xstate(struct task_struct
*);
426 extern struct kmem_cache
*task_xstate_cachep
;
430 struct thread_struct
{
431 /* Cached TLS descriptors: */
432 struct desc_struct tls_array
[GDT_ENTRY_TLS_ENTRIES
];
436 unsigned long sysenter_cs
;
438 unsigned long usersp
; /* Copy from PDA */
441 unsigned short fsindex
;
442 unsigned short gsindex
;
451 /* Save middle states of ptrace breakpoints */
452 struct perf_event
*ptrace_bps
[HBP_NUM
];
453 /* Debug status used for traps, single steps, etc... */
454 unsigned long debugreg6
;
455 /* Keep track of the exact dr7 value set by the user */
456 unsigned long ptrace_dr7
;
459 unsigned long trap_no
;
460 unsigned long error_code
;
461 /* floating point and extended processor state */
464 /* Virtual 86 mode info */
465 struct vm86_struct __user
*vm86_info
;
466 unsigned long screen_bitmap
;
467 unsigned long v86flags
;
468 unsigned long v86mask
;
469 unsigned long saved_sp0
;
470 unsigned int saved_fs
;
471 unsigned int saved_gs
;
473 /* IO permissions: */
474 unsigned long *io_bitmap_ptr
;
476 /* Max allowed port in the bitmap, in bytes: */
477 unsigned io_bitmap_max
;
480 static inline unsigned long native_get_debugreg(int regno
)
482 unsigned long val
= 0; /* Damn you, gcc! */
486 asm("mov %%db0, %0" :"=r" (val
));
489 asm("mov %%db1, %0" :"=r" (val
));
492 asm("mov %%db2, %0" :"=r" (val
));
495 asm("mov %%db3, %0" :"=r" (val
));
498 asm("mov %%db6, %0" :"=r" (val
));
501 asm("mov %%db7, %0" :"=r" (val
));
509 static inline void native_set_debugreg(int regno
, unsigned long value
)
513 asm("mov %0, %%db0" ::"r" (value
));
516 asm("mov %0, %%db1" ::"r" (value
));
519 asm("mov %0, %%db2" ::"r" (value
));
522 asm("mov %0, %%db3" ::"r" (value
));
525 asm("mov %0, %%db6" ::"r" (value
));
528 asm("mov %0, %%db7" ::"r" (value
));
536 * Set IOPL bits in EFLAGS from given mask
538 static inline void native_set_iopl_mask(unsigned mask
)
543 asm volatile ("pushfl;"
550 : "i" (~X86_EFLAGS_IOPL
), "r" (mask
));
555 native_load_sp0(struct tss_struct
*tss
, struct thread_struct
*thread
)
557 tss
->x86_tss
.sp0
= thread
->sp0
;
559 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
560 if (unlikely(tss
->x86_tss
.ss1
!= thread
->sysenter_cs
)) {
561 tss
->x86_tss
.ss1
= thread
->sysenter_cs
;
562 wrmsr(MSR_IA32_SYSENTER_CS
, thread
->sysenter_cs
, 0);
567 static inline void native_swapgs(void)
570 asm volatile("swapgs" ::: "memory");
574 #ifdef CONFIG_PARAVIRT
575 #include <asm/paravirt.h>
577 #define __cpuid native_cpuid
578 #define paravirt_enabled() 0
581 * These special macros can be used to get or set a debugging register
583 #define get_debugreg(var, register) \
584 (var) = native_get_debugreg(register)
585 #define set_debugreg(value, register) \
586 native_set_debugreg(register, value)
588 static inline void load_sp0(struct tss_struct
*tss
,
589 struct thread_struct
*thread
)
591 native_load_sp0(tss
, thread
);
594 #define set_iopl_mask native_set_iopl_mask
595 #endif /* CONFIG_PARAVIRT */
598 * Save the cr4 feature set we're using (ie
599 * Pentium 4MB enable and PPro Global page
600 * enable), so that any CPU's that boot up
601 * after us can get the correct flags.
603 extern unsigned long mmu_cr4_features
;
605 static inline void set_in_cr4(unsigned long mask
)
609 mmu_cr4_features
|= mask
;
615 static inline void clear_in_cr4(unsigned long mask
)
619 mmu_cr4_features
&= ~mask
;
631 * create a kernel thread without removing it from tasklists
633 extern int kernel_thread(int (*fn
)(void *), void *arg
, unsigned long flags
);
635 /* Free all resources held by a thread. */
636 extern void release_thread(struct task_struct
*);
638 /* Prepare to copy thread state - unlazy all lazy state */
639 extern void prepare_to_copy(struct task_struct
*tsk
);
641 unsigned long get_wchan(struct task_struct
*p
);
644 * Generic CPUID function
645 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
646 * resulting in stale register contents being returned.
648 static inline void cpuid(unsigned int op
,
649 unsigned int *eax
, unsigned int *ebx
,
650 unsigned int *ecx
, unsigned int *edx
)
654 __cpuid(eax
, ebx
, ecx
, edx
);
657 /* Some CPUID calls want 'count' to be placed in ecx */
658 static inline void cpuid_count(unsigned int op
, int count
,
659 unsigned int *eax
, unsigned int *ebx
,
660 unsigned int *ecx
, unsigned int *edx
)
664 __cpuid(eax
, ebx
, ecx
, edx
);
668 * CPUID functions returning a single datum
670 static inline unsigned int cpuid_eax(unsigned int op
)
672 unsigned int eax
, ebx
, ecx
, edx
;
674 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
679 static inline unsigned int cpuid_ebx(unsigned int op
)
681 unsigned int eax
, ebx
, ecx
, edx
;
683 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
688 static inline unsigned int cpuid_ecx(unsigned int op
)
690 unsigned int eax
, ebx
, ecx
, edx
;
692 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
697 static inline unsigned int cpuid_edx(unsigned int op
)
699 unsigned int eax
, ebx
, ecx
, edx
;
701 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
706 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
707 static inline void rep_nop(void)
709 asm volatile("rep; nop" ::: "memory");
712 static inline void cpu_relax(void)
717 /* Stop speculative execution and prefetching of modified code. */
718 static inline void sync_core(void)
722 #if defined(CONFIG_M386) || defined(CONFIG_M486)
723 if (boot_cpu_data
.x86
< 5)
724 /* There is no speculative execution.
725 * jmp is a barrier to prefetching. */
726 asm volatile("jmp 1f\n1:\n" ::: "memory");
729 /* cpuid is a barrier to speculative execution.
730 * Prefetched instructions are automatically
731 * invalidated when modified. */
732 asm volatile("cpuid" : "=a" (tmp
) : "0" (1)
733 : "ebx", "ecx", "edx", "memory");
736 static inline void __monitor(const void *eax
, unsigned long ecx
,
739 /* "monitor %eax, %ecx, %edx;" */
740 asm volatile(".byte 0x0f, 0x01, 0xc8;"
741 :: "a" (eax
), "c" (ecx
), "d"(edx
));
744 static inline void __mwait(unsigned long eax
, unsigned long ecx
)
746 /* "mwait %eax, %ecx;" */
747 asm volatile(".byte 0x0f, 0x01, 0xc9;"
748 :: "a" (eax
), "c" (ecx
));
751 static inline void __sti_mwait(unsigned long eax
, unsigned long ecx
)
754 /* "mwait %eax, %ecx;" */
755 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
756 :: "a" (eax
), "c" (ecx
));
759 extern void mwait_idle_with_hints(unsigned long eax
, unsigned long ecx
);
761 extern void select_idle_routine(const struct cpuinfo_x86
*c
);
762 extern void init_c1e_mask(void);
764 extern unsigned long boot_option_idle_override
;
765 extern unsigned long idle_halt
;
766 extern unsigned long idle_nomwait
;
767 extern bool c1e_detected
;
769 extern void enable_sep_cpu(void);
770 extern int sysenter_setup(void);
772 extern void early_trap_init(void);
774 /* Defined in head.S */
775 extern struct desc_ptr early_gdt_descr
;
777 extern void cpu_set_gdt(int);
778 extern void switch_to_new_gdt(int);
779 extern void load_percpu_segment(int);
780 extern void cpu_init(void);
782 static inline unsigned long get_debugctlmsr(void)
784 unsigned long debugctlmsr
= 0;
786 #ifndef CONFIG_X86_DEBUGCTLMSR
787 if (boot_cpu_data
.x86
< 6)
790 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
795 static inline void update_debugctlmsr(unsigned long debugctlmsr
)
797 #ifndef CONFIG_X86_DEBUGCTLMSR
798 if (boot_cpu_data
.x86
< 6)
801 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
805 * from system description table in BIOS. Mostly for MCA use, but
806 * others may find it useful:
808 extern unsigned int machine_id
;
809 extern unsigned int machine_submodel_id
;
810 extern unsigned int BIOS_revision
;
812 /* Boot loader type from the setup header: */
813 extern int bootloader_type
;
814 extern int bootloader_version
;
816 extern char ignore_fpu_irq
;
818 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
819 #define ARCH_HAS_PREFETCHW
820 #define ARCH_HAS_SPINLOCK_PREFETCH
823 # define BASE_PREFETCH ASM_NOP4
824 # define ARCH_HAS_PREFETCH
826 # define BASE_PREFETCH "prefetcht0 (%1)"
830 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
832 * It's not worth to care about 3dnow prefetches for the K6
833 * because they are microcoded there and very slow.
835 static inline void prefetch(const void *x
)
837 alternative_input(BASE_PREFETCH
,
844 * 3dnow prefetch to get an exclusive cache line.
845 * Useful for spinlocks to avoid one state transition in the
846 * cache coherency protocol:
848 static inline void prefetchw(const void *x
)
850 alternative_input(BASE_PREFETCH
,
856 static inline void spin_lock_prefetch(const void *x
)
863 * User space process size: 3GB (default).
865 #define TASK_SIZE PAGE_OFFSET
866 #define TASK_SIZE_MAX TASK_SIZE
867 #define STACK_TOP TASK_SIZE
868 #define STACK_TOP_MAX STACK_TOP
870 #define INIT_THREAD { \
871 .sp0 = sizeof(init_stack) + (long)&init_stack, \
873 .sysenter_cs = __KERNEL_CS, \
874 .io_bitmap_ptr = NULL, \
878 * Note that the .io_bitmap member must be extra-big. This is because
879 * the CPU will access an additional byte beyond the end of the IO
880 * permission bitmap. The extra byte must be all 1 bits, and must
881 * be within the limit.
885 .sp0 = sizeof(init_stack) + (long)&init_stack, \
886 .ss0 = __KERNEL_DS, \
887 .ss1 = __KERNEL_CS, \
888 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
890 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
893 extern unsigned long thread_saved_pc(struct task_struct
*tsk
);
895 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
896 #define KSTK_TOP(info) \
898 unsigned long *__ptr = (unsigned long *)(info); \
899 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
903 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
904 * This is necessary to guarantee that the entire "struct pt_regs"
905 * is accessible even if the CPU haven't stored the SS/ESP registers
906 * on the stack (interrupt gate does not save these registers
907 * when switching to the same priv ring).
908 * Therefore beware: accessing the ss/esp fields of the
909 * "struct pt_regs" is possible, but they may contain the
910 * completely wrong values.
912 #define task_pt_regs(task) \
914 struct pt_regs *__regs__; \
915 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
919 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
923 * User space process size. 47bits minus one guard page.
925 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
927 /* This decides where the kernel will search for a free chunk of vm
928 * space during mmap's.
930 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
931 0xc0000000 : 0xFFFFe000)
933 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
934 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
935 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
936 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
938 #define STACK_TOP TASK_SIZE
939 #define STACK_TOP_MAX TASK_SIZE_MAX
941 #define INIT_THREAD { \
942 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
946 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
950 * Return saved PC of a blocked thread.
951 * What is this good for? it will be always the scheduler or ret_from_fork.
953 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
955 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
956 extern unsigned long KSTK_ESP(struct task_struct
*task
);
957 #endif /* CONFIG_X86_64 */
959 extern void start_thread(struct pt_regs
*regs
, unsigned long new_ip
,
960 unsigned long new_sp
);
963 * This decides where the kernel will search for a free chunk of vm
964 * space during mmap's.
966 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
968 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
970 /* Get/set a process' ability to use the timestamp counter instruction */
971 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
972 #define SET_TSC_CTL(val) set_tsc_mode((val))
974 extern int get_tsc_mode(unsigned long adr
);
975 extern int set_tsc_mode(unsigned int val
);
977 extern int amd_get_nb_id(int cpu
);
983 static inline void get_aperfmperf(struct aperfmperf
*am
)
985 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF
));
987 rdmsrl(MSR_IA32_APERF
, am
->aperf
);
988 rdmsrl(MSR_IA32_MPERF
, am
->mperf
);
991 #define APERFMPERF_SHIFT 10
994 unsigned long calc_aperfmperf_ratio(struct aperfmperf
*old
,
995 struct aperfmperf
*new)
997 u64 aperf
= new->aperf
- old
->aperf
;
998 u64 mperf
= new->mperf
- old
->mperf
;
999 unsigned long ratio
= aperf
;
1001 mperf
>>= APERFMPERF_SHIFT
;
1003 ratio
= div64_u64(aperf
, mperf
);
1009 * AMD errata checking
1011 #ifdef CONFIG_CPU_SUP_AMD
1012 extern const int amd_erratum_383
[];
1013 extern const int amd_erratum_400
[];
1014 extern bool cpu_has_amd_erratum(const int *);
1016 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1017 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1018 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1019 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1020 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1021 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1022 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1025 #define cpu_has_amd_erratum(x) (false)
1026 #endif /* CONFIG_CPU_SUP_AMD */
1028 #endif /* _ASM_X86_PROCESSOR_H */