arch/x86/include/asm/svm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __SVM_H
   3 #define __SVM_H
   4
   5 #include <uapi/asm/svm.h>
   6 #include <uapi/asm/kvm.h>
   7
   8 /*
   9  * 32-bit intercept words in the VMCB Control Area, starting
  10  * at Byte offset 000h.
  11  */
  12
  13 enum intercept_words {
  14         INTERCEPT_CR = 0,
  15         INTERCEPT_DR,
  16         INTERCEPT_EXCEPTION,
  17         MAX_INTERCEPT,
  18 };
  19
  20 enum {
  21         /* Byte offset 000h (word 0) */
  22         INTERCEPT_CR0_READ = 0,
  23         INTERCEPT_CR3_READ = 3,
  24         INTERCEPT_CR4_READ = 4,
  25         INTERCEPT_CR8_READ = 8,
  26         INTERCEPT_CR0_WRITE = 16,
  27         INTERCEPT_CR3_WRITE = 16 + 3,
  28         INTERCEPT_CR4_WRITE = 16 + 4,
  29         INTERCEPT_CR8_WRITE = 16 + 8,
  30         /* Byte offset 004h (word 1) */
  31         INTERCEPT_DR0_READ = 32,
  32         INTERCEPT_DR1_READ,
  33         INTERCEPT_DR2_READ,
  34         INTERCEPT_DR3_READ,
  35         INTERCEPT_DR4_READ,
  36         INTERCEPT_DR5_READ,
  37         INTERCEPT_DR6_READ,
  38         INTERCEPT_DR7_READ,
  39         INTERCEPT_DR0_WRITE = 48,
  40         INTERCEPT_DR1_WRITE,
  41         INTERCEPT_DR2_WRITE,
  42         INTERCEPT_DR3_WRITE,
  43         INTERCEPT_DR4_WRITE,
  44         INTERCEPT_DR5_WRITE,
  45         INTERCEPT_DR6_WRITE,
  46         INTERCEPT_DR7_WRITE,
  47         /* Byte offset 008h (word 2) */
  48         INTERCEPT_EXCEPTION_OFFSET = 64,
  49 };
  50
  51 enum {
  52         INTERCEPT_INTR,
  53         INTERCEPT_NMI,
  54         INTERCEPT_SMI,
  55         INTERCEPT_INIT,
  56         INTERCEPT_VINTR,
  57         INTERCEPT_SELECTIVE_CR0,
  58         INTERCEPT_STORE_IDTR,
  59         INTERCEPT_STORE_GDTR,
  60         INTERCEPT_STORE_LDTR,
  61         INTERCEPT_STORE_TR,
  62         INTERCEPT_LOAD_IDTR,
  63         INTERCEPT_LOAD_GDTR,
  64         INTERCEPT_LOAD_LDTR,
  65         INTERCEPT_LOAD_TR,
  66         INTERCEPT_RDTSC,
  67         INTERCEPT_RDPMC,
  68         INTERCEPT_PUSHF,
  69         INTERCEPT_POPF,
  70         INTERCEPT_CPUID,
  71         INTERCEPT_RSM,
  72         INTERCEPT_IRET,
  73         INTERCEPT_INTn,
  74         INTERCEPT_INVD,
  75         INTERCEPT_PAUSE,
  76         INTERCEPT_HLT,
  77         INTERCEPT_INVLPG,
  78         INTERCEPT_INVLPGA,
  79         INTERCEPT_IOIO_PROT,
  80         INTERCEPT_MSR_PROT,
  81         INTERCEPT_TASK_SWITCH,
  82         INTERCEPT_FERR_FREEZE,
  83         INTERCEPT_SHUTDOWN,
  84         INTERCEPT_VMRUN,
  85         INTERCEPT_VMMCALL,
  86         INTERCEPT_VMLOAD,
  87         INTERCEPT_VMSAVE,
  88         INTERCEPT_STGI,
  89         INTERCEPT_CLGI,
  90         INTERCEPT_SKINIT,
  91         INTERCEPT_RDTSCP,
  92         INTERCEPT_ICEBP,
  93         INTERCEPT_WBINVD,
  94         INTERCEPT_MONITOR,
  95         INTERCEPT_MWAIT,
  96         INTERCEPT_MWAIT_COND,
  97         INTERCEPT_XSETBV,
  98         INTERCEPT_RDPRU,
  99 };
 100
 101
 102 struct __attribute__ ((__packed__)) vmcb_control_area {
 103         u32 intercepts[MAX_INTERCEPT];
 104         u64 intercept;
 105         u8 reserved_1[40];
 106         u16 pause_filter_thresh;
 107         u16 pause_filter_count;
 108         u64 iopm_base_pa;
 109         u64 msrpm_base_pa;
 110         u64 tsc_offset;
 111         u32 asid;
 112         u8 tlb_ctl;
 113         u8 reserved_2[3];
 114         u32 int_ctl;
 115         u32 int_vector;
 116         u32 int_state;
 117         u8 reserved_3[4];
 118         u32 exit_code;
 119         u32 exit_code_hi;
 120         u64 exit_info_1;
 121         u64 exit_info_2;
 122         u32 exit_int_info;
 123         u32 exit_int_info_err;
 124         u64 nested_ctl;
 125         u64 avic_vapic_bar;
 126         u8 reserved_4[8];
 127         u32 event_inj;
 128         u32 event_inj_err;
 129         u64 nested_cr3;
 130         u64 virt_ext;
 131         u32 clean;
 132         u32 reserved_5;
 133         u64 next_rip;
 134         u8 insn_len;
 135         u8 insn_bytes[15];
 136         u64 avic_backing_page;  /* Offset 0xe0 */
 137         u8 reserved_6[8];       /* Offset 0xe8 */
 138         u64 avic_logical_id;    /* Offset 0xf0 */
 139         u64 avic_physical_id;   /* Offset 0xf8 */
 140 };
 141
 142
 143 #define TLB_CONTROL_DO_NOTHING 0
 144 #define TLB_CONTROL_FLUSH_ALL_ASID 1
 145 #define TLB_CONTROL_FLUSH_ASID 3
 146 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
 147
 148 #define V_TPR_MASK 0x0f
 149
 150 #define V_IRQ_SHIFT 8
 151 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
 152
 153 #define V_GIF_SHIFT 9
 154 #define V_GIF_MASK (1 << V_GIF_SHIFT)
 155
 156 #define V_INTR_PRIO_SHIFT 16
 157 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
 158
 159 #define V_IGN_TPR_SHIFT 20
 160 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
 161
 162 #define V_INTR_MASKING_SHIFT 24
 163 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
 164
 165 #define V_GIF_ENABLE_SHIFT 25
 166 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
 167
 168 #define AVIC_ENABLE_SHIFT 31
 169 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
 170
 171 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
 172 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
 173
 174 #define SVM_INTERRUPT_SHADOW_MASK 1
 175
 176 #define SVM_IOIO_STR_SHIFT 2
 177 #define SVM_IOIO_REP_SHIFT 3
 178 #define SVM_IOIO_SIZE_SHIFT 4
 179 #define SVM_IOIO_ASIZE_SHIFT 7
 180
 181 #define SVM_IOIO_TYPE_MASK 1
 182 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
 183 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
 184 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
 185 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
 186
 187 #define SVM_VM_CR_VALID_MASK    0x001fULL
 188 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
 189 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
 190
 191 #define SVM_NESTED_CTL_NP_ENABLE        BIT(0)
 192 #define SVM_NESTED_CTL_SEV_ENABLE       BIT(1)
 193
 194 struct vmcb_seg {
 195         u16 selector;
 196         u16 attrib;
 197         u32 limit;
 198         u64 base;
 199 } __packed;
 200
 201 struct vmcb_save_area {
 202         struct vmcb_seg es;
 203         struct vmcb_seg cs;
 204         struct vmcb_seg ss;
 205         struct vmcb_seg ds;
 206         struct vmcb_seg fs;
 207         struct vmcb_seg gs;
 208         struct vmcb_seg gdtr;
 209         struct vmcb_seg ldtr;
 210         struct vmcb_seg idtr;
 211         struct vmcb_seg tr;
 212         u8 reserved_1[43];
 213         u8 cpl;
 214         u8 reserved_2[4];
 215         u64 efer;
 216         u8 reserved_3[112];
 217         u64 cr4;
 218         u64 cr3;
 219         u64 cr0;
 220         u64 dr7;
 221         u64 dr6;
 222         u64 rflags;
 223         u64 rip;
 224         u8 reserved_4[88];
 225         u64 rsp;
 226         u8 reserved_5[24];
 227         u64 rax;
 228         u64 star;
 229         u64 lstar;
 230         u64 cstar;
 231         u64 sfmask;
 232         u64 kernel_gs_base;
 233         u64 sysenter_cs;
 234         u64 sysenter_esp;
 235         u64 sysenter_eip;
 236         u64 cr2;
 237         u8 reserved_6[32];
 238         u64 g_pat;
 239         u64 dbgctl;
 240         u64 br_from;
 241         u64 br_to;
 242         u64 last_excp_from;
 243         u64 last_excp_to;
 244
 245         /*
 246          * The following part of the save area is valid only for
 247          * SEV-ES guests when referenced through the GHCB.
 248          */
 249         u8 reserved_7[104];
 250         u64 reserved_8;         /* rax already available at 0x01f8 */
 251         u64 rcx;
 252         u64 rdx;
 253         u64 rbx;
 254         u64 reserved_9;         /* rsp already available at 0x01d8 */
 255         u64 rbp;
 256         u64 rsi;
 257         u64 rdi;
 258         u64 r8;
 259         u64 r9;
 260         u64 r10;
 261         u64 r11;
 262         u64 r12;
 263         u64 r13;
 264         u64 r14;
 265         u64 r15;
 266         u8 reserved_10[16];
 267         u64 sw_exit_code;
 268         u64 sw_exit_info_1;
 269         u64 sw_exit_info_2;
 270         u64 sw_scratch;
 271         u8 reserved_11[56];
 272         u64 xcr0;
 273         u8 valid_bitmap[16];
 274         u64 x87_state_gpa;
 275 } __packed;
 276
 277 struct ghcb {
 278         struct vmcb_save_area save;
 279         u8 reserved_save[2048 - sizeof(struct vmcb_save_area)];
 280
 281         u8 shared_buffer[2032];
 282
 283         u8 reserved_1[10];
 284         u16 protocol_version;   /* negotiated SEV-ES/GHCB protocol version */
 285         u32 ghcb_usage;
 286 } __packed;
 287
 288
 289 #define EXPECTED_VMCB_SAVE_AREA_SIZE            1032
 290 #define EXPECTED_VMCB_CONTROL_AREA_SIZE         256
 291 #define EXPECTED_GHCB_SIZE                      PAGE_SIZE
 292
 293 static inline void __unused_size_checks(void)
 294 {
 295         BUILD_BUG_ON(sizeof(struct vmcb_save_area)      != EXPECTED_VMCB_SAVE_AREA_SIZE);
 296         BUILD_BUG_ON(sizeof(struct vmcb_control_area)   != EXPECTED_VMCB_CONTROL_AREA_SIZE);
 297         BUILD_BUG_ON(sizeof(struct ghcb)                != EXPECTED_GHCB_SIZE);
 298 }
 299
 300 struct vmcb {
 301         struct vmcb_control_area control;
 302         u8 reserved_control[1024 - sizeof(struct vmcb_control_area)];
 303         struct vmcb_save_area save;
 304 } __packed;
 305
 306 #define SVM_CPUID_FUNC 0x8000000a
 307
 308 #define SVM_VM_CR_SVM_DISABLE 4
 309
 310 #define SVM_SELECTOR_S_SHIFT 4
 311 #define SVM_SELECTOR_DPL_SHIFT 5
 312 #define SVM_SELECTOR_P_SHIFT 7
 313 #define SVM_SELECTOR_AVL_SHIFT 8
 314 #define SVM_SELECTOR_L_SHIFT 9
 315 #define SVM_SELECTOR_DB_SHIFT 10
 316 #define SVM_SELECTOR_G_SHIFT 11
 317
 318 #define SVM_SELECTOR_TYPE_MASK (0xf)
 319 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
 320 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
 321 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
 322 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
 323 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
 324 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
 325 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
 326
 327 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
 328 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
 329 #define SVM_SELECTOR_CODE_MASK (1 << 3)
 330
 331 #define SVM_EVTINJ_VEC_MASK 0xff
 332
 333 #define SVM_EVTINJ_TYPE_SHIFT 8
 334 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
 335
 336 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
 337 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
 338 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
 339 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
 340
 341 #define SVM_EVTINJ_VALID (1 << 31)
 342 #define SVM_EVTINJ_VALID_ERR (1 << 11)
 343
 344 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
 345 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
 346
 347 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
 348 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
 349 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
 350 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
 351
 352 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
 353 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
 354
 355 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
 356 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
 357 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
 358
 359 #define SVM_EXITINFO_REG_MASK 0x0F
 360
 361 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
 362
 363 /* GHCB Accessor functions */
 364
 365 #define GHCB_BITMAP_IDX(field)                                                  \
 366         (offsetof(struct vmcb_save_area, field) / sizeof(u64))
 367
 368 #define DEFINE_GHCB_ACCESSORS(field)                                            \
 369         static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb)     \
 370         {                                                                       \
 371                 return test_bit(GHCB_BITMAP_IDX(field),                         \
 372                                 (unsigned long *)&ghcb->save.valid_bitmap);     \
 373         }                                                                       \
 374                                                                                 \
 375         static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value)       \
 376         {                                                                       \
 377                 __set_bit(GHCB_BITMAP_IDX(field),                               \
 378                           (unsigned long *)&ghcb->save.valid_bitmap);           \
 379                 ghcb->save.field = value;                                       \
 380         }
 381
 382 DEFINE_GHCB_ACCESSORS(cpl)
 383 DEFINE_GHCB_ACCESSORS(rip)
 384 DEFINE_GHCB_ACCESSORS(rsp)
 385 DEFINE_GHCB_ACCESSORS(rax)
 386 DEFINE_GHCB_ACCESSORS(rcx)
 387 DEFINE_GHCB_ACCESSORS(rdx)
 388 DEFINE_GHCB_ACCESSORS(rbx)
 389 DEFINE_GHCB_ACCESSORS(rbp)
 390 DEFINE_GHCB_ACCESSORS(rsi)
 391 DEFINE_GHCB_ACCESSORS(rdi)
 392 DEFINE_GHCB_ACCESSORS(r8)
 393 DEFINE_GHCB_ACCESSORS(r9)
 394 DEFINE_GHCB_ACCESSORS(r10)
 395 DEFINE_GHCB_ACCESSORS(r11)
 396 DEFINE_GHCB_ACCESSORS(r12)
 397 DEFINE_GHCB_ACCESSORS(r13)
 398 DEFINE_GHCB_ACCESSORS(r14)
 399 DEFINE_GHCB_ACCESSORS(r15)
 400 DEFINE_GHCB_ACCESSORS(sw_exit_code)
 401 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
 402 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
 403 DEFINE_GHCB_ACCESSORS(sw_scratch)
 404 DEFINE_GHCB_ACCESSORS(xcr0)
 405
 406 #endif