4 #include <uapi/asm/svm.h>
13 INTERCEPT_SELECTIVE_CR0
,
37 INTERCEPT_TASK_SWITCH
,
38 INTERCEPT_FERR_FREEZE
,
57 struct __attribute__ ((__packed__
)) vmcb_control_area
{
60 u32 intercept_exceptions
;
63 u16 pause_filter_count
;
79 u32 exit_int_info_err
;
92 u64 avic_backing_page
; /* Offset 0xe0 */
93 u8 reserved_6
[8]; /* Offset 0xe8 */
94 u64 avic_logical_id
; /* Offset 0xf0 */
95 u64 avic_physical_id
; /* Offset 0xf8 */
100 #define TLB_CONTROL_DO_NOTHING 0
101 #define TLB_CONTROL_FLUSH_ALL_ASID 1
102 #define TLB_CONTROL_FLUSH_ASID 3
103 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
105 #define V_TPR_MASK 0x0f
107 #define V_IRQ_SHIFT 8
108 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
110 #define V_INTR_PRIO_SHIFT 16
111 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
113 #define V_IGN_TPR_SHIFT 20
114 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
116 #define V_INTR_MASKING_SHIFT 24
117 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
119 #define AVIC_ENABLE_SHIFT 31
120 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
122 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
123 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
125 #define SVM_INTERRUPT_SHADOW_MASK 1
127 #define SVM_IOIO_STR_SHIFT 2
128 #define SVM_IOIO_REP_SHIFT 3
129 #define SVM_IOIO_SIZE_SHIFT 4
130 #define SVM_IOIO_ASIZE_SHIFT 7
132 #define SVM_IOIO_TYPE_MASK 1
133 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
134 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
135 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
136 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
138 #define SVM_VM_CR_VALID_MASK 0x001fULL
139 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
140 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
142 struct __attribute__ ((__packed__
)) vmcb_seg
{
149 struct __attribute__ ((__packed__
)) vmcb_save_area
{
156 struct vmcb_seg gdtr
;
157 struct vmcb_seg ldtr
;
158 struct vmcb_seg idtr
;
194 struct __attribute__ ((__packed__
)) vmcb
{
195 struct vmcb_control_area control
;
196 struct vmcb_save_area save
;
199 #define SVM_CPUID_FUNC 0x8000000a
201 #define SVM_VM_CR_SVM_DISABLE 4
203 #define SVM_SELECTOR_S_SHIFT 4
204 #define SVM_SELECTOR_DPL_SHIFT 5
205 #define SVM_SELECTOR_P_SHIFT 7
206 #define SVM_SELECTOR_AVL_SHIFT 8
207 #define SVM_SELECTOR_L_SHIFT 9
208 #define SVM_SELECTOR_DB_SHIFT 10
209 #define SVM_SELECTOR_G_SHIFT 11
211 #define SVM_SELECTOR_TYPE_MASK (0xf)
212 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
213 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
214 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
215 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
216 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
217 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
218 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
220 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
221 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
222 #define SVM_SELECTOR_CODE_MASK (1 << 3)
224 #define INTERCEPT_CR0_READ 0
225 #define INTERCEPT_CR3_READ 3
226 #define INTERCEPT_CR4_READ 4
227 #define INTERCEPT_CR8_READ 8
228 #define INTERCEPT_CR0_WRITE (16 + 0)
229 #define INTERCEPT_CR3_WRITE (16 + 3)
230 #define INTERCEPT_CR4_WRITE (16 + 4)
231 #define INTERCEPT_CR8_WRITE (16 + 8)
233 #define INTERCEPT_DR0_READ 0
234 #define INTERCEPT_DR1_READ 1
235 #define INTERCEPT_DR2_READ 2
236 #define INTERCEPT_DR3_READ 3
237 #define INTERCEPT_DR4_READ 4
238 #define INTERCEPT_DR5_READ 5
239 #define INTERCEPT_DR6_READ 6
240 #define INTERCEPT_DR7_READ 7
241 #define INTERCEPT_DR0_WRITE (16 + 0)
242 #define INTERCEPT_DR1_WRITE (16 + 1)
243 #define INTERCEPT_DR2_WRITE (16 + 2)
244 #define INTERCEPT_DR3_WRITE (16 + 3)
245 #define INTERCEPT_DR4_WRITE (16 + 4)
246 #define INTERCEPT_DR5_WRITE (16 + 5)
247 #define INTERCEPT_DR6_WRITE (16 + 6)
248 #define INTERCEPT_DR7_WRITE (16 + 7)
250 #define SVM_EVTINJ_VEC_MASK 0xff
252 #define SVM_EVTINJ_TYPE_SHIFT 8
253 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
255 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
256 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
257 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
258 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
260 #define SVM_EVTINJ_VALID (1 << 31)
261 #define SVM_EVTINJ_VALID_ERR (1 << 11)
263 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
264 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
266 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
267 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
268 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
269 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
271 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
272 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
274 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
275 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
276 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
278 #define SVM_EXITINFO_REG_MASK 0x0F
280 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
282 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
283 #define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
284 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
285 #define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
286 #define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
287 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"