1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <uapi/asm/svm.h>
14 INTERCEPT_SELECTIVE_CR0
,
38 INTERCEPT_TASK_SWITCH
,
39 INTERCEPT_FERR_FREEZE
,
58 struct __attribute__ ((__packed__
)) vmcb_control_area
{
61 u32 intercept_exceptions
;
64 u16 pause_filter_count
;
80 u32 exit_int_info_err
;
93 u64 avic_backing_page
; /* Offset 0xe0 */
94 u8 reserved_6
[8]; /* Offset 0xe8 */
95 u64 avic_logical_id
; /* Offset 0xf0 */
96 u64 avic_physical_id
; /* Offset 0xf8 */
101 #define TLB_CONTROL_DO_NOTHING 0
102 #define TLB_CONTROL_FLUSH_ALL_ASID 1
103 #define TLB_CONTROL_FLUSH_ASID 3
104 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
106 #define V_TPR_MASK 0x0f
108 #define V_IRQ_SHIFT 8
109 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
111 #define V_GIF_SHIFT 9
112 #define V_GIF_MASK (1 << V_GIF_SHIFT)
114 #define V_INTR_PRIO_SHIFT 16
115 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
117 #define V_IGN_TPR_SHIFT 20
118 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
120 #define V_INTR_MASKING_SHIFT 24
121 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
123 #define V_GIF_ENABLE_SHIFT 25
124 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
126 #define AVIC_ENABLE_SHIFT 31
127 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
129 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
130 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
132 #define SVM_INTERRUPT_SHADOW_MASK 1
134 #define SVM_IOIO_STR_SHIFT 2
135 #define SVM_IOIO_REP_SHIFT 3
136 #define SVM_IOIO_SIZE_SHIFT 4
137 #define SVM_IOIO_ASIZE_SHIFT 7
139 #define SVM_IOIO_TYPE_MASK 1
140 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
141 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
142 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
143 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
145 #define SVM_VM_CR_VALID_MASK 0x001fULL
146 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
147 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
149 struct __attribute__ ((__packed__
)) vmcb_seg
{
156 struct __attribute__ ((__packed__
)) vmcb_save_area
{
163 struct vmcb_seg gdtr
;
164 struct vmcb_seg ldtr
;
165 struct vmcb_seg idtr
;
201 struct __attribute__ ((__packed__
)) vmcb
{
202 struct vmcb_control_area control
;
203 struct vmcb_save_area save
;
206 #define SVM_CPUID_FUNC 0x8000000a
208 #define SVM_VM_CR_SVM_DISABLE 4
210 #define SVM_SELECTOR_S_SHIFT 4
211 #define SVM_SELECTOR_DPL_SHIFT 5
212 #define SVM_SELECTOR_P_SHIFT 7
213 #define SVM_SELECTOR_AVL_SHIFT 8
214 #define SVM_SELECTOR_L_SHIFT 9
215 #define SVM_SELECTOR_DB_SHIFT 10
216 #define SVM_SELECTOR_G_SHIFT 11
218 #define SVM_SELECTOR_TYPE_MASK (0xf)
219 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
220 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
221 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
222 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
223 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
224 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
225 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
227 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
228 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
229 #define SVM_SELECTOR_CODE_MASK (1 << 3)
231 #define INTERCEPT_CR0_READ 0
232 #define INTERCEPT_CR3_READ 3
233 #define INTERCEPT_CR4_READ 4
234 #define INTERCEPT_CR8_READ 8
235 #define INTERCEPT_CR0_WRITE (16 + 0)
236 #define INTERCEPT_CR3_WRITE (16 + 3)
237 #define INTERCEPT_CR4_WRITE (16 + 4)
238 #define INTERCEPT_CR8_WRITE (16 + 8)
240 #define INTERCEPT_DR0_READ 0
241 #define INTERCEPT_DR1_READ 1
242 #define INTERCEPT_DR2_READ 2
243 #define INTERCEPT_DR3_READ 3
244 #define INTERCEPT_DR4_READ 4
245 #define INTERCEPT_DR5_READ 5
246 #define INTERCEPT_DR6_READ 6
247 #define INTERCEPT_DR7_READ 7
248 #define INTERCEPT_DR0_WRITE (16 + 0)
249 #define INTERCEPT_DR1_WRITE (16 + 1)
250 #define INTERCEPT_DR2_WRITE (16 + 2)
251 #define INTERCEPT_DR3_WRITE (16 + 3)
252 #define INTERCEPT_DR4_WRITE (16 + 4)
253 #define INTERCEPT_DR5_WRITE (16 + 5)
254 #define INTERCEPT_DR6_WRITE (16 + 6)
255 #define INTERCEPT_DR7_WRITE (16 + 7)
257 #define SVM_EVTINJ_VEC_MASK 0xff
259 #define SVM_EVTINJ_TYPE_SHIFT 8
260 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
262 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
263 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
264 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
265 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
267 #define SVM_EVTINJ_VALID (1 << 31)
268 #define SVM_EVTINJ_VALID_ERR (1 << 11)
270 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
271 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
273 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
274 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
275 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
276 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
278 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
279 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
281 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
282 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
283 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
285 #define SVM_EXITINFO_REG_MASK 0x0F
287 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
289 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
290 #define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
291 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
292 #define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
293 #define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
294 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"