1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_TLBFLUSH_H
3 #define _ASM_X86_TLBFLUSH_H
6 #include <linux/sched.h>
8 #include <asm/processor.h>
9 #include <asm/cpufeature.h>
10 #include <asm/special_insns.h>
12 #include <asm/invpcid.h>
14 #include <asm/processor-flags.h>
17 * The x86 feature is called PCID (Process Context IDentifier). It is similar
18 * to what is traditionally called ASID on the RISC processors.
20 * We don't use the traditional ASID implementation, where each process/mm gets
21 * its own ASID and flush/restart when we run out of ASID space.
23 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
24 * that came by on this CPU, allowing cheaper switch_mm between processes on
27 * We end up with different spaces for different things. To avoid confusion we
28 * use different names for each of them:
30 * ASID - [0, TLB_NR_DYN_ASIDS-1]
31 * the canonical identifier for an mm
33 * kPCID - [1, TLB_NR_DYN_ASIDS]
34 * the value we write into the PCID part of CR3; corresponds to the
35 * ASID+1, because PCID 0 is special.
37 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
38 * for KPTI each mm has two address spaces and thus needs two
39 * PCID values, but we can still do with a single ASID denomination
40 * for each mm. Corresponds to kPCID + 2048.
44 /* There are 12 bits of space for ASIDS in CR3 */
45 #define CR3_HW_ASID_BITS 12
48 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
49 * user/kernel switches
51 #ifdef CONFIG_PAGE_TABLE_ISOLATION
52 # define PTI_CONSUMED_PCID_BITS 1
54 # define PTI_CONSUMED_PCID_BITS 0
57 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
60 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
61 * for them being zero-based. Another -1 is because PCID 0 is reserved for
62 * use by non-PCID-aware users.
64 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
67 * 6 because 6 should be plenty and struct tlb_state will fit in two cache
70 #define TLB_NR_DYN_ASIDS 6
73 * Given @asid, compute kPCID
75 static inline u16
kern_pcid(u16 asid
)
77 VM_WARN_ON_ONCE(asid
> MAX_ASID_AVAILABLE
);
79 #ifdef CONFIG_PAGE_TABLE_ISOLATION
81 * Make sure that the dynamic ASID space does not confict with the
82 * bit we are using to switch between user and kernel ASIDs.
84 BUILD_BUG_ON(TLB_NR_DYN_ASIDS
>= (1 << X86_CR3_PTI_SWITCH_BIT
));
87 * The ASID being passed in here should have respected the
88 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
90 VM_WARN_ON_ONCE(asid
& (1 << X86_CR3_PTI_SWITCH_BIT
));
93 * The dynamically-assigned ASIDs that get passed in are small
94 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
95 * so do not bother to clear it.
97 * If PCID is on, ASID-aware code paths put the ASID+1 into the
98 * PCID bits. This serves two purposes. It prevents a nasty
99 * situation in which PCID-unaware code saves CR3, loads some other
100 * value (with PCID == 0), and then restores CR3, thus corrupting
101 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
102 * that any bugs involving loading a PCID-enabled CR3 with
103 * CR4.PCIDE off will trigger deterministically.
109 * Given @asid, compute uPCID
111 static inline u16
user_pcid(u16 asid
)
113 u16 ret
= kern_pcid(asid
);
114 #ifdef CONFIG_PAGE_TABLE_ISOLATION
115 ret
|= 1 << X86_CR3_PTI_SWITCH_BIT
;
121 static inline unsigned long build_cr3(pgd_t
*pgd
, u16 asid
)
123 if (static_cpu_has(X86_FEATURE_PCID
)) {
124 return __sme_pa(pgd
) | kern_pcid(asid
);
126 VM_WARN_ON_ONCE(asid
!= 0);
127 return __sme_pa(pgd
);
131 static inline unsigned long build_cr3_noflush(pgd_t
*pgd
, u16 asid
)
133 VM_WARN_ON_ONCE(asid
> MAX_ASID_AVAILABLE
);
134 VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID
));
135 return __sme_pa(pgd
) | kern_pcid(asid
) | CR3_NOFLUSH
;
138 #ifdef CONFIG_PARAVIRT
139 #include <asm/paravirt.h>
141 #define __flush_tlb() __native_flush_tlb()
142 #define __flush_tlb_global() __native_flush_tlb_global()
143 #define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
146 static inline bool tlb_defer_switch_to_init_mm(void)
149 * If we have PCID, then switching to init_mm is reasonably
150 * fast. If we don't have PCID, then switching to init_mm is
151 * quite slow, so we try to defer it in the hopes that we can
152 * avoid it entirely. The latter approach runs the risk of
153 * receiving otherwise unnecessary IPIs.
155 * This choice is just a heuristic. The tlb code can handle this
156 * function returning true or false regardless of whether we have
159 return !static_cpu_has(X86_FEATURE_PCID
);
169 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
170 * are on. This means that it may not match current->active_mm,
171 * which will contain the previous user mm when we're in lazy TLB
172 * mode even if we've already switched back to swapper_pg_dir.
174 struct mm_struct
*loaded_mm
;
179 * We can be in one of several states:
181 * - Actively using an mm. Our CPU's bit will be set in
182 * mm_cpumask(loaded_mm) and is_lazy == false;
184 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
185 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
187 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
188 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
189 * We're heuristically guessing that the CR3 load we
190 * skipped more than makes up for the overhead added by
196 * If set we changed the page tables in such a way that we
197 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
198 * This tells us to go invalidate all the non-loaded ctxs[]
199 * on the next context switch.
201 * The current ctx was kept up-to-date as it ran and does not
202 * need to be invalidated.
204 bool invalidate_other
;
207 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
208 * the corresponding user PCID needs a flush next time we
209 * switch to it; see SWITCH_TO_USER_CR3.
211 unsigned short user_pcid_flush_mask
;
214 * Access to this CR4 shadow and to H/W CR4 is protected by
215 * disabling interrupts when modifying either one.
220 * This is a list of all contexts that might exist in the TLB.
221 * There is one per ASID that we use, and the ASID (what the
222 * CPU calls PCID) is the index into ctxts.
224 * For each context, ctx_id indicates which mm the TLB's user
225 * entries came from. As an invariant, the TLB will never
226 * contain entries that are out-of-date as when that mm reached
227 * the tlb_gen in the list.
229 * To be clear, this means that it's legal for the TLB code to
230 * flush the TLB without updating tlb_gen. This can happen
231 * (for now, at least) due to paravirt remote flushes.
233 * NB: context 0 is a bit special, since it's also used by
234 * various bits of init code. This is fine -- code that
235 * isn't aware of PCID will end up harmlessly flushing
238 struct tlb_context ctxs
[TLB_NR_DYN_ASIDS
];
240 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
);
242 /* Initialize cr4 shadow for this CPU. */
243 static inline void cr4_init_shadow(void)
245 this_cpu_write(cpu_tlbstate
.cr4
, __read_cr4());
248 static inline void __cr4_set(unsigned long cr4
)
250 lockdep_assert_irqs_disabled();
251 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
255 /* Set in this cpu's CR4. */
256 static inline void cr4_set_bits(unsigned long mask
)
258 unsigned long cr4
, flags
;
260 local_irq_save(flags
);
261 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
262 if ((cr4
| mask
) != cr4
)
263 __cr4_set(cr4
| mask
);
264 local_irq_restore(flags
);
267 /* Clear in this cpu's CR4. */
268 static inline void cr4_clear_bits(unsigned long mask
)
270 unsigned long cr4
, flags
;
272 local_irq_save(flags
);
273 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
274 if ((cr4
& ~mask
) != cr4
)
275 __cr4_set(cr4
& ~mask
);
276 local_irq_restore(flags
);
279 static inline void cr4_toggle_bits_irqsoff(unsigned long mask
)
283 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
284 __cr4_set(cr4
^ mask
);
287 /* Read the CR4 shadow. */
288 static inline unsigned long cr4_read_shadow(void)
290 return this_cpu_read(cpu_tlbstate
.cr4
);
294 * Mark all other ASIDs as invalid, preserves the current.
296 static inline void invalidate_other_asid(void)
298 this_cpu_write(cpu_tlbstate
.invalidate_other
, true);
302 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
303 * enable and PPro Global page enable), so that any CPU's that boot
304 * up after us can get the correct flags. This should only be used
305 * during boot on the boot cpu.
307 extern unsigned long mmu_cr4_features
;
308 extern u32
*trampoline_cr4_features
;
310 static inline void cr4_set_bits_and_update_boot(unsigned long mask
)
312 mmu_cr4_features
|= mask
;
313 if (trampoline_cr4_features
)
314 *trampoline_cr4_features
= mmu_cr4_features
;
318 extern void initialize_tlbstate_and_flush(void);
321 * Given an ASID, flush the corresponding user ASID. We can delay this
322 * until the next time we switch to it.
324 * See SWITCH_TO_USER_CR3.
326 static inline void invalidate_user_asid(u16 asid
)
328 /* There is no user ASID if address space separation is off */
329 if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION
))
333 * We only have a single ASID if PCID is off and the CR3
334 * write will have flushed it.
336 if (!cpu_feature_enabled(X86_FEATURE_PCID
))
339 if (!static_cpu_has(X86_FEATURE_PTI
))
342 __set_bit(kern_pcid(asid
),
343 (unsigned long *)this_cpu_ptr(&cpu_tlbstate
.user_pcid_flush_mask
));
347 * flush the entire current user mapping
349 static inline void __native_flush_tlb(void)
351 invalidate_user_asid(this_cpu_read(cpu_tlbstate
.loaded_mm_asid
));
353 * If current->mm == NULL then we borrow a mm which may change
354 * during a task switch and therefore we must not be preempted
355 * while we write CR3 back:
358 native_write_cr3(__native_read_cr3());
365 static inline void __native_flush_tlb_global(void)
367 unsigned long cr4
, flags
;
369 if (static_cpu_has(X86_FEATURE_INVPCID
)) {
371 * Using INVPCID is considerably faster than a pair of writes
372 * to CR4 sandwiched inside an IRQ flag save/restore.
374 * Note, this works with CR4.PCIDE=0 or 1.
381 * Read-modify-write to CR4 - protect it from preemption and
382 * from interrupts. (Use the raw variant because this code can
383 * be called from deep inside debugging code.)
385 raw_local_irq_save(flags
);
387 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
389 native_write_cr4(cr4
^ X86_CR4_PGE
);
390 /* write old PGE again and flush TLBs */
391 native_write_cr4(cr4
);
393 raw_local_irq_restore(flags
);
397 * flush one page in the user mapping
399 static inline void __native_flush_tlb_single(unsigned long addr
)
401 u32 loaded_mm_asid
= this_cpu_read(cpu_tlbstate
.loaded_mm_asid
);
403 asm volatile("invlpg (%0)" ::"r" (addr
) : "memory");
405 if (!static_cpu_has(X86_FEATURE_PTI
))
409 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
410 * Just use invalidate_user_asid() in case we are called early.
412 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE
))
413 invalidate_user_asid(loaded_mm_asid
);
415 invpcid_flush_one(user_pcid(loaded_mm_asid
), addr
);
421 static inline void __flush_tlb_all(void)
423 if (boot_cpu_has(X86_FEATURE_PGE
)) {
424 __flush_tlb_global();
427 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
434 * flush one page in the kernel mapping
436 static inline void __flush_tlb_one(unsigned long addr
)
438 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE
);
439 __flush_tlb_single(addr
);
441 if (!static_cpu_has(X86_FEATURE_PTI
))
445 * __flush_tlb_single() will have cleared the TLB entry for this ASID,
446 * but since kernel space is replicated across all, we must also
447 * invalidate all others.
449 invalidate_other_asid();
452 #define TLB_FLUSH_ALL -1UL
457 * - flush_tlb_all() flushes all processes TLBs
458 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
459 * - flush_tlb_page(vma, vmaddr) flushes one page
460 * - flush_tlb_range(vma, start, end) flushes a range of pages
461 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
462 * - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
464 * ..but the i386 has somewhat limited tlb flushing capabilities,
465 * and page-granular flushes are available only on i486 and up.
467 struct flush_tlb_info
{
469 * We support several kinds of flushes.
471 * - Fully flush a single mm. .mm will be set, .end will be
472 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
473 * which the IPI sender is trying to catch us up.
475 * - Partially flush a single mm. .mm will be set, .start and
476 * .end will indicate the range, and .new_tlb_gen will be set
477 * such that the changes between generation .new_tlb_gen-1 and
478 * .new_tlb_gen are entirely contained in the indicated range.
480 * - Fully flush all mms whose tlb_gens have been updated. .mm
481 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
484 struct mm_struct
*mm
;
490 #define local_flush_tlb() __flush_tlb()
492 #define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
494 #define flush_tlb_range(vma, start, end) \
495 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
497 extern void flush_tlb_all(void);
498 extern void flush_tlb_mm_range(struct mm_struct
*mm
, unsigned long start
,
499 unsigned long end
, unsigned long vmflag
);
500 extern void flush_tlb_kernel_range(unsigned long start
, unsigned long end
);
502 static inline void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long a
)
504 flush_tlb_mm_range(vma
->vm_mm
, a
, a
+ PAGE_SIZE
, VM_NONE
);
507 void native_flush_tlb_others(const struct cpumask
*cpumask
,
508 const struct flush_tlb_info
*info
);
510 static inline u64
inc_mm_tlb_gen(struct mm_struct
*mm
)
513 * Bump the generation count. This also serves as a full barrier
514 * that synchronizes with switch_mm(): callers are required to order
515 * their read of mm_cpumask after their writes to the paging
518 return atomic64_inc_return(&mm
->context
.tlb_gen
);
521 static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch
*batch
,
522 struct mm_struct
*mm
)
525 cpumask_or(&batch
->cpumask
, &batch
->cpumask
, mm_cpumask(mm
));
528 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch
*batch
);
530 #ifndef CONFIG_PARAVIRT
531 #define flush_tlb_others(mask, info) \
532 native_flush_tlb_others(mask, info)
535 #endif /* _ASM_X86_TLBFLUSH_H */