1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_TLBFLUSH_H
3 #define _ASM_X86_TLBFLUSH_H
6 #include <linux/sched.h>
8 #include <asm/processor.h>
9 #include <asm/cpufeature.h>
10 #include <asm/special_insns.h>
12 #include <asm/invpcid.h>
14 #include <asm/processor-flags.h>
16 static inline u64
inc_mm_tlb_gen(struct mm_struct
*mm
)
19 * Bump the generation count. This also serves as a full barrier
20 * that synchronizes with switch_mm(): callers are required to order
21 * their read of mm_cpumask after their writes to the paging
24 return atomic64_inc_return(&mm
->context
.tlb_gen
);
27 /* There are 12 bits of space for ASIDS in CR3 */
28 #define CR3_HW_ASID_BITS 12
31 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
32 * user/kernel switches
34 #ifdef CONFIG_PAGE_TABLE_ISOLATION
35 # define PTI_CONSUMED_PCID_BITS 1
37 # define PTI_CONSUMED_PCID_BITS 0
40 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
43 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
44 * for them being zero-based. Another -1 is because ASID 0 is reserved for
45 * use by non-PCID-aware users.
47 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
50 * 6 because 6 should be plenty and struct tlb_state will fit in two cache
53 #define TLB_NR_DYN_ASIDS 6
55 static inline u16
kern_pcid(u16 asid
)
57 VM_WARN_ON_ONCE(asid
> MAX_ASID_AVAILABLE
);
59 #ifdef CONFIG_PAGE_TABLE_ISOLATION
61 * Make sure that the dynamic ASID space does not confict with the
62 * bit we are using to switch between user and kernel ASIDs.
64 BUILD_BUG_ON(TLB_NR_DYN_ASIDS
>= (1 << X86_CR3_PTI_SWITCH_BIT
));
67 * The ASID being passed in here should have respected the
68 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
70 VM_WARN_ON_ONCE(asid
& (1 << X86_CR3_PTI_SWITCH_BIT
));
73 * The dynamically-assigned ASIDs that get passed in are small
74 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
75 * so do not bother to clear it.
77 * If PCID is on, ASID-aware code paths put the ASID+1 into the
78 * PCID bits. This serves two purposes. It prevents a nasty
79 * situation in which PCID-unaware code saves CR3, loads some other
80 * value (with PCID == 0), and then restores CR3, thus corrupting
81 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
82 * that any bugs involving loading a PCID-enabled CR3 with
83 * CR4.PCIDE off will trigger deterministically.
89 * The user PCID is just the kernel one, plus the "switch bit".
91 static inline u16
user_pcid(u16 asid
)
93 u16 ret
= kern_pcid(asid
);
94 #ifdef CONFIG_PAGE_TABLE_ISOLATION
95 ret
|= 1 << X86_CR3_PTI_SWITCH_BIT
;
101 static inline unsigned long build_cr3(pgd_t
*pgd
, u16 asid
)
103 if (static_cpu_has(X86_FEATURE_PCID
)) {
104 return __sme_pa(pgd
) | kern_pcid(asid
);
106 VM_WARN_ON_ONCE(asid
!= 0);
107 return __sme_pa(pgd
);
111 static inline unsigned long build_cr3_noflush(pgd_t
*pgd
, u16 asid
)
113 VM_WARN_ON_ONCE(asid
> MAX_ASID_AVAILABLE
);
114 VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID
));
115 return __sme_pa(pgd
) | kern_pcid(asid
) | CR3_NOFLUSH
;
118 #ifdef CONFIG_PARAVIRT
119 #include <asm/paravirt.h>
121 #define __flush_tlb() __native_flush_tlb()
122 #define __flush_tlb_global() __native_flush_tlb_global()
123 #define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
126 static inline bool tlb_defer_switch_to_init_mm(void)
129 * If we have PCID, then switching to init_mm is reasonably
130 * fast. If we don't have PCID, then switching to init_mm is
131 * quite slow, so we try to defer it in the hopes that we can
132 * avoid it entirely. The latter approach runs the risk of
133 * receiving otherwise unnecessary IPIs.
135 * This choice is just a heuristic. The tlb code can handle this
136 * function returning true or false regardless of whether we have
139 return !static_cpu_has(X86_FEATURE_PCID
);
149 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
150 * are on. This means that it may not match current->active_mm,
151 * which will contain the previous user mm when we're in lazy TLB
152 * mode even if we've already switched back to swapper_pg_dir.
154 struct mm_struct
*loaded_mm
;
159 * We can be in one of several states:
161 * - Actively using an mm. Our CPU's bit will be set in
162 * mm_cpumask(loaded_mm) and is_lazy == false;
164 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
165 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
167 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
168 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
169 * We're heuristically guessing that the CR3 load we
170 * skipped more than makes up for the overhead added by
176 * If set we changed the page tables in such a way that we
177 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
178 * This tells us to go invalidate all the non-loaded ctxs[]
179 * on the next context switch.
181 * The current ctx was kept up-to-date as it ran and does not
182 * need to be invalidated.
184 bool invalidate_other
;
187 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
188 * the corresponding user PCID needs a flush next time we
189 * switch to it; see SWITCH_TO_USER_CR3.
191 unsigned short user_pcid_flush_mask
;
194 * Access to this CR4 shadow and to H/W CR4 is protected by
195 * disabling interrupts when modifying either one.
200 * This is a list of all contexts that might exist in the TLB.
201 * There is one per ASID that we use, and the ASID (what the
202 * CPU calls PCID) is the index into ctxts.
204 * For each context, ctx_id indicates which mm the TLB's user
205 * entries came from. As an invariant, the TLB will never
206 * contain entries that are out-of-date as when that mm reached
207 * the tlb_gen in the list.
209 * To be clear, this means that it's legal for the TLB code to
210 * flush the TLB without updating tlb_gen. This can happen
211 * (for now, at least) due to paravirt remote flushes.
213 * NB: context 0 is a bit special, since it's also used by
214 * various bits of init code. This is fine -- code that
215 * isn't aware of PCID will end up harmlessly flushing
218 struct tlb_context ctxs
[TLB_NR_DYN_ASIDS
];
220 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
);
222 /* Initialize cr4 shadow for this CPU. */
223 static inline void cr4_init_shadow(void)
225 this_cpu_write(cpu_tlbstate
.cr4
, __read_cr4());
228 /* Set in this cpu's CR4. */
229 static inline void cr4_set_bits(unsigned long mask
)
233 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
234 if ((cr4
| mask
) != cr4
) {
236 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
241 /* Clear in this cpu's CR4. */
242 static inline void cr4_clear_bits(unsigned long mask
)
246 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
247 if ((cr4
& ~mask
) != cr4
) {
249 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
254 static inline void cr4_toggle_bits(unsigned long mask
)
258 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
260 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
264 /* Read the CR4 shadow. */
265 static inline unsigned long cr4_read_shadow(void)
267 return this_cpu_read(cpu_tlbstate
.cr4
);
271 * Mark all other ASIDs as invalid, preserves the current.
273 static inline void invalidate_other_asid(void)
275 this_cpu_write(cpu_tlbstate
.invalidate_other
, true);
279 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
280 * enable and PPro Global page enable), so that any CPU's that boot
281 * up after us can get the correct flags. This should only be used
282 * during boot on the boot cpu.
284 extern unsigned long mmu_cr4_features
;
285 extern u32
*trampoline_cr4_features
;
287 static inline void cr4_set_bits_and_update_boot(unsigned long mask
)
289 mmu_cr4_features
|= mask
;
290 if (trampoline_cr4_features
)
291 *trampoline_cr4_features
= mmu_cr4_features
;
295 extern void initialize_tlbstate_and_flush(void);
298 * Given an ASID, flush the corresponding user ASID. We can delay this
299 * until the next time we switch to it.
301 * See SWITCH_TO_USER_CR3.
303 static inline void invalidate_user_asid(u16 asid
)
305 /* There is no user ASID if address space separation is off */
306 if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION
))
310 * We only have a single ASID if PCID is off and the CR3
311 * write will have flushed it.
313 if (!cpu_feature_enabled(X86_FEATURE_PCID
))
316 if (!static_cpu_has(X86_FEATURE_PTI
))
319 __set_bit(kern_pcid(asid
),
320 (unsigned long *)this_cpu_ptr(&cpu_tlbstate
.user_pcid_flush_mask
));
324 * flush the entire current user mapping
326 static inline void __native_flush_tlb(void)
328 invalidate_user_asid(this_cpu_read(cpu_tlbstate
.loaded_mm_asid
));
330 * If current->mm == NULL then we borrow a mm which may change
331 * during a task switch and therefore we must not be preempted
332 * while we write CR3 back:
335 native_write_cr3(__native_read_cr3());
342 static inline void __native_flush_tlb_global(void)
344 unsigned long cr4
, flags
;
346 if (static_cpu_has(X86_FEATURE_INVPCID
)) {
348 * Using INVPCID is considerably faster than a pair of writes
349 * to CR4 sandwiched inside an IRQ flag save/restore.
351 * Note, this works with CR4.PCIDE=0 or 1.
358 * Read-modify-write to CR4 - protect it from preemption and
359 * from interrupts. (Use the raw variant because this code can
360 * be called from deep inside debugging code.)
362 raw_local_irq_save(flags
);
364 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
366 native_write_cr4(cr4
^ X86_CR4_PGE
);
367 /* write old PGE again and flush TLBs */
368 native_write_cr4(cr4
);
370 raw_local_irq_restore(flags
);
374 * flush one page in the user mapping
376 static inline void __native_flush_tlb_single(unsigned long addr
)
378 u32 loaded_mm_asid
= this_cpu_read(cpu_tlbstate
.loaded_mm_asid
);
380 asm volatile("invlpg (%0)" ::"r" (addr
) : "memory");
382 if (!static_cpu_has(X86_FEATURE_PTI
))
386 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
387 * Just use invalidate_user_asid() in case we are called early.
389 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE
))
390 invalidate_user_asid(loaded_mm_asid
);
392 invpcid_flush_one(user_pcid(loaded_mm_asid
), addr
);
398 static inline void __flush_tlb_all(void)
400 if (boot_cpu_has(X86_FEATURE_PGE
)) {
401 __flush_tlb_global();
404 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
411 * flush one page in the kernel mapping
413 static inline void __flush_tlb_one(unsigned long addr
)
415 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE
);
416 __flush_tlb_single(addr
);
418 if (!static_cpu_has(X86_FEATURE_PTI
))
422 * __flush_tlb_single() will have cleared the TLB entry for this ASID,
423 * but since kernel space is replicated across all, we must also
424 * invalidate all others.
426 invalidate_other_asid();
429 #define TLB_FLUSH_ALL -1UL
434 * - flush_tlb_all() flushes all processes TLBs
435 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
436 * - flush_tlb_page(vma, vmaddr) flushes one page
437 * - flush_tlb_range(vma, start, end) flushes a range of pages
438 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
439 * - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
441 * ..but the i386 has somewhat limited tlb flushing capabilities,
442 * and page-granular flushes are available only on i486 and up.
444 struct flush_tlb_info
{
446 * We support several kinds of flushes.
448 * - Fully flush a single mm. .mm will be set, .end will be
449 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
450 * which the IPI sender is trying to catch us up.
452 * - Partially flush a single mm. .mm will be set, .start and
453 * .end will indicate the range, and .new_tlb_gen will be set
454 * such that the changes between generation .new_tlb_gen-1 and
455 * .new_tlb_gen are entirely contained in the indicated range.
457 * - Fully flush all mms whose tlb_gens have been updated. .mm
458 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
461 struct mm_struct
*mm
;
467 #define local_flush_tlb() __flush_tlb()
469 #define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
471 #define flush_tlb_range(vma, start, end) \
472 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
474 extern void flush_tlb_all(void);
475 extern void flush_tlb_mm_range(struct mm_struct
*mm
, unsigned long start
,
476 unsigned long end
, unsigned long vmflag
);
477 extern void flush_tlb_kernel_range(unsigned long start
, unsigned long end
);
479 static inline void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long a
)
481 flush_tlb_mm_range(vma
->vm_mm
, a
, a
+ PAGE_SIZE
, VM_NONE
);
484 void native_flush_tlb_others(const struct cpumask
*cpumask
,
485 const struct flush_tlb_info
*info
);
487 static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch
*batch
,
488 struct mm_struct
*mm
)
491 cpumask_or(&batch
->cpumask
, &batch
->cpumask
, mm_cpumask(mm
));
494 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch
*batch
);
496 #ifndef CONFIG_PARAVIRT
497 #define flush_tlb_others(mask, info) \
498 native_flush_tlb_others(mask, info)
501 #endif /* _ASM_X86_TLBFLUSH_H */