1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_TLBFLUSH_H
3 #define _ASM_X86_TLBFLUSH_H
6 #include <linux/sched.h>
8 #include <asm/processor.h>
9 #include <asm/cpufeature.h>
10 #include <asm/special_insns.h>
13 static inline void __invpcid(unsigned long pcid
, unsigned long addr
,
16 struct { u64 d
[2]; } desc
= { { pcid
, addr
} };
19 * The memory clobber is because the whole point is to invalidate
20 * stale TLB entries and, especially if we're flushing global
21 * mappings, we don't want the compiler to reorder any subsequent
22 * memory accesses before the TLB flush.
24 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
25 * invpcid (%rcx), %rax in long mode.
27 asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
28 : : "m" (desc
), "a" (type
), "c" (&desc
) : "memory");
31 #define INVPCID_TYPE_INDIV_ADDR 0
32 #define INVPCID_TYPE_SINGLE_CTXT 1
33 #define INVPCID_TYPE_ALL_INCL_GLOBAL 2
34 #define INVPCID_TYPE_ALL_NON_GLOBAL 3
36 /* Flush all mappings for a given pcid and addr, not including globals. */
37 static inline void invpcid_flush_one(unsigned long pcid
,
40 __invpcid(pcid
, addr
, INVPCID_TYPE_INDIV_ADDR
);
43 /* Flush all mappings for a given PCID, not including globals. */
44 static inline void invpcid_flush_single_context(unsigned long pcid
)
46 __invpcid(pcid
, 0, INVPCID_TYPE_SINGLE_CTXT
);
49 /* Flush all mappings, including globals, for all PCIDs. */
50 static inline void invpcid_flush_all(void)
52 __invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL
);
55 /* Flush all mappings for all PCIDs except globals. */
56 static inline void invpcid_flush_all_nonglobals(void)
58 __invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL
);
61 static inline u64
inc_mm_tlb_gen(struct mm_struct
*mm
)
64 * Bump the generation count. This also serves as a full barrier
65 * that synchronizes with switch_mm(): callers are required to order
66 * their read of mm_cpumask after their writes to the paging
69 return atomic64_inc_return(&mm
->context
.tlb_gen
);
72 /* There are 12 bits of space for ASIDS in CR3 */
73 #define CR3_HW_ASID_BITS 12
75 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
76 * user/kernel switches
78 #define PTI_CONSUMED_ASID_BITS 0
80 #define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS - PTI_CONSUMED_ASID_BITS)
82 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
83 * for them being zero-based. Another -1 is because ASID 0 is reserved for
84 * use by non-PCID-aware users.
86 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_ASID_BITS) - 2)
88 static inline u16
kern_pcid(u16 asid
)
90 VM_WARN_ON_ONCE(asid
> MAX_ASID_AVAILABLE
);
92 * If PCID is on, ASID-aware code paths put the ASID+1 into the
93 * PCID bits. This serves two purposes. It prevents a nasty
94 * situation in which PCID-unaware code saves CR3, loads some other
95 * value (with PCID == 0), and then restores CR3, thus corrupting
96 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
97 * that any bugs involving loading a PCID-enabled CR3 with
98 * CR4.PCIDE off will trigger deterministically.
104 static inline unsigned long build_cr3(pgd_t
*pgd
, u16 asid
)
106 if (static_cpu_has(X86_FEATURE_PCID
)) {
107 return __sme_pa(pgd
) | kern_pcid(asid
);
109 VM_WARN_ON_ONCE(asid
!= 0);
110 return __sme_pa(pgd
);
114 static inline unsigned long build_cr3_noflush(pgd_t
*pgd
, u16 asid
)
116 VM_WARN_ON_ONCE(asid
> MAX_ASID_AVAILABLE
);
117 VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID
));
118 return __sme_pa(pgd
) | kern_pcid(asid
) | CR3_NOFLUSH
;
121 #ifdef CONFIG_PARAVIRT
122 #include <asm/paravirt.h>
124 #define __flush_tlb() __native_flush_tlb()
125 #define __flush_tlb_global() __native_flush_tlb_global()
126 #define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
129 static inline bool tlb_defer_switch_to_init_mm(void)
132 * If we have PCID, then switching to init_mm is reasonably
133 * fast. If we don't have PCID, then switching to init_mm is
134 * quite slow, so we try to defer it in the hopes that we can
135 * avoid it entirely. The latter approach runs the risk of
136 * receiving otherwise unnecessary IPIs.
138 * This choice is just a heuristic. The tlb code can handle this
139 * function returning true or false regardless of whether we have
142 return !static_cpu_has(X86_FEATURE_PCID
);
146 * 6 because 6 should be plenty and struct tlb_state will fit in
149 #define TLB_NR_DYN_ASIDS 6
158 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
159 * are on. This means that it may not match current->active_mm,
160 * which will contain the previous user mm when we're in lazy TLB
161 * mode even if we've already switched back to swapper_pg_dir.
163 struct mm_struct
*loaded_mm
;
168 * We can be in one of several states:
170 * - Actively using an mm. Our CPU's bit will be set in
171 * mm_cpumask(loaded_mm) and is_lazy == false;
173 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
174 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
176 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
177 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
178 * We're heuristically guessing that the CR3 load we
179 * skipped more than makes up for the overhead added by
185 * Access to this CR4 shadow and to H/W CR4 is protected by
186 * disabling interrupts when modifying either one.
191 * This is a list of all contexts that might exist in the TLB.
192 * There is one per ASID that we use, and the ASID (what the
193 * CPU calls PCID) is the index into ctxts.
195 * For each context, ctx_id indicates which mm the TLB's user
196 * entries came from. As an invariant, the TLB will never
197 * contain entries that are out-of-date as when that mm reached
198 * the tlb_gen in the list.
200 * To be clear, this means that it's legal for the TLB code to
201 * flush the TLB without updating tlb_gen. This can happen
202 * (for now, at least) due to paravirt remote flushes.
204 * NB: context 0 is a bit special, since it's also used by
205 * various bits of init code. This is fine -- code that
206 * isn't aware of PCID will end up harmlessly flushing
209 struct tlb_context ctxs
[TLB_NR_DYN_ASIDS
];
211 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
);
213 /* Initialize cr4 shadow for this CPU. */
214 static inline void cr4_init_shadow(void)
216 this_cpu_write(cpu_tlbstate
.cr4
, __read_cr4());
219 /* Set in this cpu's CR4. */
220 static inline void cr4_set_bits(unsigned long mask
)
224 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
225 if ((cr4
| mask
) != cr4
) {
227 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
232 /* Clear in this cpu's CR4. */
233 static inline void cr4_clear_bits(unsigned long mask
)
237 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
238 if ((cr4
& ~mask
) != cr4
) {
240 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
245 static inline void cr4_toggle_bits(unsigned long mask
)
249 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
251 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
255 /* Read the CR4 shadow. */
256 static inline unsigned long cr4_read_shadow(void)
258 return this_cpu_read(cpu_tlbstate
.cr4
);
262 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
263 * enable and PPro Global page enable), so that any CPU's that boot
264 * up after us can get the correct flags. This should only be used
265 * during boot on the boot cpu.
267 extern unsigned long mmu_cr4_features
;
268 extern u32
*trampoline_cr4_features
;
270 static inline void cr4_set_bits_and_update_boot(unsigned long mask
)
272 mmu_cr4_features
|= mask
;
273 if (trampoline_cr4_features
)
274 *trampoline_cr4_features
= mmu_cr4_features
;
278 extern void initialize_tlbstate_and_flush(void);
281 * flush the entire current user mapping
283 static inline void __native_flush_tlb(void)
286 * If current->mm == NULL then we borrow a mm which may change during a
287 * task switch and therefore we must not be preempted while we write CR3
291 native_write_cr3(__native_read_cr3());
298 static inline void __native_flush_tlb_global(void)
300 unsigned long cr4
, flags
;
302 if (static_cpu_has(X86_FEATURE_INVPCID
)) {
304 * Using INVPCID is considerably faster than a pair of writes
305 * to CR4 sandwiched inside an IRQ flag save/restore.
312 * Read-modify-write to CR4 - protect it from preemption and
313 * from interrupts. (Use the raw variant because this code can
314 * be called from deep inside debugging code.)
316 raw_local_irq_save(flags
);
318 cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
320 native_write_cr4(cr4
^ X86_CR4_PGE
);
321 /* write old PGE again and flush TLBs */
322 native_write_cr4(cr4
);
324 raw_local_irq_restore(flags
);
328 * flush one page in the user mapping
330 static inline void __native_flush_tlb_single(unsigned long addr
)
332 asm volatile("invlpg (%0)" ::"r" (addr
) : "memory");
338 static inline void __flush_tlb_all(void)
340 if (boot_cpu_has(X86_FEATURE_PGE
)) {
341 __flush_tlb_global();
344 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
350 * Note: if we somehow had PCID but not PGE, then this wouldn't work --
351 * we'd end up flushing kernel translations for the current ASID but
352 * we might fail to flush kernel translations for other cached ASIDs.
354 * To avoid this issue, we force PCID off if PGE is off.
359 * flush one page in the kernel mapping
361 static inline void __flush_tlb_one(unsigned long addr
)
363 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE
);
364 __flush_tlb_single(addr
);
367 #define TLB_FLUSH_ALL -1UL
372 * - flush_tlb_all() flushes all processes TLBs
373 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
374 * - flush_tlb_page(vma, vmaddr) flushes one page
375 * - flush_tlb_range(vma, start, end) flushes a range of pages
376 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
377 * - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
379 * ..but the i386 has somewhat limited tlb flushing capabilities,
380 * and page-granular flushes are available only on i486 and up.
382 struct flush_tlb_info
{
384 * We support several kinds of flushes.
386 * - Fully flush a single mm. .mm will be set, .end will be
387 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
388 * which the IPI sender is trying to catch us up.
390 * - Partially flush a single mm. .mm will be set, .start and
391 * .end will indicate the range, and .new_tlb_gen will be set
392 * such that the changes between generation .new_tlb_gen-1 and
393 * .new_tlb_gen are entirely contained in the indicated range.
395 * - Fully flush all mms whose tlb_gens have been updated. .mm
396 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
399 struct mm_struct
*mm
;
405 #define local_flush_tlb() __flush_tlb()
407 #define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
409 #define flush_tlb_range(vma, start, end) \
410 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
412 extern void flush_tlb_all(void);
413 extern void flush_tlb_mm_range(struct mm_struct
*mm
, unsigned long start
,
414 unsigned long end
, unsigned long vmflag
);
415 extern void flush_tlb_kernel_range(unsigned long start
, unsigned long end
);
417 static inline void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long a
)
419 flush_tlb_mm_range(vma
->vm_mm
, a
, a
+ PAGE_SIZE
, VM_NONE
);
422 void native_flush_tlb_others(const struct cpumask
*cpumask
,
423 const struct flush_tlb_info
*info
);
425 static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch
*batch
,
426 struct mm_struct
*mm
)
429 cpumask_or(&batch
->cpumask
, &batch
->cpumask
, mm_cpumask(mm
));
432 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch
*batch
);
434 #ifndef CONFIG_PARAVIRT
435 #define flush_tlb_others(mask, info) \
436 native_flush_tlb_others(mask, info)
439 #endif /* _ASM_X86_TLBFLUSH_H */