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2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_X86_UV__UV_HUB_H
12 #define _ASM_X86_UV__UV_HUB_H
14 #include <linux/numa.h>
15 #include <linux/percpu.h>
16 #include <asm/types.h>
17 #include <asm/percpu.h>
21 * Addressing Terminology
23 * M - The low M bits of a physical address represent the offset
24 * into the blade local memory. RAM memory on a blade is physically
25 * contiguous (although various IO spaces may punch holes in
28 * N - Number of bits in the node portion of a socket physical
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
32 * routers always have low bit of 1, C/MBricks have low bit
33 * equal to 0. Most addressing macros that target UV hub chips
34 * right shift the NASID by 1 to exclude the always-zero bit.
35 * NASIDs contain up to 15 bits.
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
41 * of the nasid for socket usage.
44 * NumaLink Global Physical Address Format:
45 * +--------------------------------+---------------------+
46 * |00..000| GNODE | NodeOffset |
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
50 * M - number of node offset bits (35 .. 40)
53 * Memory/UV-HUB Processor Socket Address Format:
54 * +----------------+---------------+---------------------+
55 * |00..000000000000| PNODE | NodeOffset |
56 * +----------------+---------------+---------------------+
57 * <--- N bits --->|<--------M bits ----->
59 * M - number of node offset bits (35 .. 40)
60 * N - number of PNODE bits (0 .. 10)
62 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
63 * The actual values are configuration dependent and are set at
64 * boot time. M & N values are set by the hardware/BIOS at boot.
68 * NOTE!!!!!! This is the current format of the APICID. However, code
69 * should assume that this will change in the future. Use functions
70 * in this file for all APICID bit manipulations and conversion.
78 * l = socket number on board
81 * s = bits that are in the SOCKET_ID CSR
83 * Note: Processor only supports 12 bits in the APICID register. The ACPI
84 * tables hold all 16 bits. Software needs to be aware of this.
86 * Unless otherwise specified, all references to APICID refer to
87 * the FULL value contained in ACPI tables, not the subset in the
88 * processor APICID register.
93 * Maximum number of bricks in all partitions and in all coherency domains.
94 * This is the total number of bricks accessible in the numalink fabric. It
95 * includes all C & M bricks. Routers are NOT included.
97 * This value is also the value of the maximum number of non-router NASIDs
98 * in the numalink fabric.
100 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
102 #define UV_MAX_NUMALINK_BLADES 16384
105 * Maximum number of C/Mbricks within a software SSI (hardware may support
108 #define UV_MAX_SSI_BLADES 256
111 * The largest possible NASID of a C or M brick (+ 2)
113 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
116 * The following defines attributes of the HUB chip. These attributes are
117 * frequently referenced and are kept in the per-cpu data areas of each cpu.
118 * They are kept together in a struct to minimize cache misses.
120 struct uv_hub_info_s
{
121 unsigned long global_mmr_base
;
122 unsigned long gpa_mask
;
123 unsigned long gnode_upper
;
124 unsigned long lowmem_remap_top
;
125 unsigned long lowmem_remap_base
;
126 unsigned short pnode
;
127 unsigned short pnode_mask
;
128 unsigned short coherency_domain_number
;
129 unsigned short numa_blade_id
;
130 unsigned char blade_processor_id
;
134 DECLARE_PER_CPU(struct uv_hub_info_s
, __uv_hub_info
);
135 #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
136 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
139 * Local & Global MMR space macros.
140 * Note: macros are intended to be used ONLY by inline functions
141 * in this file - not by other kernel code.
142 * n - NASID (full 15-bit global nasid)
143 * g - GNODE (full 15-bit global nasid, right shifted 1)
144 * p - PNODE (local part of nsids, right shifted 1)
146 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
147 #define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
149 #define UV_LOCAL_MMR_BASE 0xf4000000UL
150 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL
151 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
152 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
153 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
155 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
156 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26
158 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
160 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
161 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
163 #define UV_APIC_PNODE_SHIFT 6
166 * Macros for converting between kernel virtual addresses, socket local physical
167 * addresses, and UV global physical addresses.
168 * Note: use the standard __pa() & __va() macros for converting
169 * between socket virtual and socket physical addresses.
172 /* socket phys RAM --> UV global physical address */
173 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr
)
175 if (paddr
< uv_hub_info
->lowmem_remap_top
)
176 paddr
+= uv_hub_info
->lowmem_remap_base
;
177 return paddr
| uv_hub_info
->gnode_upper
;
181 /* socket virtual --> UV global physical address */
182 static inline unsigned long uv_gpa(void *v
)
184 return __pa(v
) | uv_hub_info
->gnode_upper
;
187 /* socket virtual --> UV global physical address */
188 static inline void *uv_vgpa(void *v
)
190 return (void *)uv_gpa(v
);
193 /* UV global physical address --> socket virtual */
194 static inline void *uv_va(unsigned long gpa
)
196 return __va(gpa
& uv_hub_info
->gpa_mask
);
199 /* pnode, offset --> socket virtual */
200 static inline void *uv_pnode_offset_to_vaddr(int pnode
, unsigned long offset
)
202 return __va(((unsigned long)pnode
<< uv_hub_info
->m_val
) | offset
);
207 * Extract a PNODE from an APICID (full apicid, not processor subset)
209 static inline int uv_apicid_to_pnode(int apicid
)
211 return (apicid
>> UV_APIC_PNODE_SHIFT
);
215 * Access global MMRs using the low memory MMR32 space. This region supports
216 * faster MMR access but not all MMRs are accessible in this space.
218 static inline unsigned long *uv_global_mmr32_address(int pnode
,
219 unsigned long offset
)
221 return __va(UV_GLOBAL_MMR32_BASE
|
222 UV_GLOBAL_MMR32_PNODE_BITS(pnode
) | offset
);
225 static inline void uv_write_global_mmr32(int pnode
, unsigned long offset
,
228 *uv_global_mmr32_address(pnode
, offset
) = val
;
231 static inline unsigned long uv_read_global_mmr32(int pnode
,
232 unsigned long offset
)
234 return *uv_global_mmr32_address(pnode
, offset
);
238 * Access Global MMR space using the MMR space located at the top of physical
241 static inline unsigned long *uv_global_mmr64_address(int pnode
,
242 unsigned long offset
)
244 return __va(UV_GLOBAL_MMR64_BASE
|
245 UV_GLOBAL_MMR64_PNODE_BITS(pnode
) | offset
);
248 static inline void uv_write_global_mmr64(int pnode
, unsigned long offset
,
251 *uv_global_mmr64_address(pnode
, offset
) = val
;
254 static inline unsigned long uv_read_global_mmr64(int pnode
,
255 unsigned long offset
)
257 return *uv_global_mmr64_address(pnode
, offset
);
261 * Access hub local MMRs. Faster than using global space but only local MMRs
264 static inline unsigned long *uv_local_mmr_address(unsigned long offset
)
266 return __va(UV_LOCAL_MMR_BASE
| offset
);
269 static inline unsigned long uv_read_local_mmr(unsigned long offset
)
271 return *uv_local_mmr_address(offset
);
274 static inline void uv_write_local_mmr(unsigned long offset
, unsigned long val
)
276 *uv_local_mmr_address(offset
) = val
;
280 * Structures and definitions for converting between cpu, node, pnode, and blade
283 struct uv_blade_info
{
284 unsigned short nr_possible_cpus
;
285 unsigned short nr_online_cpus
;
286 unsigned short pnode
;
288 extern struct uv_blade_info
*uv_blade_info
;
289 extern short *uv_node_to_blade
;
290 extern short *uv_cpu_to_blade
;
291 extern short uv_possible_blades
;
293 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
294 static inline int uv_blade_processor_id(void)
296 return uv_hub_info
->blade_processor_id
;
299 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
300 static inline int uv_numa_blade_id(void)
302 return uv_hub_info
->numa_blade_id
;
305 /* Convert a cpu number to the the UV blade number */
306 static inline int uv_cpu_to_blade_id(int cpu
)
308 return uv_cpu_to_blade
[cpu
];
311 /* Convert linux node number to the UV blade number */
312 static inline int uv_node_to_blade_id(int nid
)
314 return uv_node_to_blade
[nid
];
317 /* Convert a blade id to the PNODE of the blade */
318 static inline int uv_blade_to_pnode(int bid
)
320 return uv_blade_info
[bid
].pnode
;
323 /* Determine the number of possible cpus on a blade */
324 static inline int uv_blade_nr_possible_cpus(int bid
)
326 return uv_blade_info
[bid
].nr_possible_cpus
;
329 /* Determine the number of online cpus on a blade */
330 static inline int uv_blade_nr_online_cpus(int bid
)
332 return uv_blade_info
[bid
].nr_online_cpus
;
335 /* Convert a cpu id to the PNODE of the blade containing the cpu */
336 static inline int uv_cpu_to_pnode(int cpu
)
338 return uv_blade_info
[uv_cpu_to_blade_id(cpu
)].pnode
;
341 /* Convert a linux node number to the PNODE of the blade */
342 static inline int uv_node_to_pnode(int nid
)
344 return uv_blade_info
[uv_node_to_blade_id(nid
)].pnode
;
347 /* Maximum possible number of blades */
348 static inline int uv_num_possible_blades(void)
350 return uv_possible_blades
;
353 #endif /* _ASM_X86_UV__UV_HUB_H */