arch/x86/include/uapi/asm/hyperv.h

   1 #ifndef _ASM_X86_HYPERV_H
   2 #define _ASM_X86_HYPERV_H
   3
   4 #include <linux/types.h>
   5
   6 /*
   7  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
   8  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
   9  */
  10 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  11 #define HYPERV_CPUID_INTERFACE                  0x40000001
  12 #define HYPERV_CPUID_VERSION                    0x40000002
  13 #define HYPERV_CPUID_FEATURES                   0x40000003
  14 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  15 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  16
  17 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  18 #define HYPERV_CPUID_MIN                        0x40000005
  19 #define HYPERV_CPUID_MAX                        0x4000ffff
  20
  21 /*
  22  * Feature identification. EAX indicates which features are available
  23  * to the partition based upon the current partition privileges.
  24  */
  25
  26 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
  27 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         (1 << 0)
  28 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
  29 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE     (1 << 1)
  30 /* Partition reference TSC MSR is available */
  31 #define HV_X64_MSR_REFERENCE_TSC_AVAILABLE              (1 << 9)
  32
  33 /* A partition's reference time stamp counter (TSC) page */
  34 #define HV_X64_MSR_REFERENCE_TSC                0x40000021
  35
  36 /*
  37  * There is a single feature flag that signifies if the partition has access
  38  * to MSRs with local APIC and TSC frequencies.
  39  */
  40 #define HV_X64_ACCESS_FREQUENCY_MSRS            (1 << 11)
  41
  42 /*
  43  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
  44  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
  45  */
  46 #define HV_X64_MSR_SYNIC_AVAILABLE              (1 << 2)
  47 /*
  48  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
  49  * HV_X64_MSR_STIMER3_COUNT) available
  50  */
  51 #define HV_X64_MSR_SYNTIMER_AVAILABLE           (1 << 3)
  52 /*
  53  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
  54  * are available
  55  */
  56 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        (1 << 4)
  57 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
  58 #define HV_X64_MSR_HYPERCALL_AVAILABLE          (1 << 5)
  59 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
  60 #define HV_X64_MSR_VP_INDEX_AVAILABLE           (1 << 6)
  61 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
  62 #define HV_X64_MSR_RESET_AVAILABLE              (1 << 7)
  63  /*
  64   * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  65   * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  66   * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  67   */
  68 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         (1 << 8)
  69
  70 /* Frequency MSRs available */
  71 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE     (1 << 8)
  72
  73 /* Crash MSR available */
  74 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
  75
  76 /*
  77  * Feature identification: EBX indicates which flags were specified at
  78  * partition creation. The format is the same as the partition creation
  79  * flag structure defined in section Partition Creation Flags.
  80  */
  81 #define HV_X64_CREATE_PARTITIONS                (1 << 0)
  82 #define HV_X64_ACCESS_PARTITION_ID              (1 << 1)
  83 #define HV_X64_ACCESS_MEMORY_POOL               (1 << 2)
  84 #define HV_X64_ADJUST_MESSAGE_BUFFERS           (1 << 3)
  85 #define HV_X64_POST_MESSAGES                    (1 << 4)
  86 #define HV_X64_SIGNAL_EVENTS                    (1 << 5)
  87 #define HV_X64_CREATE_PORT                      (1 << 6)
  88 #define HV_X64_CONNECT_PORT                     (1 << 7)
  89 #define HV_X64_ACCESS_STATS                     (1 << 8)
  90 #define HV_X64_DEBUGGING                        (1 << 11)
  91 #define HV_X64_CPU_POWER_MANAGEMENT             (1 << 12)
  92 #define HV_X64_CONFIGURE_PROFILER               (1 << 13)
  93
  94 /*
  95  * Feature identification. EDX indicates which miscellaneous features
  96  * are available to the partition.
  97  */
  98 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
  99 #define HV_X64_MWAIT_AVAILABLE                          (1 << 0)
 100 /* Guest debugging support is available */
 101 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                (1 << 1)
 102 /* Performance Monitor support is available*/
 103 #define HV_X64_PERF_MONITOR_AVAILABLE                   (1 << 2)
 104 /* Support for physical CPU dynamic partitioning events is available*/
 105 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       (1 << 3)
 106 /*
 107  * Support for passing hypercall input parameter block via XMM
 108  * registers is available
 109  */
 110 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           (1 << 4)
 111 /* Support for a virtual guest idle state is available */
 112 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               (1 << 5)
 113 /* Guest crash data handler available */
 114 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE                (1 << 10)
 115
 116 /*
 117  * Implementation recommendations. Indicates which behaviors the hypervisor
 118  * recommends the OS implement for optimal performance.
 119  */
 120  /*
 121   * Recommend using hypercall for address space switches rather
 122   * than MOV to CR3 instruction
 123   */
 124 #define HV_X64_AS_SWITCH_RECOMMENDED            (1 << 0)
 125 /* Recommend using hypercall for local TLB flushes rather
 126  * than INVLPG or MOV to CR3 instructions */
 127 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED      (1 << 1)
 128 /*
 129  * Recommend using hypercall for remote TLB flushes rather
 130  * than inter-processor interrupts
 131  */
 132 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED     (1 << 2)
 133 /*
 134  * Recommend using MSRs for accessing APIC registers
 135  * EOI, ICR and TPR rather than their memory-mapped counterparts
 136  */
 137 #define HV_X64_APIC_ACCESS_RECOMMENDED          (1 << 3)
 138 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 139 #define HV_X64_SYSTEM_RESET_RECOMMENDED         (1 << 4)
 140 /*
 141  * Recommend using relaxed timing for this partition. If used,
 142  * the VM should disable any watchdog timeouts that rely on the
 143  * timely delivery of external interrupts
 144  */
 145 #define HV_X64_RELAXED_TIMING_RECOMMENDED       (1 << 5)
 146
 147 /*
 148  * Virtual APIC support
 149  */
 150 #define HV_X64_DEPRECATING_AEOI_RECOMMENDED     (1 << 9)
 151
 152 /* Recommend using the newer ExProcessorMasks interface */
 153 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED   (1 << 11)
 154
 155 /*
 156  * HV_VP_SET available
 157  */
 158 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED   (1 << 11)
 159
 160
 161 /*
 162  * Crash notification flag.
 163  */
 164 #define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
 165
 166 /* MSR used to identify the guest OS. */
 167 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 168
 169 /* MSR used to setup pages used to communicate with the hypervisor. */
 170 #define HV_X64_MSR_HYPERCALL                    0x40000001
 171
 172 /* MSR used to provide vcpu index */
 173 #define HV_X64_MSR_VP_INDEX                     0x40000002
 174
 175 /* MSR used to reset the guest OS. */
 176 #define HV_X64_MSR_RESET                        0x40000003
 177
 178 /* MSR used to provide vcpu runtime in 100ns units */
 179 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 180
 181 /* MSR used to read the per-partition time reference counter */
 182 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 183
 184 /* MSR used to retrieve the TSC frequency */
 185 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 186
 187 /* MSR used to retrieve the local APIC timer frequency */
 188 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 189
 190 /* Define the virtual APIC registers */
 191 #define HV_X64_MSR_EOI                          0x40000070
 192 #define HV_X64_MSR_ICR                          0x40000071
 193 #define HV_X64_MSR_TPR                          0x40000072
 194 #define HV_X64_MSR_APIC_ASSIST_PAGE             0x40000073
 195
 196 /* Define synthetic interrupt controller model specific registers. */
 197 #define HV_X64_MSR_SCONTROL                     0x40000080
 198 #define HV_X64_MSR_SVERSION                     0x40000081
 199 #define HV_X64_MSR_SIEFP                        0x40000082
 200 #define HV_X64_MSR_SIMP                         0x40000083
 201 #define HV_X64_MSR_EOM                          0x40000084
 202 #define HV_X64_MSR_SINT0                        0x40000090
 203 #define HV_X64_MSR_SINT1                        0x40000091
 204 #define HV_X64_MSR_SINT2                        0x40000092
 205 #define HV_X64_MSR_SINT3                        0x40000093
 206 #define HV_X64_MSR_SINT4                        0x40000094
 207 #define HV_X64_MSR_SINT5                        0x40000095
 208 #define HV_X64_MSR_SINT6                        0x40000096
 209 #define HV_X64_MSR_SINT7                        0x40000097
 210 #define HV_X64_MSR_SINT8                        0x40000098
 211 #define HV_X64_MSR_SINT9                        0x40000099
 212 #define HV_X64_MSR_SINT10                       0x4000009A
 213 #define HV_X64_MSR_SINT11                       0x4000009B
 214 #define HV_X64_MSR_SINT12                       0x4000009C
 215 #define HV_X64_MSR_SINT13                       0x4000009D
 216 #define HV_X64_MSR_SINT14                       0x4000009E
 217 #define HV_X64_MSR_SINT15                       0x4000009F
 218
 219 /*
 220  * Synthetic Timer MSRs. Four timers per vcpu.
 221  */
 222 #define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
 223 #define HV_X64_MSR_STIMER0_COUNT                0x400000B1
 224 #define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
 225 #define HV_X64_MSR_STIMER1_COUNT                0x400000B3
 226 #define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
 227 #define HV_X64_MSR_STIMER2_COUNT                0x400000B5
 228 #define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
 229 #define HV_X64_MSR_STIMER3_COUNT                0x400000B7
 230
 231 /* Hyper-V guest crash notification MSR's */
 232 #define HV_X64_MSR_CRASH_P0                     0x40000100
 233 #define HV_X64_MSR_CRASH_P1                     0x40000101
 234 #define HV_X64_MSR_CRASH_P2                     0x40000102
 235 #define HV_X64_MSR_CRASH_P3                     0x40000103
 236 #define HV_X64_MSR_CRASH_P4                     0x40000104
 237 #define HV_X64_MSR_CRASH_CTL                    0x40000105
 238 #define HV_X64_MSR_CRASH_CTL_NOTIFY             (1ULL << 63)
 239 #define HV_X64_MSR_CRASH_PARAMS         \
 240                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 241
 242 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 243 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 244 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 245                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 246
 247 /* Declare the various hypercall operations. */
 248 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE      0x0002
 249 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST       0x0003
 250 #define HVCALL_NOTIFY_LONG_SPIN_WAIT            0x0008
 251 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
 252 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
 253 #define HVCALL_POST_MESSAGE                     0x005c
 254 #define HVCALL_SIGNAL_EVENT                     0x005d
 255
 256 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE              0x00000001
 257 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT       12
 258 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK        \
 259                 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 260
 261 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 262 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 263
 264 #define HV_PROCESSOR_POWER_STATE_C0             0
 265 #define HV_PROCESSOR_POWER_STATE_C1             1
 266 #define HV_PROCESSOR_POWER_STATE_C2             2
 267 #define HV_PROCESSOR_POWER_STATE_C3             3
 268
 269 #define HV_FLUSH_ALL_PROCESSORS                 BIT(0)
 270 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES     BIT(1)
 271 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY       BIT(2)
 272 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT      BIT(3)
 273
 274 enum HV_GENERIC_SET_FORMAT {
 275         HV_GENERIC_SET_SPARCE_4K,
 276         HV_GENERIC_SET_ALL,
 277 };
 278
 279 /* hypercall status code */
 280 #define HV_STATUS_SUCCESS                       0
 281 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 282 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 283 #define HV_STATUS_INVALID_ALIGNMENT             4
 284 #define HV_STATUS_INSUFFICIENT_MEMORY           11
 285 #define HV_STATUS_INVALID_CONNECTION_ID         18
 286 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 287
 288 typedef struct _HV_REFERENCE_TSC_PAGE {
 289         __u32 tsc_sequence;
 290         __u32 res1;
 291         __u64 tsc_scale;
 292         __s64 tsc_offset;
 293 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
 294
 295 /* Define the number of synthetic interrupt sources. */
 296 #define HV_SYNIC_SINT_COUNT             (16)
 297 /* Define the expected SynIC version. */
 298 #define HV_SYNIC_VERSION_1              (0x1)
 299
 300 #define HV_SYNIC_CONTROL_ENABLE         (1ULL << 0)
 301 #define HV_SYNIC_SIMP_ENABLE            (1ULL << 0)
 302 #define HV_SYNIC_SIEFP_ENABLE           (1ULL << 0)
 303 #define HV_SYNIC_SINT_MASKED            (1ULL << 16)
 304 #define HV_SYNIC_SINT_AUTO_EOI          (1ULL << 17)
 305 #define HV_SYNIC_SINT_VECTOR_MASK       (0xFF)
 306
 307 #define HV_SYNIC_STIMER_COUNT           (4)
 308
 309 /* Define synthetic interrupt controller message constants. */
 310 #define HV_MESSAGE_SIZE                 (256)
 311 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT   (240)
 312 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT  (30)
 313
 314 /* Define hypervisor message types. */
 315 enum hv_message_type {
 316         HVMSG_NONE                      = 0x00000000,
 317
 318         /* Memory access messages. */
 319         HVMSG_UNMAPPED_GPA              = 0x80000000,
 320         HVMSG_GPA_INTERCEPT             = 0x80000001,
 321
 322         /* Timer notification messages. */
 323         HVMSG_TIMER_EXPIRED                     = 0x80000010,
 324
 325         /* Error messages. */
 326         HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
 327         HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
 328         HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
 329
 330         /* Trace buffer complete messages. */
 331         HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
 332
 333         /* Platform-specific processor intercept messages. */
 334         HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
 335         HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
 336         HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
 337         HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
 338         HVMSG_X64_APIC_EOI                      = 0x80010004,
 339         HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
 340 };
 341
 342 /* Define synthetic interrupt controller message flags. */
 343 union hv_message_flags {
 344         __u8 asu8;
 345         struct {
 346                 __u8 msg_pending:1;
 347                 __u8 reserved:7;
 348         };
 349 };
 350
 351 /* Define port identifier type. */
 352 union hv_port_id {
 353         __u32 asu32;
 354         struct {
 355                 __u32 id:24;
 356                 __u32 reserved:8;
 357         } u;
 358 };
 359
 360 /* Define synthetic interrupt controller message header. */
 361 struct hv_message_header {
 362         __u32 message_type;
 363         __u8 payload_size;
 364         union hv_message_flags message_flags;
 365         __u8 reserved[2];
 366         union {
 367                 __u64 sender;
 368                 union hv_port_id port;
 369         };
 370 };
 371
 372 /* Define synthetic interrupt controller message format. */
 373 struct hv_message {
 374         struct hv_message_header header;
 375         union {
 376                 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
 377         } u;
 378 };
 379
 380 /* Define the synthetic interrupt message page layout. */
 381 struct hv_message_page {
 382         struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
 383 };
 384
 385 /* Define timer message payload structure. */
 386 struct hv_timer_message_payload {
 387         __u32 timer_index;
 388         __u32 reserved;
 389         __u64 expiration_time;  /* When the timer expired */
 390         __u64 delivery_time;    /* When the message was delivered */
 391 };
 392
 393 #define HV_STIMER_ENABLE                (1ULL << 0)
 394 #define HV_STIMER_PERIODIC              (1ULL << 1)
 395 #define HV_STIMER_LAZY                  (1ULL << 2)
 396 #define HV_STIMER_AUTOENABLE            (1ULL << 3)
 397 #define HV_STIMER_SINT(config)          (__u8)(((config) >> 16) & 0x0F)
 398
 399 #endif