arch/x86/include/uapi/asm/hyperv.h

   1 #ifndef _ASM_X86_HYPERV_H
   2 #define _ASM_X86_HYPERV_H
   3
   4 #include <linux/types.h>
   5
   6 /*
   7  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
   8  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
   9  */
  10 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  11 #define HYPERV_CPUID_INTERFACE                  0x40000001
  12 #define HYPERV_CPUID_VERSION                    0x40000002
  13 #define HYPERV_CPUID_FEATURES                   0x40000003
  14 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  15 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  16
  17 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  18 #define HYPERV_CPUID_MIN                        0x40000005
  19 #define HYPERV_CPUID_MAX                        0x4000ffff
  20
  21 /*
  22  * Feature identification. EAX indicates which features are available
  23  * to the partition based upon the current partition privileges.
  24  */
  25
  26 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
  27 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         (1 << 0)
  28 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
  29 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE     (1 << 1)
  30
  31 /*
  32  * There is a single feature flag that signifies the presence of the MSR
  33  * that can be used to retrieve both the local APIC Timer frequency as
  34  * well as the TSC frequency.
  35  */
  36
  37 /* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */
  38 #define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11)
  39
  40 /* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */
  41 #define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11)
  42
  43 /*
  44  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
  45  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
  46  */
  47 #define HV_X64_MSR_SYNIC_AVAILABLE              (1 << 2)
  48 /*
  49  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
  50  * HV_X64_MSR_STIMER3_COUNT) available
  51  */
  52 #define HV_X64_MSR_SYNTIMER_AVAILABLE           (1 << 3)
  53 /*
  54  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
  55  * are available
  56  */
  57 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        (1 << 4)
  58 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
  59 #define HV_X64_MSR_HYPERCALL_AVAILABLE          (1 << 5)
  60 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
  61 #define HV_X64_MSR_VP_INDEX_AVAILABLE           (1 << 6)
  62 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
  63 #define HV_X64_MSR_RESET_AVAILABLE              (1 << 7)
  64  /*
  65   * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  66   * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  67   * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  68   */
  69 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         (1 << 8)
  70
  71 /*
  72  * Feature identification: EBX indicates which flags were specified at
  73  * partition creation. The format is the same as the partition creation
  74  * flag structure defined in section Partition Creation Flags.
  75  */
  76 #define HV_X64_CREATE_PARTITIONS                (1 << 0)
  77 #define HV_X64_ACCESS_PARTITION_ID              (1 << 1)
  78 #define HV_X64_ACCESS_MEMORY_POOL               (1 << 2)
  79 #define HV_X64_ADJUST_MESSAGE_BUFFERS           (1 << 3)
  80 #define HV_X64_POST_MESSAGES                    (1 << 4)
  81 #define HV_X64_SIGNAL_EVENTS                    (1 << 5)
  82 #define HV_X64_CREATE_PORT                      (1 << 6)
  83 #define HV_X64_CONNECT_PORT                     (1 << 7)
  84 #define HV_X64_ACCESS_STATS                     (1 << 8)
  85 #define HV_X64_DEBUGGING                        (1 << 11)
  86 #define HV_X64_CPU_POWER_MANAGEMENT             (1 << 12)
  87 #define HV_X64_CONFIGURE_PROFILER               (1 << 13)
  88
  89 /*
  90  * Feature identification. EDX indicates which miscellaneous features
  91  * are available to the partition.
  92  */
  93 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
  94 #define HV_X64_MWAIT_AVAILABLE                          (1 << 0)
  95 /* Guest debugging support is available */
  96 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                (1 << 1)
  97 /* Performance Monitor support is available*/
  98 #define HV_X64_PERF_MONITOR_AVAILABLE                   (1 << 2)
  99 /* Support for physical CPU dynamic partitioning events is available*/
 100 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       (1 << 3)
 101 /*
 102  * Support for passing hypercall input parameter block via XMM
 103  * registers is available
 104  */
 105 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           (1 << 4)
 106 /* Support for a virtual guest idle state is available */
 107 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               (1 << 5)
 108
 109 /*
 110  * Implementation recommendations. Indicates which behaviors the hypervisor
 111  * recommends the OS implement for optimal performance.
 112  */
 113  /*
 114   * Recommend using hypercall for address space switches rather
 115   * than MOV to CR3 instruction
 116   */
 117 #define HV_X64_MWAIT_RECOMMENDED                (1 << 0)
 118 /* Recommend using hypercall for local TLB flushes rather
 119  * than INVLPG or MOV to CR3 instructions */
 120 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED      (1 << 1)
 121 /*
 122  * Recommend using hypercall for remote TLB flushes rather
 123  * than inter-processor interrupts
 124  */
 125 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED     (1 << 2)
 126 /*
 127  * Recommend using MSRs for accessing APIC registers
 128  * EOI, ICR and TPR rather than their memory-mapped counterparts
 129  */
 130 #define HV_X64_APIC_ACCESS_RECOMMENDED          (1 << 3)
 131 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 132 #define HV_X64_SYSTEM_RESET_RECOMMENDED         (1 << 4)
 133 /*
 134  * Recommend using relaxed timing for this partition. If used,
 135  * the VM should disable any watchdog timeouts that rely on the
 136  * timely delivery of external interrupts
 137  */
 138 #define HV_X64_RELAXED_TIMING_RECOMMENDED       (1 << 5)
 139
 140 /* MSR used to identify the guest OS. */
 141 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 142
 143 /* MSR used to setup pages used to communicate with the hypervisor. */
 144 #define HV_X64_MSR_HYPERCALL                    0x40000001
 145
 146 /* MSR used to provide vcpu index */
 147 #define HV_X64_MSR_VP_INDEX                     0x40000002
 148
 149 /* MSR used to read the per-partition time reference counter */
 150 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 151
 152 /* MSR used to retrieve the TSC frequency */
 153 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 154
 155 /* MSR used to retrieve the local APIC timer frequency */
 156 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 157
 158 /* Define the virtual APIC registers */
 159 #define HV_X64_MSR_EOI                          0x40000070
 160 #define HV_X64_MSR_ICR                          0x40000071
 161 #define HV_X64_MSR_TPR                          0x40000072
 162 #define HV_X64_MSR_APIC_ASSIST_PAGE             0x40000073
 163
 164 /* Define synthetic interrupt controller model specific registers. */
 165 #define HV_X64_MSR_SCONTROL                     0x40000080
 166 #define HV_X64_MSR_SVERSION                     0x40000081
 167 #define HV_X64_MSR_SIEFP                        0x40000082
 168 #define HV_X64_MSR_SIMP                         0x40000083
 169 #define HV_X64_MSR_EOM                          0x40000084
 170 #define HV_X64_MSR_SINT0                        0x40000090
 171 #define HV_X64_MSR_SINT1                        0x40000091
 172 #define HV_X64_MSR_SINT2                        0x40000092
 173 #define HV_X64_MSR_SINT3                        0x40000093
 174 #define HV_X64_MSR_SINT4                        0x40000094
 175 #define HV_X64_MSR_SINT5                        0x40000095
 176 #define HV_X64_MSR_SINT6                        0x40000096
 177 #define HV_X64_MSR_SINT7                        0x40000097
 178 #define HV_X64_MSR_SINT8                        0x40000098
 179 #define HV_X64_MSR_SINT9                        0x40000099
 180 #define HV_X64_MSR_SINT10                       0x4000009A
 181 #define HV_X64_MSR_SINT11                       0x4000009B
 182 #define HV_X64_MSR_SINT12                       0x4000009C
 183 #define HV_X64_MSR_SINT13                       0x4000009D
 184 #define HV_X64_MSR_SINT14                       0x4000009E
 185 #define HV_X64_MSR_SINT15                       0x4000009F
 186
 187
 188 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 189 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 190 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 191                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 192
 193 /* Declare the various hypercall operations. */
 194 #define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT         0x0008
 195
 196 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE              0x00000001
 197 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT       12
 198 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK        \
 199                 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 200
 201 #define HV_PROCESSOR_POWER_STATE_C0             0
 202 #define HV_PROCESSOR_POWER_STATE_C1             1
 203 #define HV_PROCESSOR_POWER_STATE_C2             2
 204 #define HV_PROCESSOR_POWER_STATE_C3             3
 205
 206 /* hypercall status code */
 207 #define HV_STATUS_SUCCESS                       0
 208 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 209 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 210 #define HV_STATUS_INVALID_ALIGNMENT             4
 211 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 212
 213 #endif