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1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
33
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
35
36 #define EXIT_LOOP_COUNT 10000000
37
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
39
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
43
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
46 #endif
47
48 /*
49 * general struct to manage commands send to an IOMMU
50 */
51 struct iommu_cmd {
52 u32 data[4];
53 };
54
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61
62 #ifdef CONFIG_AMD_IOMMU_STATS
63
64 /*
65 * Initialization code for statistics collection
66 */
67
68 DECLARE_STATS_COUNTER(compl_wait);
69 DECLARE_STATS_COUNTER(cnt_map_single);
70 DECLARE_STATS_COUNTER(cnt_unmap_single);
71 DECLARE_STATS_COUNTER(cnt_map_sg);
72 DECLARE_STATS_COUNTER(cnt_unmap_sg);
73 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
74 DECLARE_STATS_COUNTER(cnt_free_coherent);
75 DECLARE_STATS_COUNTER(cross_page);
76 DECLARE_STATS_COUNTER(domain_flush_single);
77 DECLARE_STATS_COUNTER(domain_flush_all);
78 DECLARE_STATS_COUNTER(alloced_io_mem);
79 DECLARE_STATS_COUNTER(total_map_requests);
80
81 static struct dentry *stats_dir;
82 static struct dentry *de_isolate;
83 static struct dentry *de_fflush;
84
85 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
86 {
87 if (stats_dir == NULL)
88 return;
89
90 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
91 &cnt->value);
92 }
93
94 static void amd_iommu_stats_init(void)
95 {
96 stats_dir = debugfs_create_dir("amd-iommu", NULL);
97 if (stats_dir == NULL)
98 return;
99
100 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
101 (u32 *)&amd_iommu_isolate);
102
103 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
104 (u32 *)&amd_iommu_unmap_flush);
105
106 amd_iommu_stats_add(&compl_wait);
107 amd_iommu_stats_add(&cnt_map_single);
108 amd_iommu_stats_add(&cnt_unmap_single);
109 amd_iommu_stats_add(&cnt_map_sg);
110 amd_iommu_stats_add(&cnt_unmap_sg);
111 amd_iommu_stats_add(&cnt_alloc_coherent);
112 amd_iommu_stats_add(&cnt_free_coherent);
113 amd_iommu_stats_add(&cross_page);
114 amd_iommu_stats_add(&domain_flush_single);
115 amd_iommu_stats_add(&domain_flush_all);
116 amd_iommu_stats_add(&alloced_io_mem);
117 amd_iommu_stats_add(&total_map_requests);
118 }
119
120 #endif
121
122 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
123 static int iommu_has_npcache(struct amd_iommu *iommu)
124 {
125 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
126 }
127
128 /****************************************************************************
129 *
130 * Interrupt handling functions
131 *
132 ****************************************************************************/
133
134 static void iommu_print_event(void *__evt)
135 {
136 u32 *event = __evt;
137 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
138 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
139 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
140 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
141 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
142
143 printk(KERN_ERR "AMD IOMMU: Event logged [");
144
145 switch (type) {
146 case EVENT_TYPE_ILL_DEV:
147 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
148 "address=0x%016llx flags=0x%04x]\n",
149 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
150 address, flags);
151 break;
152 case EVENT_TYPE_IO_FAULT:
153 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
154 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
155 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
156 domid, address, flags);
157 break;
158 case EVENT_TYPE_DEV_TAB_ERR:
159 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
160 "address=0x%016llx flags=0x%04x]\n",
161 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
162 address, flags);
163 break;
164 case EVENT_TYPE_PAGE_TAB_ERR:
165 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
166 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
167 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
168 domid, address, flags);
169 break;
170 case EVENT_TYPE_ILL_CMD:
171 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
172 break;
173 case EVENT_TYPE_CMD_HARD_ERR:
174 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
175 "flags=0x%04x]\n", address, flags);
176 break;
177 case EVENT_TYPE_IOTLB_INV_TO:
178 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
179 "address=0x%016llx]\n",
180 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 address);
182 break;
183 case EVENT_TYPE_INV_DEV_REQ:
184 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
185 "address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 address, flags);
188 break;
189 default:
190 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
191 }
192 }
193
194 static void iommu_poll_events(struct amd_iommu *iommu)
195 {
196 u32 head, tail;
197 unsigned long flags;
198
199 spin_lock_irqsave(&iommu->lock, flags);
200
201 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
202 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
203
204 while (head != tail) {
205 iommu_print_event(iommu->evt_buf + head);
206 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
207 }
208
209 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
210
211 spin_unlock_irqrestore(&iommu->lock, flags);
212 }
213
214 irqreturn_t amd_iommu_int_handler(int irq, void *data)
215 {
216 struct amd_iommu *iommu;
217
218 list_for_each_entry(iommu, &amd_iommu_list, list)
219 iommu_poll_events(iommu);
220
221 return IRQ_HANDLED;
222 }
223
224 /****************************************************************************
225 *
226 * IOMMU command queuing functions
227 *
228 ****************************************************************************/
229
230 /*
231 * Writes the command to the IOMMUs command buffer and informs the
232 * hardware about the new command. Must be called with iommu->lock held.
233 */
234 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
235 {
236 u32 tail, head;
237 u8 *target;
238
239 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
240 target = iommu->cmd_buf + tail;
241 memcpy_toio(target, cmd, sizeof(*cmd));
242 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
243 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
244 if (tail == head)
245 return -ENOMEM;
246 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
247
248 return 0;
249 }
250
251 /*
252 * General queuing function for commands. Takes iommu->lock and calls
253 * __iommu_queue_command().
254 */
255 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
256 {
257 unsigned long flags;
258 int ret;
259
260 spin_lock_irqsave(&iommu->lock, flags);
261 ret = __iommu_queue_command(iommu, cmd);
262 if (!ret)
263 iommu->need_sync = true;
264 spin_unlock_irqrestore(&iommu->lock, flags);
265
266 return ret;
267 }
268
269 /*
270 * This function waits until an IOMMU has completed a completion
271 * wait command
272 */
273 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
274 {
275 int ready = 0;
276 unsigned status = 0;
277 unsigned long i = 0;
278
279 INC_STATS_COUNTER(compl_wait);
280
281 while (!ready && (i < EXIT_LOOP_COUNT)) {
282 ++i;
283 /* wait for the bit to become one */
284 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
285 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
286 }
287
288 /* set bit back to zero */
289 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
290 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
291
292 if (unlikely(i == EXIT_LOOP_COUNT))
293 panic("AMD IOMMU: Completion wait loop failed\n");
294 }
295
296 /*
297 * This function queues a completion wait command into the command
298 * buffer of an IOMMU
299 */
300 static int __iommu_completion_wait(struct amd_iommu *iommu)
301 {
302 struct iommu_cmd cmd;
303
304 memset(&cmd, 0, sizeof(cmd));
305 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
306 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
307
308 return __iommu_queue_command(iommu, &cmd);
309 }
310
311 /*
312 * This function is called whenever we need to ensure that the IOMMU has
313 * completed execution of all commands we sent. It sends a
314 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
315 * us about that by writing a value to a physical address we pass with
316 * the command.
317 */
318 static int iommu_completion_wait(struct amd_iommu *iommu)
319 {
320 int ret = 0;
321 unsigned long flags;
322
323 spin_lock_irqsave(&iommu->lock, flags);
324
325 if (!iommu->need_sync)
326 goto out;
327
328 ret = __iommu_completion_wait(iommu);
329
330 iommu->need_sync = false;
331
332 if (ret)
333 goto out;
334
335 __iommu_wait_for_completion(iommu);
336
337 out:
338 spin_unlock_irqrestore(&iommu->lock, flags);
339
340 return 0;
341 }
342
343 /*
344 * Command send function for invalidating a device table entry
345 */
346 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
347 {
348 struct iommu_cmd cmd;
349 int ret;
350
351 BUG_ON(iommu == NULL);
352
353 memset(&cmd, 0, sizeof(cmd));
354 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
355 cmd.data[0] = devid;
356
357 ret = iommu_queue_command(iommu, &cmd);
358
359 return ret;
360 }
361
362 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
363 u16 domid, int pde, int s)
364 {
365 memset(cmd, 0, sizeof(*cmd));
366 address &= PAGE_MASK;
367 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
368 cmd->data[1] |= domid;
369 cmd->data[2] = lower_32_bits(address);
370 cmd->data[3] = upper_32_bits(address);
371 if (s) /* size bit - we flush more than one 4kb page */
372 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
373 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
374 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
375 }
376
377 /*
378 * Generic command send function for invalidaing TLB entries
379 */
380 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
381 u64 address, u16 domid, int pde, int s)
382 {
383 struct iommu_cmd cmd;
384 int ret;
385
386 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
387
388 ret = iommu_queue_command(iommu, &cmd);
389
390 return ret;
391 }
392
393 /*
394 * TLB invalidation function which is called from the mapping functions.
395 * It invalidates a single PTE if the range to flush is within a single
396 * page. Otherwise it flushes the whole TLB of the IOMMU.
397 */
398 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
399 u64 address, size_t size)
400 {
401 int s = 0;
402 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
403
404 address &= PAGE_MASK;
405
406 if (pages > 1) {
407 /*
408 * If we have to flush more than one page, flush all
409 * TLB entries for this domain
410 */
411 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
412 s = 1;
413 }
414
415 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
416
417 return 0;
418 }
419
420 /* Flush the whole IO/TLB for a given protection domain */
421 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
422 {
423 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
424
425 INC_STATS_COUNTER(domain_flush_single);
426
427 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
428 }
429
430 /*
431 * This function is used to flush the IO/TLB for a given protection domain
432 * on every IOMMU in the system
433 */
434 static void iommu_flush_domain(u16 domid)
435 {
436 unsigned long flags;
437 struct amd_iommu *iommu;
438 struct iommu_cmd cmd;
439
440 INC_STATS_COUNTER(domain_flush_all);
441
442 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
443 domid, 1, 1);
444
445 list_for_each_entry(iommu, &amd_iommu_list, list) {
446 spin_lock_irqsave(&iommu->lock, flags);
447 __iommu_queue_command(iommu, &cmd);
448 __iommu_completion_wait(iommu);
449 __iommu_wait_for_completion(iommu);
450 spin_unlock_irqrestore(&iommu->lock, flags);
451 }
452 }
453
454 /****************************************************************************
455 *
456 * The functions below are used the create the page table mappings for
457 * unity mapped regions.
458 *
459 ****************************************************************************/
460
461 /*
462 * Generic mapping functions. It maps a physical address into a DMA
463 * address space. It allocates the page table pages if necessary.
464 * In the future it can be extended to a generic mapping function
465 * supporting all features of AMD IOMMU page tables like level skipping
466 * and full 64 bit address spaces.
467 */
468 static int iommu_map_page(struct protection_domain *dom,
469 unsigned long bus_addr,
470 unsigned long phys_addr,
471 int prot)
472 {
473 u64 __pte, *pte;
474
475 bus_addr = PAGE_ALIGN(bus_addr);
476 phys_addr = PAGE_ALIGN(phys_addr);
477
478 /* only support 512GB address spaces for now */
479 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
480 return -EINVAL;
481
482 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
483
484 if (IOMMU_PTE_PRESENT(*pte))
485 return -EBUSY;
486
487 __pte = phys_addr | IOMMU_PTE_P;
488 if (prot & IOMMU_PROT_IR)
489 __pte |= IOMMU_PTE_IR;
490 if (prot & IOMMU_PROT_IW)
491 __pte |= IOMMU_PTE_IW;
492
493 *pte = __pte;
494
495 return 0;
496 }
497
498 static void iommu_unmap_page(struct protection_domain *dom,
499 unsigned long bus_addr)
500 {
501 u64 *pte;
502
503 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
504
505 if (!IOMMU_PTE_PRESENT(*pte))
506 return;
507
508 pte = IOMMU_PTE_PAGE(*pte);
509 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
510
511 if (!IOMMU_PTE_PRESENT(*pte))
512 return;
513
514 pte = IOMMU_PTE_PAGE(*pte);
515 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
516
517 *pte = 0;
518 }
519
520 /*
521 * This function checks if a specific unity mapping entry is needed for
522 * this specific IOMMU.
523 */
524 static int iommu_for_unity_map(struct amd_iommu *iommu,
525 struct unity_map_entry *entry)
526 {
527 u16 bdf, i;
528
529 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
530 bdf = amd_iommu_alias_table[i];
531 if (amd_iommu_rlookup_table[bdf] == iommu)
532 return 1;
533 }
534
535 return 0;
536 }
537
538 /*
539 * Init the unity mappings for a specific IOMMU in the system
540 *
541 * Basically iterates over all unity mapping entries and applies them to
542 * the default domain DMA of that IOMMU if necessary.
543 */
544 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
545 {
546 struct unity_map_entry *entry;
547 int ret;
548
549 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
550 if (!iommu_for_unity_map(iommu, entry))
551 continue;
552 ret = dma_ops_unity_map(iommu->default_dom, entry);
553 if (ret)
554 return ret;
555 }
556
557 return 0;
558 }
559
560 /*
561 * This function actually applies the mapping to the page table of the
562 * dma_ops domain.
563 */
564 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
565 struct unity_map_entry *e)
566 {
567 u64 addr;
568 int ret;
569
570 for (addr = e->address_start; addr < e->address_end;
571 addr += PAGE_SIZE) {
572 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
573 if (ret)
574 return ret;
575 /*
576 * if unity mapping is in aperture range mark the page
577 * as allocated in the aperture
578 */
579 if (addr < dma_dom->aperture_size)
580 __set_bit(addr >> PAGE_SHIFT,
581 dma_dom->aperture[0]->bitmap);
582 }
583
584 return 0;
585 }
586
587 /*
588 * Inits the unity mappings required for a specific device
589 */
590 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
591 u16 devid)
592 {
593 struct unity_map_entry *e;
594 int ret;
595
596 list_for_each_entry(e, &amd_iommu_unity_map, list) {
597 if (!(devid >= e->devid_start && devid <= e->devid_end))
598 continue;
599 ret = dma_ops_unity_map(dma_dom, e);
600 if (ret)
601 return ret;
602 }
603
604 return 0;
605 }
606
607 /****************************************************************************
608 *
609 * The next functions belong to the address allocator for the dma_ops
610 * interface functions. They work like the allocators in the other IOMMU
611 * drivers. Its basically a bitmap which marks the allocated pages in
612 * the aperture. Maybe it could be enhanced in the future to a more
613 * efficient allocator.
614 *
615 ****************************************************************************/
616
617 /*
618 * The address allocator core functions.
619 *
620 * called with domain->lock held
621 */
622
623 /*
624 * This function is used to add a new aperture range to an existing
625 * aperture in case of dma_ops domain allocation or address allocation
626 * failure.
627 */
628 static int alloc_new_range(struct dma_ops_domain *dma_dom,
629 bool populate, gfp_t gfp)
630 {
631 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
632
633 if (index >= APERTURE_MAX_RANGES)
634 return -ENOMEM;
635
636 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
637 if (!dma_dom->aperture[index])
638 return -ENOMEM;
639
640 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
641 if (!dma_dom->aperture[index]->bitmap)
642 goto out_free;
643
644 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
645
646 if (populate) {
647 unsigned long address = dma_dom->aperture_size;
648 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
649 u64 *pte, *pte_page;
650
651 for (i = 0; i < num_ptes; ++i) {
652 pte = alloc_pte(&dma_dom->domain, address,
653 &pte_page, gfp);
654 if (!pte)
655 goto out_free;
656
657 dma_dom->aperture[index]->pte_pages[i] = pte_page;
658
659 address += APERTURE_RANGE_SIZE / 64;
660 }
661 }
662
663 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
664
665 return 0;
666
667 out_free:
668 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
669
670 kfree(dma_dom->aperture[index]);
671 dma_dom->aperture[index] = NULL;
672
673 return -ENOMEM;
674 }
675
676 static unsigned long dma_ops_area_alloc(struct device *dev,
677 struct dma_ops_domain *dom,
678 unsigned int pages,
679 unsigned long align_mask,
680 u64 dma_mask,
681 unsigned long start)
682 {
683 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
684 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
685 int i = start >> APERTURE_RANGE_SHIFT;
686 unsigned long boundary_size;
687 unsigned long address = -1;
688 unsigned long limit;
689
690 next_bit >>= PAGE_SHIFT;
691
692 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
693 PAGE_SIZE) >> PAGE_SHIFT;
694
695 for (;i < max_index; ++i) {
696 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
697
698 if (dom->aperture[i]->offset >= dma_mask)
699 break;
700
701 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
702 dma_mask >> PAGE_SHIFT);
703
704 address = iommu_area_alloc(dom->aperture[i]->bitmap,
705 limit, next_bit, pages, 0,
706 boundary_size, align_mask);
707 if (address != -1) {
708 address = dom->aperture[i]->offset +
709 (address << PAGE_SHIFT);
710 dom->next_address = address + (pages << PAGE_SHIFT);
711 break;
712 }
713
714 next_bit = 0;
715 }
716
717 return address;
718 }
719
720 static unsigned long dma_ops_alloc_addresses(struct device *dev,
721 struct dma_ops_domain *dom,
722 unsigned int pages,
723 unsigned long align_mask,
724 u64 dma_mask)
725 {
726 unsigned long address;
727
728 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
729 dma_mask, dom->next_address);
730
731 if (address == -1) {
732 dom->next_address = 0;
733 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
734 dma_mask, 0);
735 dom->need_flush = true;
736 }
737
738 if (unlikely(address == -1))
739 address = bad_dma_address;
740
741 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
742
743 return address;
744 }
745
746 /*
747 * The address free function.
748 *
749 * called with domain->lock held
750 */
751 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
752 unsigned long address,
753 unsigned int pages)
754 {
755 unsigned i = address >> APERTURE_RANGE_SHIFT;
756 struct aperture_range *range = dom->aperture[i];
757
758 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
759
760 if (address >= dom->next_address)
761 dom->need_flush = true;
762
763 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
764
765 iommu_area_free(range->bitmap, address, pages);
766
767 }
768
769 /****************************************************************************
770 *
771 * The next functions belong to the domain allocation. A domain is
772 * allocated for every IOMMU as the default domain. If device isolation
773 * is enabled, every device get its own domain. The most important thing
774 * about domains is the page table mapping the DMA address space they
775 * contain.
776 *
777 ****************************************************************************/
778
779 static u16 domain_id_alloc(void)
780 {
781 unsigned long flags;
782 int id;
783
784 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
785 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
786 BUG_ON(id == 0);
787 if (id > 0 && id < MAX_DOMAIN_ID)
788 __set_bit(id, amd_iommu_pd_alloc_bitmap);
789 else
790 id = 0;
791 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
792
793 return id;
794 }
795
796 static void domain_id_free(int id)
797 {
798 unsigned long flags;
799
800 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
801 if (id > 0 && id < MAX_DOMAIN_ID)
802 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
803 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
804 }
805
806 /*
807 * Used to reserve address ranges in the aperture (e.g. for exclusion
808 * ranges.
809 */
810 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
811 unsigned long start_page,
812 unsigned int pages)
813 {
814 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
815
816 if (start_page + pages > last_page)
817 pages = last_page - start_page;
818
819 for (i = start_page; i < start_page + pages; ++i) {
820 int index = i / APERTURE_RANGE_PAGES;
821 int page = i % APERTURE_RANGE_PAGES;
822 __set_bit(page, dom->aperture[index]->bitmap);
823 }
824 }
825
826 static void free_pagetable(struct protection_domain *domain)
827 {
828 int i, j;
829 u64 *p1, *p2, *p3;
830
831 p1 = domain->pt_root;
832
833 if (!p1)
834 return;
835
836 for (i = 0; i < 512; ++i) {
837 if (!IOMMU_PTE_PRESENT(p1[i]))
838 continue;
839
840 p2 = IOMMU_PTE_PAGE(p1[i]);
841 for (j = 0; j < 512; ++j) {
842 if (!IOMMU_PTE_PRESENT(p2[j]))
843 continue;
844 p3 = IOMMU_PTE_PAGE(p2[j]);
845 free_page((unsigned long)p3);
846 }
847
848 free_page((unsigned long)p2);
849 }
850
851 free_page((unsigned long)p1);
852
853 domain->pt_root = NULL;
854 }
855
856 /*
857 * Free a domain, only used if something went wrong in the
858 * allocation path and we need to free an already allocated page table
859 */
860 static void dma_ops_domain_free(struct dma_ops_domain *dom)
861 {
862 int i;
863
864 if (!dom)
865 return;
866
867 free_pagetable(&dom->domain);
868
869 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
870 if (!dom->aperture[i])
871 continue;
872 free_page((unsigned long)dom->aperture[i]->bitmap);
873 kfree(dom->aperture[i]);
874 }
875
876 kfree(dom);
877 }
878
879 /*
880 * Allocates a new protection domain usable for the dma_ops functions.
881 * It also intializes the page table and the address allocator data
882 * structures required for the dma_ops interface
883 */
884 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
885 unsigned order)
886 {
887 struct dma_ops_domain *dma_dom;
888
889 /*
890 * Currently the DMA aperture must be between 32 MB and 1GB in size
891 */
892 if ((order < 25) || (order > 30))
893 return NULL;
894
895 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
896 if (!dma_dom)
897 return NULL;
898
899 spin_lock_init(&dma_dom->domain.lock);
900
901 dma_dom->domain.id = domain_id_alloc();
902 if (dma_dom->domain.id == 0)
903 goto free_dma_dom;
904 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
905 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
906 dma_dom->domain.flags = PD_DMA_OPS_MASK;
907 dma_dom->domain.priv = dma_dom;
908 if (!dma_dom->domain.pt_root)
909 goto free_dma_dom;
910
911 dma_dom->need_flush = false;
912 dma_dom->target_dev = 0xffff;
913
914 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
915 goto free_dma_dom;
916
917 /*
918 * mark the first page as allocated so we never return 0 as
919 * a valid dma-address. So we can use 0 as error value
920 */
921 dma_dom->aperture[0]->bitmap[0] = 1;
922 dma_dom->next_address = 0;
923
924 /* Intialize the exclusion range if necessary */
925 if (iommu->exclusion_start &&
926 iommu->exclusion_start < dma_dom->aperture_size) {
927 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
928 int pages = iommu_num_pages(iommu->exclusion_start,
929 iommu->exclusion_length,
930 PAGE_SIZE);
931 dma_ops_reserve_addresses(dma_dom, startpage, pages);
932 }
933
934 return dma_dom;
935
936 free_dma_dom:
937 dma_ops_domain_free(dma_dom);
938
939 return NULL;
940 }
941
942 /*
943 * little helper function to check whether a given protection domain is a
944 * dma_ops domain
945 */
946 static bool dma_ops_domain(struct protection_domain *domain)
947 {
948 return domain->flags & PD_DMA_OPS_MASK;
949 }
950
951 /*
952 * Find out the protection domain structure for a given PCI device. This
953 * will give us the pointer to the page table root for example.
954 */
955 static struct protection_domain *domain_for_device(u16 devid)
956 {
957 struct protection_domain *dom;
958 unsigned long flags;
959
960 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
961 dom = amd_iommu_pd_table[devid];
962 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
963
964 return dom;
965 }
966
967 /*
968 * If a device is not yet associated with a domain, this function does
969 * assigns it visible for the hardware
970 */
971 static void attach_device(struct amd_iommu *iommu,
972 struct protection_domain *domain,
973 u16 devid)
974 {
975 unsigned long flags;
976 u64 pte_root = virt_to_phys(domain->pt_root);
977
978 domain->dev_cnt += 1;
979
980 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
981 << DEV_ENTRY_MODE_SHIFT;
982 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
983
984 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
985 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
986 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
987 amd_iommu_dev_table[devid].data[2] = domain->id;
988
989 amd_iommu_pd_table[devid] = domain;
990 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
991
992 iommu_queue_inv_dev_entry(iommu, devid);
993 }
994
995 /*
996 * Removes a device from a protection domain (unlocked)
997 */
998 static void __detach_device(struct protection_domain *domain, u16 devid)
999 {
1000
1001 /* lock domain */
1002 spin_lock(&domain->lock);
1003
1004 /* remove domain from the lookup table */
1005 amd_iommu_pd_table[devid] = NULL;
1006
1007 /* remove entry from the device table seen by the hardware */
1008 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1009 amd_iommu_dev_table[devid].data[1] = 0;
1010 amd_iommu_dev_table[devid].data[2] = 0;
1011
1012 /* decrease reference counter */
1013 domain->dev_cnt -= 1;
1014
1015 /* ready */
1016 spin_unlock(&domain->lock);
1017 }
1018
1019 /*
1020 * Removes a device from a protection domain (with devtable_lock held)
1021 */
1022 static void detach_device(struct protection_domain *domain, u16 devid)
1023 {
1024 unsigned long flags;
1025
1026 /* lock device table */
1027 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1028 __detach_device(domain, devid);
1029 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1030 }
1031
1032 static int device_change_notifier(struct notifier_block *nb,
1033 unsigned long action, void *data)
1034 {
1035 struct device *dev = data;
1036 struct pci_dev *pdev = to_pci_dev(dev);
1037 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1038 struct protection_domain *domain;
1039 struct dma_ops_domain *dma_domain;
1040 struct amd_iommu *iommu;
1041 int order = amd_iommu_aperture_order;
1042 unsigned long flags;
1043
1044 if (devid > amd_iommu_last_bdf)
1045 goto out;
1046
1047 devid = amd_iommu_alias_table[devid];
1048
1049 iommu = amd_iommu_rlookup_table[devid];
1050 if (iommu == NULL)
1051 goto out;
1052
1053 domain = domain_for_device(devid);
1054
1055 if (domain && !dma_ops_domain(domain))
1056 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1057 "to a non-dma-ops domain\n", dev_name(dev));
1058
1059 switch (action) {
1060 case BUS_NOTIFY_BOUND_DRIVER:
1061 if (domain)
1062 goto out;
1063 dma_domain = find_protection_domain(devid);
1064 if (!dma_domain)
1065 dma_domain = iommu->default_dom;
1066 attach_device(iommu, &dma_domain->domain, devid);
1067 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1068 "device %s\n", dma_domain->domain.id, dev_name(dev));
1069 break;
1070 case BUS_NOTIFY_UNBIND_DRIVER:
1071 if (!domain)
1072 goto out;
1073 detach_device(domain, devid);
1074 break;
1075 case BUS_NOTIFY_ADD_DEVICE:
1076 /* allocate a protection domain if a device is added */
1077 dma_domain = find_protection_domain(devid);
1078 if (dma_domain)
1079 goto out;
1080 dma_domain = dma_ops_domain_alloc(iommu, order);
1081 if (!dma_domain)
1082 goto out;
1083 dma_domain->target_dev = devid;
1084
1085 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1086 list_add_tail(&dma_domain->list, &iommu_pd_list);
1087 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1088
1089 break;
1090 default:
1091 goto out;
1092 }
1093
1094 iommu_queue_inv_dev_entry(iommu, devid);
1095 iommu_completion_wait(iommu);
1096
1097 out:
1098 return 0;
1099 }
1100
1101 struct notifier_block device_nb = {
1102 .notifier_call = device_change_notifier,
1103 };
1104
1105 /*****************************************************************************
1106 *
1107 * The next functions belong to the dma_ops mapping/unmapping code.
1108 *
1109 *****************************************************************************/
1110
1111 /*
1112 * This function checks if the driver got a valid device from the caller to
1113 * avoid dereferencing invalid pointers.
1114 */
1115 static bool check_device(struct device *dev)
1116 {
1117 if (!dev || !dev->dma_mask)
1118 return false;
1119
1120 return true;
1121 }
1122
1123 /*
1124 * In this function the list of preallocated protection domains is traversed to
1125 * find the domain for a specific device
1126 */
1127 static struct dma_ops_domain *find_protection_domain(u16 devid)
1128 {
1129 struct dma_ops_domain *entry, *ret = NULL;
1130 unsigned long flags;
1131
1132 if (list_empty(&iommu_pd_list))
1133 return NULL;
1134
1135 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1136
1137 list_for_each_entry(entry, &iommu_pd_list, list) {
1138 if (entry->target_dev == devid) {
1139 ret = entry;
1140 break;
1141 }
1142 }
1143
1144 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1145
1146 return ret;
1147 }
1148
1149 /*
1150 * In the dma_ops path we only have the struct device. This function
1151 * finds the corresponding IOMMU, the protection domain and the
1152 * requestor id for a given device.
1153 * If the device is not yet associated with a domain this is also done
1154 * in this function.
1155 */
1156 static int get_device_resources(struct device *dev,
1157 struct amd_iommu **iommu,
1158 struct protection_domain **domain,
1159 u16 *bdf)
1160 {
1161 struct dma_ops_domain *dma_dom;
1162 struct pci_dev *pcidev;
1163 u16 _bdf;
1164
1165 *iommu = NULL;
1166 *domain = NULL;
1167 *bdf = 0xffff;
1168
1169 if (dev->bus != &pci_bus_type)
1170 return 0;
1171
1172 pcidev = to_pci_dev(dev);
1173 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1174
1175 /* device not translated by any IOMMU in the system? */
1176 if (_bdf > amd_iommu_last_bdf)
1177 return 0;
1178
1179 *bdf = amd_iommu_alias_table[_bdf];
1180
1181 *iommu = amd_iommu_rlookup_table[*bdf];
1182 if (*iommu == NULL)
1183 return 0;
1184 *domain = domain_for_device(*bdf);
1185 if (*domain == NULL) {
1186 dma_dom = find_protection_domain(*bdf);
1187 if (!dma_dom)
1188 dma_dom = (*iommu)->default_dom;
1189 *domain = &dma_dom->domain;
1190 attach_device(*iommu, *domain, *bdf);
1191 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1192 "device %s\n", (*domain)->id, dev_name(dev));
1193 }
1194
1195 if (domain_for_device(_bdf) == NULL)
1196 attach_device(*iommu, *domain, _bdf);
1197
1198 return 1;
1199 }
1200
1201 /*
1202 * If the pte_page is not yet allocated this function is called
1203 */
1204 static u64* alloc_pte(struct protection_domain *dom,
1205 unsigned long address, u64 **pte_page, gfp_t gfp)
1206 {
1207 u64 *pte, *page;
1208
1209 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1210
1211 if (!IOMMU_PTE_PRESENT(*pte)) {
1212 page = (u64 *)get_zeroed_page(gfp);
1213 if (!page)
1214 return NULL;
1215 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1216 }
1217
1218 pte = IOMMU_PTE_PAGE(*pte);
1219 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1220
1221 if (!IOMMU_PTE_PRESENT(*pte)) {
1222 page = (u64 *)get_zeroed_page(gfp);
1223 if (!page)
1224 return NULL;
1225 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1226 }
1227
1228 pte = IOMMU_PTE_PAGE(*pte);
1229
1230 if (pte_page)
1231 *pte_page = pte;
1232
1233 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1234
1235 return pte;
1236 }
1237
1238 /*
1239 * This function fetches the PTE for a given address in the aperture
1240 */
1241 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1242 unsigned long address)
1243 {
1244 struct aperture_range *aperture;
1245 u64 *pte, *pte_page;
1246
1247 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1248 if (!aperture)
1249 return NULL;
1250
1251 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1252 if (!pte) {
1253 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1254 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1255 } else
1256 pte += IOMMU_PTE_L0_INDEX(address);
1257
1258 return pte;
1259 }
1260
1261 /*
1262 * This is the generic map function. It maps one 4kb page at paddr to
1263 * the given address in the DMA address space for the domain.
1264 */
1265 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1266 struct dma_ops_domain *dom,
1267 unsigned long address,
1268 phys_addr_t paddr,
1269 int direction)
1270 {
1271 u64 *pte, __pte;
1272
1273 WARN_ON(address > dom->aperture_size);
1274
1275 paddr &= PAGE_MASK;
1276
1277 pte = dma_ops_get_pte(dom, address);
1278 if (!pte)
1279 return bad_dma_address;
1280
1281 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1282
1283 if (direction == DMA_TO_DEVICE)
1284 __pte |= IOMMU_PTE_IR;
1285 else if (direction == DMA_FROM_DEVICE)
1286 __pte |= IOMMU_PTE_IW;
1287 else if (direction == DMA_BIDIRECTIONAL)
1288 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1289
1290 WARN_ON(*pte);
1291
1292 *pte = __pte;
1293
1294 return (dma_addr_t)address;
1295 }
1296
1297 /*
1298 * The generic unmapping function for on page in the DMA address space.
1299 */
1300 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1301 struct dma_ops_domain *dom,
1302 unsigned long address)
1303 {
1304 struct aperture_range *aperture;
1305 u64 *pte;
1306
1307 if (address >= dom->aperture_size)
1308 return;
1309
1310 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1311 if (!aperture)
1312 return;
1313
1314 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1315 if (!pte)
1316 return;
1317
1318 pte += IOMMU_PTE_L0_INDEX(address);
1319
1320 WARN_ON(!*pte);
1321
1322 *pte = 0ULL;
1323 }
1324
1325 /*
1326 * This function contains common code for mapping of a physically
1327 * contiguous memory region into DMA address space. It is used by all
1328 * mapping functions provided with this IOMMU driver.
1329 * Must be called with the domain lock held.
1330 */
1331 static dma_addr_t __map_single(struct device *dev,
1332 struct amd_iommu *iommu,
1333 struct dma_ops_domain *dma_dom,
1334 phys_addr_t paddr,
1335 size_t size,
1336 int dir,
1337 bool align,
1338 u64 dma_mask)
1339 {
1340 dma_addr_t offset = paddr & ~PAGE_MASK;
1341 dma_addr_t address, start, ret;
1342 unsigned int pages;
1343 unsigned long align_mask = 0;
1344 int i;
1345
1346 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1347 paddr &= PAGE_MASK;
1348
1349 INC_STATS_COUNTER(total_map_requests);
1350
1351 if (pages > 1)
1352 INC_STATS_COUNTER(cross_page);
1353
1354 if (align)
1355 align_mask = (1UL << get_order(size)) - 1;
1356
1357 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1358 dma_mask);
1359 if (unlikely(address == bad_dma_address))
1360 goto out;
1361
1362 start = address;
1363 for (i = 0; i < pages; ++i) {
1364 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1365 if (ret == bad_dma_address)
1366 goto out_unmap;
1367
1368 paddr += PAGE_SIZE;
1369 start += PAGE_SIZE;
1370 }
1371 address += offset;
1372
1373 ADD_STATS_COUNTER(alloced_io_mem, size);
1374
1375 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1376 iommu_flush_tlb(iommu, dma_dom->domain.id);
1377 dma_dom->need_flush = false;
1378 } else if (unlikely(iommu_has_npcache(iommu)))
1379 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1380
1381 out:
1382 return address;
1383
1384 out_unmap:
1385
1386 for (--i; i >= 0; --i) {
1387 start -= PAGE_SIZE;
1388 dma_ops_domain_unmap(iommu, dma_dom, start);
1389 }
1390
1391 dma_ops_free_addresses(dma_dom, address, pages);
1392
1393 return bad_dma_address;
1394 }
1395
1396 /*
1397 * Does the reverse of the __map_single function. Must be called with
1398 * the domain lock held too
1399 */
1400 static void __unmap_single(struct amd_iommu *iommu,
1401 struct dma_ops_domain *dma_dom,
1402 dma_addr_t dma_addr,
1403 size_t size,
1404 int dir)
1405 {
1406 dma_addr_t i, start;
1407 unsigned int pages;
1408
1409 if ((dma_addr == bad_dma_address) ||
1410 (dma_addr + size > dma_dom->aperture_size))
1411 return;
1412
1413 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1414 dma_addr &= PAGE_MASK;
1415 start = dma_addr;
1416
1417 for (i = 0; i < pages; ++i) {
1418 dma_ops_domain_unmap(iommu, dma_dom, start);
1419 start += PAGE_SIZE;
1420 }
1421
1422 SUB_STATS_COUNTER(alloced_io_mem, size);
1423
1424 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1425
1426 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1427 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1428 dma_dom->need_flush = false;
1429 }
1430 }
1431
1432 /*
1433 * The exported map_single function for dma_ops.
1434 */
1435 static dma_addr_t map_page(struct device *dev, struct page *page,
1436 unsigned long offset, size_t size,
1437 enum dma_data_direction dir,
1438 struct dma_attrs *attrs)
1439 {
1440 unsigned long flags;
1441 struct amd_iommu *iommu;
1442 struct protection_domain *domain;
1443 u16 devid;
1444 dma_addr_t addr;
1445 u64 dma_mask;
1446 phys_addr_t paddr = page_to_phys(page) + offset;
1447
1448 INC_STATS_COUNTER(cnt_map_single);
1449
1450 if (!check_device(dev))
1451 return bad_dma_address;
1452
1453 dma_mask = *dev->dma_mask;
1454
1455 get_device_resources(dev, &iommu, &domain, &devid);
1456
1457 if (iommu == NULL || domain == NULL)
1458 /* device not handled by any AMD IOMMU */
1459 return (dma_addr_t)paddr;
1460
1461 if (!dma_ops_domain(domain))
1462 return bad_dma_address;
1463
1464 spin_lock_irqsave(&domain->lock, flags);
1465 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1466 dma_mask);
1467 if (addr == bad_dma_address)
1468 goto out;
1469
1470 iommu_completion_wait(iommu);
1471
1472 out:
1473 spin_unlock_irqrestore(&domain->lock, flags);
1474
1475 return addr;
1476 }
1477
1478 /*
1479 * The exported unmap_single function for dma_ops.
1480 */
1481 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1482 enum dma_data_direction dir, struct dma_attrs *attrs)
1483 {
1484 unsigned long flags;
1485 struct amd_iommu *iommu;
1486 struct protection_domain *domain;
1487 u16 devid;
1488
1489 INC_STATS_COUNTER(cnt_unmap_single);
1490
1491 if (!check_device(dev) ||
1492 !get_device_resources(dev, &iommu, &domain, &devid))
1493 /* device not handled by any AMD IOMMU */
1494 return;
1495
1496 if (!dma_ops_domain(domain))
1497 return;
1498
1499 spin_lock_irqsave(&domain->lock, flags);
1500
1501 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1502
1503 iommu_completion_wait(iommu);
1504
1505 spin_unlock_irqrestore(&domain->lock, flags);
1506 }
1507
1508 /*
1509 * This is a special map_sg function which is used if we should map a
1510 * device which is not handled by an AMD IOMMU in the system.
1511 */
1512 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1513 int nelems, int dir)
1514 {
1515 struct scatterlist *s;
1516 int i;
1517
1518 for_each_sg(sglist, s, nelems, i) {
1519 s->dma_address = (dma_addr_t)sg_phys(s);
1520 s->dma_length = s->length;
1521 }
1522
1523 return nelems;
1524 }
1525
1526 /*
1527 * The exported map_sg function for dma_ops (handles scatter-gather
1528 * lists).
1529 */
1530 static int map_sg(struct device *dev, struct scatterlist *sglist,
1531 int nelems, enum dma_data_direction dir,
1532 struct dma_attrs *attrs)
1533 {
1534 unsigned long flags;
1535 struct amd_iommu *iommu;
1536 struct protection_domain *domain;
1537 u16 devid;
1538 int i;
1539 struct scatterlist *s;
1540 phys_addr_t paddr;
1541 int mapped_elems = 0;
1542 u64 dma_mask;
1543
1544 INC_STATS_COUNTER(cnt_map_sg);
1545
1546 if (!check_device(dev))
1547 return 0;
1548
1549 dma_mask = *dev->dma_mask;
1550
1551 get_device_resources(dev, &iommu, &domain, &devid);
1552
1553 if (!iommu || !domain)
1554 return map_sg_no_iommu(dev, sglist, nelems, dir);
1555
1556 if (!dma_ops_domain(domain))
1557 return 0;
1558
1559 spin_lock_irqsave(&domain->lock, flags);
1560
1561 for_each_sg(sglist, s, nelems, i) {
1562 paddr = sg_phys(s);
1563
1564 s->dma_address = __map_single(dev, iommu, domain->priv,
1565 paddr, s->length, dir, false,
1566 dma_mask);
1567
1568 if (s->dma_address) {
1569 s->dma_length = s->length;
1570 mapped_elems++;
1571 } else
1572 goto unmap;
1573 }
1574
1575 iommu_completion_wait(iommu);
1576
1577 out:
1578 spin_unlock_irqrestore(&domain->lock, flags);
1579
1580 return mapped_elems;
1581 unmap:
1582 for_each_sg(sglist, s, mapped_elems, i) {
1583 if (s->dma_address)
1584 __unmap_single(iommu, domain->priv, s->dma_address,
1585 s->dma_length, dir);
1586 s->dma_address = s->dma_length = 0;
1587 }
1588
1589 mapped_elems = 0;
1590
1591 goto out;
1592 }
1593
1594 /*
1595 * The exported map_sg function for dma_ops (handles scatter-gather
1596 * lists).
1597 */
1598 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1599 int nelems, enum dma_data_direction dir,
1600 struct dma_attrs *attrs)
1601 {
1602 unsigned long flags;
1603 struct amd_iommu *iommu;
1604 struct protection_domain *domain;
1605 struct scatterlist *s;
1606 u16 devid;
1607 int i;
1608
1609 INC_STATS_COUNTER(cnt_unmap_sg);
1610
1611 if (!check_device(dev) ||
1612 !get_device_resources(dev, &iommu, &domain, &devid))
1613 return;
1614
1615 if (!dma_ops_domain(domain))
1616 return;
1617
1618 spin_lock_irqsave(&domain->lock, flags);
1619
1620 for_each_sg(sglist, s, nelems, i) {
1621 __unmap_single(iommu, domain->priv, s->dma_address,
1622 s->dma_length, dir);
1623 s->dma_address = s->dma_length = 0;
1624 }
1625
1626 iommu_completion_wait(iommu);
1627
1628 spin_unlock_irqrestore(&domain->lock, flags);
1629 }
1630
1631 /*
1632 * The exported alloc_coherent function for dma_ops.
1633 */
1634 static void *alloc_coherent(struct device *dev, size_t size,
1635 dma_addr_t *dma_addr, gfp_t flag)
1636 {
1637 unsigned long flags;
1638 void *virt_addr;
1639 struct amd_iommu *iommu;
1640 struct protection_domain *domain;
1641 u16 devid;
1642 phys_addr_t paddr;
1643 u64 dma_mask = dev->coherent_dma_mask;
1644
1645 INC_STATS_COUNTER(cnt_alloc_coherent);
1646
1647 if (!check_device(dev))
1648 return NULL;
1649
1650 if (!get_device_resources(dev, &iommu, &domain, &devid))
1651 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1652
1653 flag |= __GFP_ZERO;
1654 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1655 if (!virt_addr)
1656 return 0;
1657
1658 paddr = virt_to_phys(virt_addr);
1659
1660 if (!iommu || !domain) {
1661 *dma_addr = (dma_addr_t)paddr;
1662 return virt_addr;
1663 }
1664
1665 if (!dma_ops_domain(domain))
1666 goto out_free;
1667
1668 if (!dma_mask)
1669 dma_mask = *dev->dma_mask;
1670
1671 spin_lock_irqsave(&domain->lock, flags);
1672
1673 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1674 size, DMA_BIDIRECTIONAL, true, dma_mask);
1675
1676 if (*dma_addr == bad_dma_address)
1677 goto out_free;
1678
1679 iommu_completion_wait(iommu);
1680
1681 spin_unlock_irqrestore(&domain->lock, flags);
1682
1683 return virt_addr;
1684
1685 out_free:
1686
1687 free_pages((unsigned long)virt_addr, get_order(size));
1688
1689 return NULL;
1690 }
1691
1692 /*
1693 * The exported free_coherent function for dma_ops.
1694 */
1695 static void free_coherent(struct device *dev, size_t size,
1696 void *virt_addr, dma_addr_t dma_addr)
1697 {
1698 unsigned long flags;
1699 struct amd_iommu *iommu;
1700 struct protection_domain *domain;
1701 u16 devid;
1702
1703 INC_STATS_COUNTER(cnt_free_coherent);
1704
1705 if (!check_device(dev))
1706 return;
1707
1708 get_device_resources(dev, &iommu, &domain, &devid);
1709
1710 if (!iommu || !domain)
1711 goto free_mem;
1712
1713 if (!dma_ops_domain(domain))
1714 goto free_mem;
1715
1716 spin_lock_irqsave(&domain->lock, flags);
1717
1718 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1719
1720 iommu_completion_wait(iommu);
1721
1722 spin_unlock_irqrestore(&domain->lock, flags);
1723
1724 free_mem:
1725 free_pages((unsigned long)virt_addr, get_order(size));
1726 }
1727
1728 /*
1729 * This function is called by the DMA layer to find out if we can handle a
1730 * particular device. It is part of the dma_ops.
1731 */
1732 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1733 {
1734 u16 bdf;
1735 struct pci_dev *pcidev;
1736
1737 /* No device or no PCI device */
1738 if (!dev || dev->bus != &pci_bus_type)
1739 return 0;
1740
1741 pcidev = to_pci_dev(dev);
1742
1743 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1744
1745 /* Out of our scope? */
1746 if (bdf > amd_iommu_last_bdf)
1747 return 0;
1748
1749 return 1;
1750 }
1751
1752 /*
1753 * The function for pre-allocating protection domains.
1754 *
1755 * If the driver core informs the DMA layer if a driver grabs a device
1756 * we don't need to preallocate the protection domains anymore.
1757 * For now we have to.
1758 */
1759 static void prealloc_protection_domains(void)
1760 {
1761 struct pci_dev *dev = NULL;
1762 struct dma_ops_domain *dma_dom;
1763 struct amd_iommu *iommu;
1764 int order = amd_iommu_aperture_order;
1765 u16 devid;
1766
1767 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1768 devid = calc_devid(dev->bus->number, dev->devfn);
1769 if (devid > amd_iommu_last_bdf)
1770 continue;
1771 devid = amd_iommu_alias_table[devid];
1772 if (domain_for_device(devid))
1773 continue;
1774 iommu = amd_iommu_rlookup_table[devid];
1775 if (!iommu)
1776 continue;
1777 dma_dom = dma_ops_domain_alloc(iommu, order);
1778 if (!dma_dom)
1779 continue;
1780 init_unity_mappings_for_device(dma_dom, devid);
1781 dma_dom->target_dev = devid;
1782
1783 list_add_tail(&dma_dom->list, &iommu_pd_list);
1784 }
1785 }
1786
1787 static struct dma_map_ops amd_iommu_dma_ops = {
1788 .alloc_coherent = alloc_coherent,
1789 .free_coherent = free_coherent,
1790 .map_page = map_page,
1791 .unmap_page = unmap_page,
1792 .map_sg = map_sg,
1793 .unmap_sg = unmap_sg,
1794 .dma_supported = amd_iommu_dma_supported,
1795 };
1796
1797 /*
1798 * The function which clues the AMD IOMMU driver into dma_ops.
1799 */
1800 int __init amd_iommu_init_dma_ops(void)
1801 {
1802 struct amd_iommu *iommu;
1803 int order = amd_iommu_aperture_order;
1804 int ret;
1805
1806 /*
1807 * first allocate a default protection domain for every IOMMU we
1808 * found in the system. Devices not assigned to any other
1809 * protection domain will be assigned to the default one.
1810 */
1811 list_for_each_entry(iommu, &amd_iommu_list, list) {
1812 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1813 if (iommu->default_dom == NULL)
1814 return -ENOMEM;
1815 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1816 ret = iommu_init_unity_mappings(iommu);
1817 if (ret)
1818 goto free_domains;
1819 }
1820
1821 /*
1822 * If device isolation is enabled, pre-allocate the protection
1823 * domains for each device.
1824 */
1825 if (amd_iommu_isolate)
1826 prealloc_protection_domains();
1827
1828 iommu_detected = 1;
1829 force_iommu = 1;
1830 bad_dma_address = 0;
1831 #ifdef CONFIG_GART_IOMMU
1832 gart_iommu_aperture_disabled = 1;
1833 gart_iommu_aperture = 0;
1834 #endif
1835
1836 /* Make the driver finally visible to the drivers */
1837 dma_ops = &amd_iommu_dma_ops;
1838
1839 register_iommu(&amd_iommu_ops);
1840
1841 bus_register_notifier(&pci_bus_type, &device_nb);
1842
1843 amd_iommu_stats_init();
1844
1845 return 0;
1846
1847 free_domains:
1848
1849 list_for_each_entry(iommu, &amd_iommu_list, list) {
1850 if (iommu->default_dom)
1851 dma_ops_domain_free(iommu->default_dom);
1852 }
1853
1854 return ret;
1855 }
1856
1857 /*****************************************************************************
1858 *
1859 * The following functions belong to the exported interface of AMD IOMMU
1860 *
1861 * This interface allows access to lower level functions of the IOMMU
1862 * like protection domain handling and assignement of devices to domains
1863 * which is not possible with the dma_ops interface.
1864 *
1865 *****************************************************************************/
1866
1867 static void cleanup_domain(struct protection_domain *domain)
1868 {
1869 unsigned long flags;
1870 u16 devid;
1871
1872 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1873
1874 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1875 if (amd_iommu_pd_table[devid] == domain)
1876 __detach_device(domain, devid);
1877
1878 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1879 }
1880
1881 static int amd_iommu_domain_init(struct iommu_domain *dom)
1882 {
1883 struct protection_domain *domain;
1884
1885 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1886 if (!domain)
1887 return -ENOMEM;
1888
1889 spin_lock_init(&domain->lock);
1890 domain->mode = PAGE_MODE_3_LEVEL;
1891 domain->id = domain_id_alloc();
1892 if (!domain->id)
1893 goto out_free;
1894 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1895 if (!domain->pt_root)
1896 goto out_free;
1897
1898 dom->priv = domain;
1899
1900 return 0;
1901
1902 out_free:
1903 kfree(domain);
1904
1905 return -ENOMEM;
1906 }
1907
1908 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1909 {
1910 struct protection_domain *domain = dom->priv;
1911
1912 if (!domain)
1913 return;
1914
1915 if (domain->dev_cnt > 0)
1916 cleanup_domain(domain);
1917
1918 BUG_ON(domain->dev_cnt != 0);
1919
1920 free_pagetable(domain);
1921
1922 domain_id_free(domain->id);
1923
1924 kfree(domain);
1925
1926 dom->priv = NULL;
1927 }
1928
1929 static void amd_iommu_detach_device(struct iommu_domain *dom,
1930 struct device *dev)
1931 {
1932 struct protection_domain *domain = dom->priv;
1933 struct amd_iommu *iommu;
1934 struct pci_dev *pdev;
1935 u16 devid;
1936
1937 if (dev->bus != &pci_bus_type)
1938 return;
1939
1940 pdev = to_pci_dev(dev);
1941
1942 devid = calc_devid(pdev->bus->number, pdev->devfn);
1943
1944 if (devid > 0)
1945 detach_device(domain, devid);
1946
1947 iommu = amd_iommu_rlookup_table[devid];
1948 if (!iommu)
1949 return;
1950
1951 iommu_queue_inv_dev_entry(iommu, devid);
1952 iommu_completion_wait(iommu);
1953 }
1954
1955 static int amd_iommu_attach_device(struct iommu_domain *dom,
1956 struct device *dev)
1957 {
1958 struct protection_domain *domain = dom->priv;
1959 struct protection_domain *old_domain;
1960 struct amd_iommu *iommu;
1961 struct pci_dev *pdev;
1962 u16 devid;
1963
1964 if (dev->bus != &pci_bus_type)
1965 return -EINVAL;
1966
1967 pdev = to_pci_dev(dev);
1968
1969 devid = calc_devid(pdev->bus->number, pdev->devfn);
1970
1971 if (devid >= amd_iommu_last_bdf ||
1972 devid != amd_iommu_alias_table[devid])
1973 return -EINVAL;
1974
1975 iommu = amd_iommu_rlookup_table[devid];
1976 if (!iommu)
1977 return -EINVAL;
1978
1979 old_domain = domain_for_device(devid);
1980 if (old_domain)
1981 return -EBUSY;
1982
1983 attach_device(iommu, domain, devid);
1984
1985 iommu_completion_wait(iommu);
1986
1987 return 0;
1988 }
1989
1990 static int amd_iommu_map_range(struct iommu_domain *dom,
1991 unsigned long iova, phys_addr_t paddr,
1992 size_t size, int iommu_prot)
1993 {
1994 struct protection_domain *domain = dom->priv;
1995 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1996 int prot = 0;
1997 int ret;
1998
1999 if (iommu_prot & IOMMU_READ)
2000 prot |= IOMMU_PROT_IR;
2001 if (iommu_prot & IOMMU_WRITE)
2002 prot |= IOMMU_PROT_IW;
2003
2004 iova &= PAGE_MASK;
2005 paddr &= PAGE_MASK;
2006
2007 for (i = 0; i < npages; ++i) {
2008 ret = iommu_map_page(domain, iova, paddr, prot);
2009 if (ret)
2010 return ret;
2011
2012 iova += PAGE_SIZE;
2013 paddr += PAGE_SIZE;
2014 }
2015
2016 return 0;
2017 }
2018
2019 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2020 unsigned long iova, size_t size)
2021 {
2022
2023 struct protection_domain *domain = dom->priv;
2024 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2025
2026 iova &= PAGE_MASK;
2027
2028 for (i = 0; i < npages; ++i) {
2029 iommu_unmap_page(domain, iova);
2030 iova += PAGE_SIZE;
2031 }
2032
2033 iommu_flush_domain(domain->id);
2034 }
2035
2036 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2037 unsigned long iova)
2038 {
2039 struct protection_domain *domain = dom->priv;
2040 unsigned long offset = iova & ~PAGE_MASK;
2041 phys_addr_t paddr;
2042 u64 *pte;
2043
2044 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2045
2046 if (!IOMMU_PTE_PRESENT(*pte))
2047 return 0;
2048
2049 pte = IOMMU_PTE_PAGE(*pte);
2050 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2051
2052 if (!IOMMU_PTE_PRESENT(*pte))
2053 return 0;
2054
2055 pte = IOMMU_PTE_PAGE(*pte);
2056 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2057
2058 if (!IOMMU_PTE_PRESENT(*pte))
2059 return 0;
2060
2061 paddr = *pte & IOMMU_PAGE_MASK;
2062 paddr |= offset;
2063
2064 return paddr;
2065 }
2066
2067 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2068 unsigned long cap)
2069 {
2070 return 0;
2071 }
2072
2073 static struct iommu_ops amd_iommu_ops = {
2074 .domain_init = amd_iommu_domain_init,
2075 .domain_destroy = amd_iommu_domain_destroy,
2076 .attach_dev = amd_iommu_attach_device,
2077 .detach_dev = amd_iommu_detach_device,
2078 .map = amd_iommu_map_range,
2079 .unmap = amd_iommu_unmap_range,
2080 .iova_to_phys = amd_iommu_iova_to_phys,
2081 .domain_has_cap = amd_iommu_domain_has_cap,
2082 };
2083
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