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amd-iommu: move page table allocation code to seperate function
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kernel / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
33
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
35
36 #define EXIT_LOOP_COUNT 10000000
37
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
39
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
43
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
46 #endif
47
48 /*
49 * general struct to manage commands send to an IOMMU
50 */
51 struct iommu_cmd {
52 u32 data[4];
53 };
54
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61
62 #ifdef CONFIG_AMD_IOMMU_STATS
63
64 /*
65 * Initialization code for statistics collection
66 */
67
68 DECLARE_STATS_COUNTER(compl_wait);
69 DECLARE_STATS_COUNTER(cnt_map_single);
70 DECLARE_STATS_COUNTER(cnt_unmap_single);
71 DECLARE_STATS_COUNTER(cnt_map_sg);
72 DECLARE_STATS_COUNTER(cnt_unmap_sg);
73 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
74 DECLARE_STATS_COUNTER(cnt_free_coherent);
75 DECLARE_STATS_COUNTER(cross_page);
76 DECLARE_STATS_COUNTER(domain_flush_single);
77 DECLARE_STATS_COUNTER(domain_flush_all);
78 DECLARE_STATS_COUNTER(alloced_io_mem);
79 DECLARE_STATS_COUNTER(total_map_requests);
80
81 static struct dentry *stats_dir;
82 static struct dentry *de_isolate;
83 static struct dentry *de_fflush;
84
85 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
86 {
87 if (stats_dir == NULL)
88 return;
89
90 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
91 &cnt->value);
92 }
93
94 static void amd_iommu_stats_init(void)
95 {
96 stats_dir = debugfs_create_dir("amd-iommu", NULL);
97 if (stats_dir == NULL)
98 return;
99
100 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
101 (u32 *)&amd_iommu_isolate);
102
103 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
104 (u32 *)&amd_iommu_unmap_flush);
105
106 amd_iommu_stats_add(&compl_wait);
107 amd_iommu_stats_add(&cnt_map_single);
108 amd_iommu_stats_add(&cnt_unmap_single);
109 amd_iommu_stats_add(&cnt_map_sg);
110 amd_iommu_stats_add(&cnt_unmap_sg);
111 amd_iommu_stats_add(&cnt_alloc_coherent);
112 amd_iommu_stats_add(&cnt_free_coherent);
113 amd_iommu_stats_add(&cross_page);
114 amd_iommu_stats_add(&domain_flush_single);
115 amd_iommu_stats_add(&domain_flush_all);
116 amd_iommu_stats_add(&alloced_io_mem);
117 amd_iommu_stats_add(&total_map_requests);
118 }
119
120 #endif
121
122 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
123 static int iommu_has_npcache(struct amd_iommu *iommu)
124 {
125 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
126 }
127
128 /****************************************************************************
129 *
130 * Interrupt handling functions
131 *
132 ****************************************************************************/
133
134 static void iommu_print_event(void *__evt)
135 {
136 u32 *event = __evt;
137 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
138 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
139 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
140 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
141 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
142
143 printk(KERN_ERR "AMD IOMMU: Event logged [");
144
145 switch (type) {
146 case EVENT_TYPE_ILL_DEV:
147 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
148 "address=0x%016llx flags=0x%04x]\n",
149 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
150 address, flags);
151 break;
152 case EVENT_TYPE_IO_FAULT:
153 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
154 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
155 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
156 domid, address, flags);
157 break;
158 case EVENT_TYPE_DEV_TAB_ERR:
159 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
160 "address=0x%016llx flags=0x%04x]\n",
161 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
162 address, flags);
163 break;
164 case EVENT_TYPE_PAGE_TAB_ERR:
165 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
166 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
167 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
168 domid, address, flags);
169 break;
170 case EVENT_TYPE_ILL_CMD:
171 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
172 break;
173 case EVENT_TYPE_CMD_HARD_ERR:
174 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
175 "flags=0x%04x]\n", address, flags);
176 break;
177 case EVENT_TYPE_IOTLB_INV_TO:
178 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
179 "address=0x%016llx]\n",
180 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 address);
182 break;
183 case EVENT_TYPE_INV_DEV_REQ:
184 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
185 "address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 address, flags);
188 break;
189 default:
190 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
191 }
192 }
193
194 static void iommu_poll_events(struct amd_iommu *iommu)
195 {
196 u32 head, tail;
197 unsigned long flags;
198
199 spin_lock_irqsave(&iommu->lock, flags);
200
201 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
202 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
203
204 while (head != tail) {
205 iommu_print_event(iommu->evt_buf + head);
206 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
207 }
208
209 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
210
211 spin_unlock_irqrestore(&iommu->lock, flags);
212 }
213
214 irqreturn_t amd_iommu_int_handler(int irq, void *data)
215 {
216 struct amd_iommu *iommu;
217
218 list_for_each_entry(iommu, &amd_iommu_list, list)
219 iommu_poll_events(iommu);
220
221 return IRQ_HANDLED;
222 }
223
224 /****************************************************************************
225 *
226 * IOMMU command queuing functions
227 *
228 ****************************************************************************/
229
230 /*
231 * Writes the command to the IOMMUs command buffer and informs the
232 * hardware about the new command. Must be called with iommu->lock held.
233 */
234 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
235 {
236 u32 tail, head;
237 u8 *target;
238
239 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
240 target = iommu->cmd_buf + tail;
241 memcpy_toio(target, cmd, sizeof(*cmd));
242 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
243 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
244 if (tail == head)
245 return -ENOMEM;
246 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
247
248 return 0;
249 }
250
251 /*
252 * General queuing function for commands. Takes iommu->lock and calls
253 * __iommu_queue_command().
254 */
255 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
256 {
257 unsigned long flags;
258 int ret;
259
260 spin_lock_irqsave(&iommu->lock, flags);
261 ret = __iommu_queue_command(iommu, cmd);
262 if (!ret)
263 iommu->need_sync = true;
264 spin_unlock_irqrestore(&iommu->lock, flags);
265
266 return ret;
267 }
268
269 /*
270 * This function waits until an IOMMU has completed a completion
271 * wait command
272 */
273 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
274 {
275 int ready = 0;
276 unsigned status = 0;
277 unsigned long i = 0;
278
279 INC_STATS_COUNTER(compl_wait);
280
281 while (!ready && (i < EXIT_LOOP_COUNT)) {
282 ++i;
283 /* wait for the bit to become one */
284 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
285 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
286 }
287
288 /* set bit back to zero */
289 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
290 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
291
292 if (unlikely(i == EXIT_LOOP_COUNT))
293 panic("AMD IOMMU: Completion wait loop failed\n");
294 }
295
296 /*
297 * This function queues a completion wait command into the command
298 * buffer of an IOMMU
299 */
300 static int __iommu_completion_wait(struct amd_iommu *iommu)
301 {
302 struct iommu_cmd cmd;
303
304 memset(&cmd, 0, sizeof(cmd));
305 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
306 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
307
308 return __iommu_queue_command(iommu, &cmd);
309 }
310
311 /*
312 * This function is called whenever we need to ensure that the IOMMU has
313 * completed execution of all commands we sent. It sends a
314 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
315 * us about that by writing a value to a physical address we pass with
316 * the command.
317 */
318 static int iommu_completion_wait(struct amd_iommu *iommu)
319 {
320 int ret = 0;
321 unsigned long flags;
322
323 spin_lock_irqsave(&iommu->lock, flags);
324
325 if (!iommu->need_sync)
326 goto out;
327
328 ret = __iommu_completion_wait(iommu);
329
330 iommu->need_sync = false;
331
332 if (ret)
333 goto out;
334
335 __iommu_wait_for_completion(iommu);
336
337 out:
338 spin_unlock_irqrestore(&iommu->lock, flags);
339
340 return 0;
341 }
342
343 /*
344 * Command send function for invalidating a device table entry
345 */
346 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
347 {
348 struct iommu_cmd cmd;
349 int ret;
350
351 BUG_ON(iommu == NULL);
352
353 memset(&cmd, 0, sizeof(cmd));
354 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
355 cmd.data[0] = devid;
356
357 ret = iommu_queue_command(iommu, &cmd);
358
359 return ret;
360 }
361
362 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
363 u16 domid, int pde, int s)
364 {
365 memset(cmd, 0, sizeof(*cmd));
366 address &= PAGE_MASK;
367 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
368 cmd->data[1] |= domid;
369 cmd->data[2] = lower_32_bits(address);
370 cmd->data[3] = upper_32_bits(address);
371 if (s) /* size bit - we flush more than one 4kb page */
372 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
373 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
374 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
375 }
376
377 /*
378 * Generic command send function for invalidaing TLB entries
379 */
380 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
381 u64 address, u16 domid, int pde, int s)
382 {
383 struct iommu_cmd cmd;
384 int ret;
385
386 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
387
388 ret = iommu_queue_command(iommu, &cmd);
389
390 return ret;
391 }
392
393 /*
394 * TLB invalidation function which is called from the mapping functions.
395 * It invalidates a single PTE if the range to flush is within a single
396 * page. Otherwise it flushes the whole TLB of the IOMMU.
397 */
398 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
399 u64 address, size_t size)
400 {
401 int s = 0;
402 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
403
404 address &= PAGE_MASK;
405
406 if (pages > 1) {
407 /*
408 * If we have to flush more than one page, flush all
409 * TLB entries for this domain
410 */
411 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
412 s = 1;
413 }
414
415 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
416
417 return 0;
418 }
419
420 /* Flush the whole IO/TLB for a given protection domain */
421 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
422 {
423 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
424
425 INC_STATS_COUNTER(domain_flush_single);
426
427 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
428 }
429
430 /*
431 * This function is used to flush the IO/TLB for a given protection domain
432 * on every IOMMU in the system
433 */
434 static void iommu_flush_domain(u16 domid)
435 {
436 unsigned long flags;
437 struct amd_iommu *iommu;
438 struct iommu_cmd cmd;
439
440 INC_STATS_COUNTER(domain_flush_all);
441
442 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
443 domid, 1, 1);
444
445 list_for_each_entry(iommu, &amd_iommu_list, list) {
446 spin_lock_irqsave(&iommu->lock, flags);
447 __iommu_queue_command(iommu, &cmd);
448 __iommu_completion_wait(iommu);
449 __iommu_wait_for_completion(iommu);
450 spin_unlock_irqrestore(&iommu->lock, flags);
451 }
452 }
453
454 /****************************************************************************
455 *
456 * The functions below are used the create the page table mappings for
457 * unity mapped regions.
458 *
459 ****************************************************************************/
460
461 /*
462 * Generic mapping functions. It maps a physical address into a DMA
463 * address space. It allocates the page table pages if necessary.
464 * In the future it can be extended to a generic mapping function
465 * supporting all features of AMD IOMMU page tables like level skipping
466 * and full 64 bit address spaces.
467 */
468 static int iommu_map_page(struct protection_domain *dom,
469 unsigned long bus_addr,
470 unsigned long phys_addr,
471 int prot)
472 {
473 u64 __pte, *pte;
474
475 bus_addr = PAGE_ALIGN(bus_addr);
476 phys_addr = PAGE_ALIGN(phys_addr);
477
478 /* only support 512GB address spaces for now */
479 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
480 return -EINVAL;
481
482 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
483
484 if (IOMMU_PTE_PRESENT(*pte))
485 return -EBUSY;
486
487 __pte = phys_addr | IOMMU_PTE_P;
488 if (prot & IOMMU_PROT_IR)
489 __pte |= IOMMU_PTE_IR;
490 if (prot & IOMMU_PROT_IW)
491 __pte |= IOMMU_PTE_IW;
492
493 *pte = __pte;
494
495 return 0;
496 }
497
498 static void iommu_unmap_page(struct protection_domain *dom,
499 unsigned long bus_addr)
500 {
501 u64 *pte;
502
503 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
504
505 if (!IOMMU_PTE_PRESENT(*pte))
506 return;
507
508 pte = IOMMU_PTE_PAGE(*pte);
509 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
510
511 if (!IOMMU_PTE_PRESENT(*pte))
512 return;
513
514 pte = IOMMU_PTE_PAGE(*pte);
515 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
516
517 *pte = 0;
518 }
519
520 /*
521 * This function checks if a specific unity mapping entry is needed for
522 * this specific IOMMU.
523 */
524 static int iommu_for_unity_map(struct amd_iommu *iommu,
525 struct unity_map_entry *entry)
526 {
527 u16 bdf, i;
528
529 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
530 bdf = amd_iommu_alias_table[i];
531 if (amd_iommu_rlookup_table[bdf] == iommu)
532 return 1;
533 }
534
535 return 0;
536 }
537
538 /*
539 * Init the unity mappings for a specific IOMMU in the system
540 *
541 * Basically iterates over all unity mapping entries and applies them to
542 * the default domain DMA of that IOMMU if necessary.
543 */
544 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
545 {
546 struct unity_map_entry *entry;
547 int ret;
548
549 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
550 if (!iommu_for_unity_map(iommu, entry))
551 continue;
552 ret = dma_ops_unity_map(iommu->default_dom, entry);
553 if (ret)
554 return ret;
555 }
556
557 return 0;
558 }
559
560 /*
561 * This function actually applies the mapping to the page table of the
562 * dma_ops domain.
563 */
564 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
565 struct unity_map_entry *e)
566 {
567 u64 addr;
568 int ret;
569
570 for (addr = e->address_start; addr < e->address_end;
571 addr += PAGE_SIZE) {
572 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
573 if (ret)
574 return ret;
575 /*
576 * if unity mapping is in aperture range mark the page
577 * as allocated in the aperture
578 */
579 if (addr < dma_dom->aperture_size)
580 __set_bit(addr >> PAGE_SHIFT,
581 dma_dom->aperture.bitmap);
582 }
583
584 return 0;
585 }
586
587 /*
588 * Inits the unity mappings required for a specific device
589 */
590 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
591 u16 devid)
592 {
593 struct unity_map_entry *e;
594 int ret;
595
596 list_for_each_entry(e, &amd_iommu_unity_map, list) {
597 if (!(devid >= e->devid_start && devid <= e->devid_end))
598 continue;
599 ret = dma_ops_unity_map(dma_dom, e);
600 if (ret)
601 return ret;
602 }
603
604 return 0;
605 }
606
607 /****************************************************************************
608 *
609 * The next functions belong to the address allocator for the dma_ops
610 * interface functions. They work like the allocators in the other IOMMU
611 * drivers. Its basically a bitmap which marks the allocated pages in
612 * the aperture. Maybe it could be enhanced in the future to a more
613 * efficient allocator.
614 *
615 ****************************************************************************/
616
617 /*
618 * The address allocator core function.
619 *
620 * called with domain->lock held
621 */
622 static unsigned long dma_ops_alloc_addresses(struct device *dev,
623 struct dma_ops_domain *dom,
624 unsigned int pages,
625 unsigned long align_mask,
626 u64 dma_mask)
627 {
628 unsigned long limit;
629 unsigned long address;
630 unsigned long boundary_size;
631
632 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
633 PAGE_SIZE) >> PAGE_SHIFT;
634 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
635 dma_mask >> PAGE_SHIFT);
636
637 if (dom->next_bit >= limit) {
638 dom->next_bit = 0;
639 dom->need_flush = true;
640 }
641
642 address = iommu_area_alloc(dom->aperture.bitmap, limit, dom->next_bit,
643 pages, 0 , boundary_size, align_mask);
644 if (address == -1) {
645 address = iommu_area_alloc(dom->aperture.bitmap, limit, 0,
646 pages, 0, boundary_size,
647 align_mask);
648 dom->need_flush = true;
649 }
650
651 if (likely(address != -1)) {
652 dom->next_bit = address + pages;
653 address <<= PAGE_SHIFT;
654 } else
655 address = bad_dma_address;
656
657 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
658
659 return address;
660 }
661
662 /*
663 * The address free function.
664 *
665 * called with domain->lock held
666 */
667 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
668 unsigned long address,
669 unsigned int pages)
670 {
671 address >>= PAGE_SHIFT;
672 iommu_area_free(dom->aperture.bitmap, address, pages);
673
674 if (address >= dom->next_bit)
675 dom->need_flush = true;
676 }
677
678 /****************************************************************************
679 *
680 * The next functions belong to the domain allocation. A domain is
681 * allocated for every IOMMU as the default domain. If device isolation
682 * is enabled, every device get its own domain. The most important thing
683 * about domains is the page table mapping the DMA address space they
684 * contain.
685 *
686 ****************************************************************************/
687
688 static u16 domain_id_alloc(void)
689 {
690 unsigned long flags;
691 int id;
692
693 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
694 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
695 BUG_ON(id == 0);
696 if (id > 0 && id < MAX_DOMAIN_ID)
697 __set_bit(id, amd_iommu_pd_alloc_bitmap);
698 else
699 id = 0;
700 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
701
702 return id;
703 }
704
705 static void domain_id_free(int id)
706 {
707 unsigned long flags;
708
709 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
710 if (id > 0 && id < MAX_DOMAIN_ID)
711 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
712 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
713 }
714
715 /*
716 * Used to reserve address ranges in the aperture (e.g. for exclusion
717 * ranges.
718 */
719 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
720 unsigned long start_page,
721 unsigned int pages)
722 {
723 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
724
725 if (start_page + pages > last_page)
726 pages = last_page - start_page;
727
728 iommu_area_reserve(dom->aperture.bitmap, start_page, pages);
729 }
730
731 static void free_pagetable(struct protection_domain *domain)
732 {
733 int i, j;
734 u64 *p1, *p2, *p3;
735
736 p1 = domain->pt_root;
737
738 if (!p1)
739 return;
740
741 for (i = 0; i < 512; ++i) {
742 if (!IOMMU_PTE_PRESENT(p1[i]))
743 continue;
744
745 p2 = IOMMU_PTE_PAGE(p1[i]);
746 for (j = 0; j < 512; ++j) {
747 if (!IOMMU_PTE_PRESENT(p2[j]))
748 continue;
749 p3 = IOMMU_PTE_PAGE(p2[j]);
750 free_page((unsigned long)p3);
751 }
752
753 free_page((unsigned long)p2);
754 }
755
756 free_page((unsigned long)p1);
757
758 domain->pt_root = NULL;
759 }
760
761 /*
762 * Free a domain, only used if something went wrong in the
763 * allocation path and we need to free an already allocated page table
764 */
765 static void dma_ops_domain_free(struct dma_ops_domain *dom)
766 {
767 if (!dom)
768 return;
769
770 free_pagetable(&dom->domain);
771
772 free_page((unsigned long)dom->aperture.bitmap);
773
774 kfree(dom);
775 }
776
777 /*
778 * Allocates a new protection domain usable for the dma_ops functions.
779 * It also intializes the page table and the address allocator data
780 * structures required for the dma_ops interface
781 */
782 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
783 unsigned order)
784 {
785 struct dma_ops_domain *dma_dom;
786 unsigned i, num_pte_pages;
787 u64 *l2_pde;
788 u64 address;
789
790 /*
791 * Currently the DMA aperture must be between 32 MB and 1GB in size
792 */
793 if ((order < 25) || (order > 30))
794 return NULL;
795
796 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
797 if (!dma_dom)
798 return NULL;
799
800 spin_lock_init(&dma_dom->domain.lock);
801
802 dma_dom->domain.id = domain_id_alloc();
803 if (dma_dom->domain.id == 0)
804 goto free_dma_dom;
805 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
806 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
807 dma_dom->domain.flags = PD_DMA_OPS_MASK;
808 dma_dom->domain.priv = dma_dom;
809 if (!dma_dom->domain.pt_root)
810 goto free_dma_dom;
811 dma_dom->aperture_size = APERTURE_RANGE_SIZE;
812 dma_dom->aperture.bitmap = (void *)get_zeroed_page(GFP_KERNEL);
813 if (!dma_dom->aperture.bitmap)
814 goto free_dma_dom;
815 /*
816 * mark the first page as allocated so we never return 0 as
817 * a valid dma-address. So we can use 0 as error value
818 */
819 dma_dom->aperture.bitmap[0] = 1;
820 dma_dom->next_bit = 0;
821
822 dma_dom->need_flush = false;
823 dma_dom->target_dev = 0xffff;
824
825 /* Intialize the exclusion range if necessary */
826 if (iommu->exclusion_start &&
827 iommu->exclusion_start < dma_dom->aperture_size) {
828 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
829 int pages = iommu_num_pages(iommu->exclusion_start,
830 iommu->exclusion_length,
831 PAGE_SIZE);
832 dma_ops_reserve_addresses(dma_dom, startpage, pages);
833 }
834
835 /*
836 * At the last step, build the page tables so we don't need to
837 * allocate page table pages in the dma_ops mapping/unmapping
838 * path for the first 128MB of dma address space.
839 */
840 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
841
842 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
843 if (l2_pde == NULL)
844 goto free_dma_dom;
845
846 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
847
848 for (i = 0; i < num_pte_pages; ++i) {
849 u64 **pte_page = &dma_dom->aperture.pte_pages[i];
850 *pte_page = (u64 *)get_zeroed_page(GFP_KERNEL);
851 if (!*pte_page)
852 goto free_dma_dom;
853 address = virt_to_phys(*pte_page);
854 l2_pde[i] = IOMMU_L1_PDE(address);
855 }
856
857 return dma_dom;
858
859 free_dma_dom:
860 dma_ops_domain_free(dma_dom);
861
862 return NULL;
863 }
864
865 /*
866 * little helper function to check whether a given protection domain is a
867 * dma_ops domain
868 */
869 static bool dma_ops_domain(struct protection_domain *domain)
870 {
871 return domain->flags & PD_DMA_OPS_MASK;
872 }
873
874 /*
875 * Find out the protection domain structure for a given PCI device. This
876 * will give us the pointer to the page table root for example.
877 */
878 static struct protection_domain *domain_for_device(u16 devid)
879 {
880 struct protection_domain *dom;
881 unsigned long flags;
882
883 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
884 dom = amd_iommu_pd_table[devid];
885 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
886
887 return dom;
888 }
889
890 /*
891 * If a device is not yet associated with a domain, this function does
892 * assigns it visible for the hardware
893 */
894 static void attach_device(struct amd_iommu *iommu,
895 struct protection_domain *domain,
896 u16 devid)
897 {
898 unsigned long flags;
899 u64 pte_root = virt_to_phys(domain->pt_root);
900
901 domain->dev_cnt += 1;
902
903 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
904 << DEV_ENTRY_MODE_SHIFT;
905 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
906
907 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
908 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
909 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
910 amd_iommu_dev_table[devid].data[2] = domain->id;
911
912 amd_iommu_pd_table[devid] = domain;
913 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
914
915 iommu_queue_inv_dev_entry(iommu, devid);
916 }
917
918 /*
919 * Removes a device from a protection domain (unlocked)
920 */
921 static void __detach_device(struct protection_domain *domain, u16 devid)
922 {
923
924 /* lock domain */
925 spin_lock(&domain->lock);
926
927 /* remove domain from the lookup table */
928 amd_iommu_pd_table[devid] = NULL;
929
930 /* remove entry from the device table seen by the hardware */
931 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
932 amd_iommu_dev_table[devid].data[1] = 0;
933 amd_iommu_dev_table[devid].data[2] = 0;
934
935 /* decrease reference counter */
936 domain->dev_cnt -= 1;
937
938 /* ready */
939 spin_unlock(&domain->lock);
940 }
941
942 /*
943 * Removes a device from a protection domain (with devtable_lock held)
944 */
945 static void detach_device(struct protection_domain *domain, u16 devid)
946 {
947 unsigned long flags;
948
949 /* lock device table */
950 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
951 __detach_device(domain, devid);
952 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
953 }
954
955 static int device_change_notifier(struct notifier_block *nb,
956 unsigned long action, void *data)
957 {
958 struct device *dev = data;
959 struct pci_dev *pdev = to_pci_dev(dev);
960 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
961 struct protection_domain *domain;
962 struct dma_ops_domain *dma_domain;
963 struct amd_iommu *iommu;
964 int order = amd_iommu_aperture_order;
965 unsigned long flags;
966
967 if (devid > amd_iommu_last_bdf)
968 goto out;
969
970 devid = amd_iommu_alias_table[devid];
971
972 iommu = amd_iommu_rlookup_table[devid];
973 if (iommu == NULL)
974 goto out;
975
976 domain = domain_for_device(devid);
977
978 if (domain && !dma_ops_domain(domain))
979 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
980 "to a non-dma-ops domain\n", dev_name(dev));
981
982 switch (action) {
983 case BUS_NOTIFY_BOUND_DRIVER:
984 if (domain)
985 goto out;
986 dma_domain = find_protection_domain(devid);
987 if (!dma_domain)
988 dma_domain = iommu->default_dom;
989 attach_device(iommu, &dma_domain->domain, devid);
990 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
991 "device %s\n", dma_domain->domain.id, dev_name(dev));
992 break;
993 case BUS_NOTIFY_UNBIND_DRIVER:
994 if (!domain)
995 goto out;
996 detach_device(domain, devid);
997 break;
998 case BUS_NOTIFY_ADD_DEVICE:
999 /* allocate a protection domain if a device is added */
1000 dma_domain = find_protection_domain(devid);
1001 if (dma_domain)
1002 goto out;
1003 dma_domain = dma_ops_domain_alloc(iommu, order);
1004 if (!dma_domain)
1005 goto out;
1006 dma_domain->target_dev = devid;
1007
1008 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1009 list_add_tail(&dma_domain->list, &iommu_pd_list);
1010 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1011
1012 break;
1013 default:
1014 goto out;
1015 }
1016
1017 iommu_queue_inv_dev_entry(iommu, devid);
1018 iommu_completion_wait(iommu);
1019
1020 out:
1021 return 0;
1022 }
1023
1024 struct notifier_block device_nb = {
1025 .notifier_call = device_change_notifier,
1026 };
1027
1028 /*****************************************************************************
1029 *
1030 * The next functions belong to the dma_ops mapping/unmapping code.
1031 *
1032 *****************************************************************************/
1033
1034 /*
1035 * This function checks if the driver got a valid device from the caller to
1036 * avoid dereferencing invalid pointers.
1037 */
1038 static bool check_device(struct device *dev)
1039 {
1040 if (!dev || !dev->dma_mask)
1041 return false;
1042
1043 return true;
1044 }
1045
1046 /*
1047 * In this function the list of preallocated protection domains is traversed to
1048 * find the domain for a specific device
1049 */
1050 static struct dma_ops_domain *find_protection_domain(u16 devid)
1051 {
1052 struct dma_ops_domain *entry, *ret = NULL;
1053 unsigned long flags;
1054
1055 if (list_empty(&iommu_pd_list))
1056 return NULL;
1057
1058 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1059
1060 list_for_each_entry(entry, &iommu_pd_list, list) {
1061 if (entry->target_dev == devid) {
1062 ret = entry;
1063 break;
1064 }
1065 }
1066
1067 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1068
1069 return ret;
1070 }
1071
1072 /*
1073 * In the dma_ops path we only have the struct device. This function
1074 * finds the corresponding IOMMU, the protection domain and the
1075 * requestor id for a given device.
1076 * If the device is not yet associated with a domain this is also done
1077 * in this function.
1078 */
1079 static int get_device_resources(struct device *dev,
1080 struct amd_iommu **iommu,
1081 struct protection_domain **domain,
1082 u16 *bdf)
1083 {
1084 struct dma_ops_domain *dma_dom;
1085 struct pci_dev *pcidev;
1086 u16 _bdf;
1087
1088 *iommu = NULL;
1089 *domain = NULL;
1090 *bdf = 0xffff;
1091
1092 if (dev->bus != &pci_bus_type)
1093 return 0;
1094
1095 pcidev = to_pci_dev(dev);
1096 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1097
1098 /* device not translated by any IOMMU in the system? */
1099 if (_bdf > amd_iommu_last_bdf)
1100 return 0;
1101
1102 *bdf = amd_iommu_alias_table[_bdf];
1103
1104 *iommu = amd_iommu_rlookup_table[*bdf];
1105 if (*iommu == NULL)
1106 return 0;
1107 *domain = domain_for_device(*bdf);
1108 if (*domain == NULL) {
1109 dma_dom = find_protection_domain(*bdf);
1110 if (!dma_dom)
1111 dma_dom = (*iommu)->default_dom;
1112 *domain = &dma_dom->domain;
1113 attach_device(*iommu, *domain, *bdf);
1114 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1115 "device %s\n", (*domain)->id, dev_name(dev));
1116 }
1117
1118 if (domain_for_device(_bdf) == NULL)
1119 attach_device(*iommu, *domain, _bdf);
1120
1121 return 1;
1122 }
1123
1124 /*
1125 * If the pte_page is not yet allocated this function is called
1126 */
1127 static u64* alloc_pte(struct protection_domain *dom,
1128 unsigned long address, u64 **pte_page, gfp_t gfp)
1129 {
1130 u64 *pte, *page;
1131
1132 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1133
1134 if (!IOMMU_PTE_PRESENT(*pte)) {
1135 page = (u64 *)get_zeroed_page(gfp);
1136 if (!page)
1137 return NULL;
1138 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1139 }
1140
1141 pte = IOMMU_PTE_PAGE(*pte);
1142 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1143
1144 if (!IOMMU_PTE_PRESENT(*pte)) {
1145 page = (u64 *)get_zeroed_page(gfp);
1146 if (!page)
1147 return NULL;
1148 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1149 }
1150
1151 pte = IOMMU_PTE_PAGE(*pte);
1152
1153 if (pte_page)
1154 *pte_page = pte;
1155
1156 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1157
1158 return pte;
1159 }
1160
1161 /*
1162 * This function fetches the PTE for a given address in the aperture
1163 */
1164 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1165 unsigned long address)
1166 {
1167 struct aperture_range *aperture = &dom->aperture;
1168 u64 *pte, *pte_page;
1169
1170 pte = aperture->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1171 if (!pte) {
1172 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1173 aperture->pte_pages[IOMMU_PTE_L1_INDEX(address)] = pte_page;
1174 }
1175
1176 return pte;
1177 }
1178
1179 /*
1180 * This is the generic map function. It maps one 4kb page at paddr to
1181 * the given address in the DMA address space for the domain.
1182 */
1183 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1184 struct dma_ops_domain *dom,
1185 unsigned long address,
1186 phys_addr_t paddr,
1187 int direction)
1188 {
1189 u64 *pte, __pte;
1190
1191 WARN_ON(address > dom->aperture_size);
1192
1193 paddr &= PAGE_MASK;
1194
1195 pte = dma_ops_get_pte(dom, address);
1196
1197 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1198
1199 if (direction == DMA_TO_DEVICE)
1200 __pte |= IOMMU_PTE_IR;
1201 else if (direction == DMA_FROM_DEVICE)
1202 __pte |= IOMMU_PTE_IW;
1203 else if (direction == DMA_BIDIRECTIONAL)
1204 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1205
1206 WARN_ON(*pte);
1207
1208 *pte = __pte;
1209
1210 return (dma_addr_t)address;
1211 }
1212
1213 /*
1214 * The generic unmapping function for on page in the DMA address space.
1215 */
1216 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1217 struct dma_ops_domain *dom,
1218 unsigned long address)
1219 {
1220 u64 *pte;
1221
1222 if (address >= dom->aperture_size)
1223 return;
1224
1225 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1226
1227 pte = dom->aperture.pte_pages[IOMMU_PTE_L1_INDEX(address)];
1228 pte += IOMMU_PTE_L0_INDEX(address);
1229
1230 WARN_ON(!*pte);
1231
1232 *pte = 0ULL;
1233 }
1234
1235 /*
1236 * This function contains common code for mapping of a physically
1237 * contiguous memory region into DMA address space. It is used by all
1238 * mapping functions provided with this IOMMU driver.
1239 * Must be called with the domain lock held.
1240 */
1241 static dma_addr_t __map_single(struct device *dev,
1242 struct amd_iommu *iommu,
1243 struct dma_ops_domain *dma_dom,
1244 phys_addr_t paddr,
1245 size_t size,
1246 int dir,
1247 bool align,
1248 u64 dma_mask)
1249 {
1250 dma_addr_t offset = paddr & ~PAGE_MASK;
1251 dma_addr_t address, start;
1252 unsigned int pages;
1253 unsigned long align_mask = 0;
1254 int i;
1255
1256 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1257 paddr &= PAGE_MASK;
1258
1259 INC_STATS_COUNTER(total_map_requests);
1260
1261 if (pages > 1)
1262 INC_STATS_COUNTER(cross_page);
1263
1264 if (align)
1265 align_mask = (1UL << get_order(size)) - 1;
1266
1267 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1268 dma_mask);
1269 if (unlikely(address == bad_dma_address))
1270 goto out;
1271
1272 start = address;
1273 for (i = 0; i < pages; ++i) {
1274 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1275 paddr += PAGE_SIZE;
1276 start += PAGE_SIZE;
1277 }
1278 address += offset;
1279
1280 ADD_STATS_COUNTER(alloced_io_mem, size);
1281
1282 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1283 iommu_flush_tlb(iommu, dma_dom->domain.id);
1284 dma_dom->need_flush = false;
1285 } else if (unlikely(iommu_has_npcache(iommu)))
1286 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1287
1288 out:
1289 return address;
1290 }
1291
1292 /*
1293 * Does the reverse of the __map_single function. Must be called with
1294 * the domain lock held too
1295 */
1296 static void __unmap_single(struct amd_iommu *iommu,
1297 struct dma_ops_domain *dma_dom,
1298 dma_addr_t dma_addr,
1299 size_t size,
1300 int dir)
1301 {
1302 dma_addr_t i, start;
1303 unsigned int pages;
1304
1305 if ((dma_addr == bad_dma_address) ||
1306 (dma_addr + size > dma_dom->aperture_size))
1307 return;
1308
1309 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1310 dma_addr &= PAGE_MASK;
1311 start = dma_addr;
1312
1313 for (i = 0; i < pages; ++i) {
1314 dma_ops_domain_unmap(iommu, dma_dom, start);
1315 start += PAGE_SIZE;
1316 }
1317
1318 SUB_STATS_COUNTER(alloced_io_mem, size);
1319
1320 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1321
1322 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1323 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1324 dma_dom->need_flush = false;
1325 }
1326 }
1327
1328 /*
1329 * The exported map_single function for dma_ops.
1330 */
1331 static dma_addr_t map_page(struct device *dev, struct page *page,
1332 unsigned long offset, size_t size,
1333 enum dma_data_direction dir,
1334 struct dma_attrs *attrs)
1335 {
1336 unsigned long flags;
1337 struct amd_iommu *iommu;
1338 struct protection_domain *domain;
1339 u16 devid;
1340 dma_addr_t addr;
1341 u64 dma_mask;
1342 phys_addr_t paddr = page_to_phys(page) + offset;
1343
1344 INC_STATS_COUNTER(cnt_map_single);
1345
1346 if (!check_device(dev))
1347 return bad_dma_address;
1348
1349 dma_mask = *dev->dma_mask;
1350
1351 get_device_resources(dev, &iommu, &domain, &devid);
1352
1353 if (iommu == NULL || domain == NULL)
1354 /* device not handled by any AMD IOMMU */
1355 return (dma_addr_t)paddr;
1356
1357 if (!dma_ops_domain(domain))
1358 return bad_dma_address;
1359
1360 spin_lock_irqsave(&domain->lock, flags);
1361 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1362 dma_mask);
1363 if (addr == bad_dma_address)
1364 goto out;
1365
1366 iommu_completion_wait(iommu);
1367
1368 out:
1369 spin_unlock_irqrestore(&domain->lock, flags);
1370
1371 return addr;
1372 }
1373
1374 /*
1375 * The exported unmap_single function for dma_ops.
1376 */
1377 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1378 enum dma_data_direction dir, struct dma_attrs *attrs)
1379 {
1380 unsigned long flags;
1381 struct amd_iommu *iommu;
1382 struct protection_domain *domain;
1383 u16 devid;
1384
1385 INC_STATS_COUNTER(cnt_unmap_single);
1386
1387 if (!check_device(dev) ||
1388 !get_device_resources(dev, &iommu, &domain, &devid))
1389 /* device not handled by any AMD IOMMU */
1390 return;
1391
1392 if (!dma_ops_domain(domain))
1393 return;
1394
1395 spin_lock_irqsave(&domain->lock, flags);
1396
1397 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1398
1399 iommu_completion_wait(iommu);
1400
1401 spin_unlock_irqrestore(&domain->lock, flags);
1402 }
1403
1404 /*
1405 * This is a special map_sg function which is used if we should map a
1406 * device which is not handled by an AMD IOMMU in the system.
1407 */
1408 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1409 int nelems, int dir)
1410 {
1411 struct scatterlist *s;
1412 int i;
1413
1414 for_each_sg(sglist, s, nelems, i) {
1415 s->dma_address = (dma_addr_t)sg_phys(s);
1416 s->dma_length = s->length;
1417 }
1418
1419 return nelems;
1420 }
1421
1422 /*
1423 * The exported map_sg function for dma_ops (handles scatter-gather
1424 * lists).
1425 */
1426 static int map_sg(struct device *dev, struct scatterlist *sglist,
1427 int nelems, enum dma_data_direction dir,
1428 struct dma_attrs *attrs)
1429 {
1430 unsigned long flags;
1431 struct amd_iommu *iommu;
1432 struct protection_domain *domain;
1433 u16 devid;
1434 int i;
1435 struct scatterlist *s;
1436 phys_addr_t paddr;
1437 int mapped_elems = 0;
1438 u64 dma_mask;
1439
1440 INC_STATS_COUNTER(cnt_map_sg);
1441
1442 if (!check_device(dev))
1443 return 0;
1444
1445 dma_mask = *dev->dma_mask;
1446
1447 get_device_resources(dev, &iommu, &domain, &devid);
1448
1449 if (!iommu || !domain)
1450 return map_sg_no_iommu(dev, sglist, nelems, dir);
1451
1452 if (!dma_ops_domain(domain))
1453 return 0;
1454
1455 spin_lock_irqsave(&domain->lock, flags);
1456
1457 for_each_sg(sglist, s, nelems, i) {
1458 paddr = sg_phys(s);
1459
1460 s->dma_address = __map_single(dev, iommu, domain->priv,
1461 paddr, s->length, dir, false,
1462 dma_mask);
1463
1464 if (s->dma_address) {
1465 s->dma_length = s->length;
1466 mapped_elems++;
1467 } else
1468 goto unmap;
1469 }
1470
1471 iommu_completion_wait(iommu);
1472
1473 out:
1474 spin_unlock_irqrestore(&domain->lock, flags);
1475
1476 return mapped_elems;
1477 unmap:
1478 for_each_sg(sglist, s, mapped_elems, i) {
1479 if (s->dma_address)
1480 __unmap_single(iommu, domain->priv, s->dma_address,
1481 s->dma_length, dir);
1482 s->dma_address = s->dma_length = 0;
1483 }
1484
1485 mapped_elems = 0;
1486
1487 goto out;
1488 }
1489
1490 /*
1491 * The exported map_sg function for dma_ops (handles scatter-gather
1492 * lists).
1493 */
1494 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1495 int nelems, enum dma_data_direction dir,
1496 struct dma_attrs *attrs)
1497 {
1498 unsigned long flags;
1499 struct amd_iommu *iommu;
1500 struct protection_domain *domain;
1501 struct scatterlist *s;
1502 u16 devid;
1503 int i;
1504
1505 INC_STATS_COUNTER(cnt_unmap_sg);
1506
1507 if (!check_device(dev) ||
1508 !get_device_resources(dev, &iommu, &domain, &devid))
1509 return;
1510
1511 if (!dma_ops_domain(domain))
1512 return;
1513
1514 spin_lock_irqsave(&domain->lock, flags);
1515
1516 for_each_sg(sglist, s, nelems, i) {
1517 __unmap_single(iommu, domain->priv, s->dma_address,
1518 s->dma_length, dir);
1519 s->dma_address = s->dma_length = 0;
1520 }
1521
1522 iommu_completion_wait(iommu);
1523
1524 spin_unlock_irqrestore(&domain->lock, flags);
1525 }
1526
1527 /*
1528 * The exported alloc_coherent function for dma_ops.
1529 */
1530 static void *alloc_coherent(struct device *dev, size_t size,
1531 dma_addr_t *dma_addr, gfp_t flag)
1532 {
1533 unsigned long flags;
1534 void *virt_addr;
1535 struct amd_iommu *iommu;
1536 struct protection_domain *domain;
1537 u16 devid;
1538 phys_addr_t paddr;
1539 u64 dma_mask = dev->coherent_dma_mask;
1540
1541 INC_STATS_COUNTER(cnt_alloc_coherent);
1542
1543 if (!check_device(dev))
1544 return NULL;
1545
1546 if (!get_device_resources(dev, &iommu, &domain, &devid))
1547 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1548
1549 flag |= __GFP_ZERO;
1550 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1551 if (!virt_addr)
1552 return 0;
1553
1554 paddr = virt_to_phys(virt_addr);
1555
1556 if (!iommu || !domain) {
1557 *dma_addr = (dma_addr_t)paddr;
1558 return virt_addr;
1559 }
1560
1561 if (!dma_ops_domain(domain))
1562 goto out_free;
1563
1564 if (!dma_mask)
1565 dma_mask = *dev->dma_mask;
1566
1567 spin_lock_irqsave(&domain->lock, flags);
1568
1569 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1570 size, DMA_BIDIRECTIONAL, true, dma_mask);
1571
1572 if (*dma_addr == bad_dma_address)
1573 goto out_free;
1574
1575 iommu_completion_wait(iommu);
1576
1577 spin_unlock_irqrestore(&domain->lock, flags);
1578
1579 return virt_addr;
1580
1581 out_free:
1582
1583 free_pages((unsigned long)virt_addr, get_order(size));
1584
1585 return NULL;
1586 }
1587
1588 /*
1589 * The exported free_coherent function for dma_ops.
1590 */
1591 static void free_coherent(struct device *dev, size_t size,
1592 void *virt_addr, dma_addr_t dma_addr)
1593 {
1594 unsigned long flags;
1595 struct amd_iommu *iommu;
1596 struct protection_domain *domain;
1597 u16 devid;
1598
1599 INC_STATS_COUNTER(cnt_free_coherent);
1600
1601 if (!check_device(dev))
1602 return;
1603
1604 get_device_resources(dev, &iommu, &domain, &devid);
1605
1606 if (!iommu || !domain)
1607 goto free_mem;
1608
1609 if (!dma_ops_domain(domain))
1610 goto free_mem;
1611
1612 spin_lock_irqsave(&domain->lock, flags);
1613
1614 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1615
1616 iommu_completion_wait(iommu);
1617
1618 spin_unlock_irqrestore(&domain->lock, flags);
1619
1620 free_mem:
1621 free_pages((unsigned long)virt_addr, get_order(size));
1622 }
1623
1624 /*
1625 * This function is called by the DMA layer to find out if we can handle a
1626 * particular device. It is part of the dma_ops.
1627 */
1628 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1629 {
1630 u16 bdf;
1631 struct pci_dev *pcidev;
1632
1633 /* No device or no PCI device */
1634 if (!dev || dev->bus != &pci_bus_type)
1635 return 0;
1636
1637 pcidev = to_pci_dev(dev);
1638
1639 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1640
1641 /* Out of our scope? */
1642 if (bdf > amd_iommu_last_bdf)
1643 return 0;
1644
1645 return 1;
1646 }
1647
1648 /*
1649 * The function for pre-allocating protection domains.
1650 *
1651 * If the driver core informs the DMA layer if a driver grabs a device
1652 * we don't need to preallocate the protection domains anymore.
1653 * For now we have to.
1654 */
1655 static void prealloc_protection_domains(void)
1656 {
1657 struct pci_dev *dev = NULL;
1658 struct dma_ops_domain *dma_dom;
1659 struct amd_iommu *iommu;
1660 int order = amd_iommu_aperture_order;
1661 u16 devid;
1662
1663 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1664 devid = calc_devid(dev->bus->number, dev->devfn);
1665 if (devid > amd_iommu_last_bdf)
1666 continue;
1667 devid = amd_iommu_alias_table[devid];
1668 if (domain_for_device(devid))
1669 continue;
1670 iommu = amd_iommu_rlookup_table[devid];
1671 if (!iommu)
1672 continue;
1673 dma_dom = dma_ops_domain_alloc(iommu, order);
1674 if (!dma_dom)
1675 continue;
1676 init_unity_mappings_for_device(dma_dom, devid);
1677 dma_dom->target_dev = devid;
1678
1679 list_add_tail(&dma_dom->list, &iommu_pd_list);
1680 }
1681 }
1682
1683 static struct dma_map_ops amd_iommu_dma_ops = {
1684 .alloc_coherent = alloc_coherent,
1685 .free_coherent = free_coherent,
1686 .map_page = map_page,
1687 .unmap_page = unmap_page,
1688 .map_sg = map_sg,
1689 .unmap_sg = unmap_sg,
1690 .dma_supported = amd_iommu_dma_supported,
1691 };
1692
1693 /*
1694 * The function which clues the AMD IOMMU driver into dma_ops.
1695 */
1696 int __init amd_iommu_init_dma_ops(void)
1697 {
1698 struct amd_iommu *iommu;
1699 int order = amd_iommu_aperture_order;
1700 int ret;
1701
1702 /*
1703 * first allocate a default protection domain for every IOMMU we
1704 * found in the system. Devices not assigned to any other
1705 * protection domain will be assigned to the default one.
1706 */
1707 list_for_each_entry(iommu, &amd_iommu_list, list) {
1708 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1709 if (iommu->default_dom == NULL)
1710 return -ENOMEM;
1711 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1712 ret = iommu_init_unity_mappings(iommu);
1713 if (ret)
1714 goto free_domains;
1715 }
1716
1717 /*
1718 * If device isolation is enabled, pre-allocate the protection
1719 * domains for each device.
1720 */
1721 if (amd_iommu_isolate)
1722 prealloc_protection_domains();
1723
1724 iommu_detected = 1;
1725 force_iommu = 1;
1726 bad_dma_address = 0;
1727 #ifdef CONFIG_GART_IOMMU
1728 gart_iommu_aperture_disabled = 1;
1729 gart_iommu_aperture = 0;
1730 #endif
1731
1732 /* Make the driver finally visible to the drivers */
1733 dma_ops = &amd_iommu_dma_ops;
1734
1735 register_iommu(&amd_iommu_ops);
1736
1737 bus_register_notifier(&pci_bus_type, &device_nb);
1738
1739 amd_iommu_stats_init();
1740
1741 return 0;
1742
1743 free_domains:
1744
1745 list_for_each_entry(iommu, &amd_iommu_list, list) {
1746 if (iommu->default_dom)
1747 dma_ops_domain_free(iommu->default_dom);
1748 }
1749
1750 return ret;
1751 }
1752
1753 /*****************************************************************************
1754 *
1755 * The following functions belong to the exported interface of AMD IOMMU
1756 *
1757 * This interface allows access to lower level functions of the IOMMU
1758 * like protection domain handling and assignement of devices to domains
1759 * which is not possible with the dma_ops interface.
1760 *
1761 *****************************************************************************/
1762
1763 static void cleanup_domain(struct protection_domain *domain)
1764 {
1765 unsigned long flags;
1766 u16 devid;
1767
1768 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1769
1770 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1771 if (amd_iommu_pd_table[devid] == domain)
1772 __detach_device(domain, devid);
1773
1774 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1775 }
1776
1777 static int amd_iommu_domain_init(struct iommu_domain *dom)
1778 {
1779 struct protection_domain *domain;
1780
1781 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1782 if (!domain)
1783 return -ENOMEM;
1784
1785 spin_lock_init(&domain->lock);
1786 domain->mode = PAGE_MODE_3_LEVEL;
1787 domain->id = domain_id_alloc();
1788 if (!domain->id)
1789 goto out_free;
1790 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1791 if (!domain->pt_root)
1792 goto out_free;
1793
1794 dom->priv = domain;
1795
1796 return 0;
1797
1798 out_free:
1799 kfree(domain);
1800
1801 return -ENOMEM;
1802 }
1803
1804 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1805 {
1806 struct protection_domain *domain = dom->priv;
1807
1808 if (!domain)
1809 return;
1810
1811 if (domain->dev_cnt > 0)
1812 cleanup_domain(domain);
1813
1814 BUG_ON(domain->dev_cnt != 0);
1815
1816 free_pagetable(domain);
1817
1818 domain_id_free(domain->id);
1819
1820 kfree(domain);
1821
1822 dom->priv = NULL;
1823 }
1824
1825 static void amd_iommu_detach_device(struct iommu_domain *dom,
1826 struct device *dev)
1827 {
1828 struct protection_domain *domain = dom->priv;
1829 struct amd_iommu *iommu;
1830 struct pci_dev *pdev;
1831 u16 devid;
1832
1833 if (dev->bus != &pci_bus_type)
1834 return;
1835
1836 pdev = to_pci_dev(dev);
1837
1838 devid = calc_devid(pdev->bus->number, pdev->devfn);
1839
1840 if (devid > 0)
1841 detach_device(domain, devid);
1842
1843 iommu = amd_iommu_rlookup_table[devid];
1844 if (!iommu)
1845 return;
1846
1847 iommu_queue_inv_dev_entry(iommu, devid);
1848 iommu_completion_wait(iommu);
1849 }
1850
1851 static int amd_iommu_attach_device(struct iommu_domain *dom,
1852 struct device *dev)
1853 {
1854 struct protection_domain *domain = dom->priv;
1855 struct protection_domain *old_domain;
1856 struct amd_iommu *iommu;
1857 struct pci_dev *pdev;
1858 u16 devid;
1859
1860 if (dev->bus != &pci_bus_type)
1861 return -EINVAL;
1862
1863 pdev = to_pci_dev(dev);
1864
1865 devid = calc_devid(pdev->bus->number, pdev->devfn);
1866
1867 if (devid >= amd_iommu_last_bdf ||
1868 devid != amd_iommu_alias_table[devid])
1869 return -EINVAL;
1870
1871 iommu = amd_iommu_rlookup_table[devid];
1872 if (!iommu)
1873 return -EINVAL;
1874
1875 old_domain = domain_for_device(devid);
1876 if (old_domain)
1877 return -EBUSY;
1878
1879 attach_device(iommu, domain, devid);
1880
1881 iommu_completion_wait(iommu);
1882
1883 return 0;
1884 }
1885
1886 static int amd_iommu_map_range(struct iommu_domain *dom,
1887 unsigned long iova, phys_addr_t paddr,
1888 size_t size, int iommu_prot)
1889 {
1890 struct protection_domain *domain = dom->priv;
1891 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1892 int prot = 0;
1893 int ret;
1894
1895 if (iommu_prot & IOMMU_READ)
1896 prot |= IOMMU_PROT_IR;
1897 if (iommu_prot & IOMMU_WRITE)
1898 prot |= IOMMU_PROT_IW;
1899
1900 iova &= PAGE_MASK;
1901 paddr &= PAGE_MASK;
1902
1903 for (i = 0; i < npages; ++i) {
1904 ret = iommu_map_page(domain, iova, paddr, prot);
1905 if (ret)
1906 return ret;
1907
1908 iova += PAGE_SIZE;
1909 paddr += PAGE_SIZE;
1910 }
1911
1912 return 0;
1913 }
1914
1915 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1916 unsigned long iova, size_t size)
1917 {
1918
1919 struct protection_domain *domain = dom->priv;
1920 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1921
1922 iova &= PAGE_MASK;
1923
1924 for (i = 0; i < npages; ++i) {
1925 iommu_unmap_page(domain, iova);
1926 iova += PAGE_SIZE;
1927 }
1928
1929 iommu_flush_domain(domain->id);
1930 }
1931
1932 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1933 unsigned long iova)
1934 {
1935 struct protection_domain *domain = dom->priv;
1936 unsigned long offset = iova & ~PAGE_MASK;
1937 phys_addr_t paddr;
1938 u64 *pte;
1939
1940 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1941
1942 if (!IOMMU_PTE_PRESENT(*pte))
1943 return 0;
1944
1945 pte = IOMMU_PTE_PAGE(*pte);
1946 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1947
1948 if (!IOMMU_PTE_PRESENT(*pte))
1949 return 0;
1950
1951 pte = IOMMU_PTE_PAGE(*pte);
1952 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1953
1954 if (!IOMMU_PTE_PRESENT(*pte))
1955 return 0;
1956
1957 paddr = *pte & IOMMU_PAGE_MASK;
1958 paddr |= offset;
1959
1960 return paddr;
1961 }
1962
1963 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
1964 unsigned long cap)
1965 {
1966 return 0;
1967 }
1968
1969 static struct iommu_ops amd_iommu_ops = {
1970 .domain_init = amd_iommu_domain_init,
1971 .domain_destroy = amd_iommu_domain_destroy,
1972 .attach_dev = amd_iommu_attach_device,
1973 .detach_dev = amd_iommu_detach_device,
1974 .map = amd_iommu_map_range,
1975 .unmap = amd_iommu_unmap_range,
1976 .iova_to_phys = amd_iommu_iova_to_phys,
1977 .domain_has_cap = amd_iommu_domain_has_cap,
1978 };
1979
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