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x86/amd-iommu: Remove iommu specific handling from dma_ops path
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kernel / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 /*
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
48 */
49 static struct protection_domain *pt_domain;
50
51 static struct iommu_ops amd_iommu_ops;
52
53 /*
54 * general struct to manage commands send to an IOMMU
55 */
56 struct iommu_cmd {
57 u32 data[4];
58 };
59
60 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
61 struct unity_map_entry *e);
62 static struct dma_ops_domain *find_protection_domain(u16 devid);
63 static u64 *alloc_pte(struct protection_domain *domain,
64 unsigned long address, int end_lvl,
65 u64 **pte_page, gfp_t gfp);
66 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
67 unsigned long start_page,
68 unsigned int pages);
69 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
70 static u64 *fetch_pte(struct protection_domain *domain,
71 unsigned long address, int map_size);
72 static void update_domain(struct protection_domain *domain);
73
74 #ifdef CONFIG_AMD_IOMMU_STATS
75
76 /*
77 * Initialization code for statistics collection
78 */
79
80 DECLARE_STATS_COUNTER(compl_wait);
81 DECLARE_STATS_COUNTER(cnt_map_single);
82 DECLARE_STATS_COUNTER(cnt_unmap_single);
83 DECLARE_STATS_COUNTER(cnt_map_sg);
84 DECLARE_STATS_COUNTER(cnt_unmap_sg);
85 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
86 DECLARE_STATS_COUNTER(cnt_free_coherent);
87 DECLARE_STATS_COUNTER(cross_page);
88 DECLARE_STATS_COUNTER(domain_flush_single);
89 DECLARE_STATS_COUNTER(domain_flush_all);
90 DECLARE_STATS_COUNTER(alloced_io_mem);
91 DECLARE_STATS_COUNTER(total_map_requests);
92
93 static struct dentry *stats_dir;
94 static struct dentry *de_isolate;
95 static struct dentry *de_fflush;
96
97 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
98 {
99 if (stats_dir == NULL)
100 return;
101
102 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
103 &cnt->value);
104 }
105
106 static void amd_iommu_stats_init(void)
107 {
108 stats_dir = debugfs_create_dir("amd-iommu", NULL);
109 if (stats_dir == NULL)
110 return;
111
112 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
113 (u32 *)&amd_iommu_isolate);
114
115 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
116 (u32 *)&amd_iommu_unmap_flush);
117
118 amd_iommu_stats_add(&compl_wait);
119 amd_iommu_stats_add(&cnt_map_single);
120 amd_iommu_stats_add(&cnt_unmap_single);
121 amd_iommu_stats_add(&cnt_map_sg);
122 amd_iommu_stats_add(&cnt_unmap_sg);
123 amd_iommu_stats_add(&cnt_alloc_coherent);
124 amd_iommu_stats_add(&cnt_free_coherent);
125 amd_iommu_stats_add(&cross_page);
126 amd_iommu_stats_add(&domain_flush_single);
127 amd_iommu_stats_add(&domain_flush_all);
128 amd_iommu_stats_add(&alloced_io_mem);
129 amd_iommu_stats_add(&total_map_requests);
130 }
131
132 #endif
133
134 /****************************************************************************
135 *
136 * Interrupt handling functions
137 *
138 ****************************************************************************/
139
140 static void dump_dte_entry(u16 devid)
141 {
142 int i;
143
144 for (i = 0; i < 8; ++i)
145 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
146 amd_iommu_dev_table[devid].data[i]);
147 }
148
149 static void dump_command(unsigned long phys_addr)
150 {
151 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
152 int i;
153
154 for (i = 0; i < 4; ++i)
155 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
156 }
157
158 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
159 {
160 u32 *event = __evt;
161 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
162 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
163 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
164 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
165 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
166
167 printk(KERN_ERR "AMD-Vi: Event logged [");
168
169 switch (type) {
170 case EVENT_TYPE_ILL_DEV:
171 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
172 "address=0x%016llx flags=0x%04x]\n",
173 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
174 address, flags);
175 dump_dte_entry(devid);
176 break;
177 case EVENT_TYPE_IO_FAULT:
178 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
179 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
180 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 domid, address, flags);
182 break;
183 case EVENT_TYPE_DEV_TAB_ERR:
184 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
185 "address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 address, flags);
188 break;
189 case EVENT_TYPE_PAGE_TAB_ERR:
190 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
191 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
192 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
193 domid, address, flags);
194 break;
195 case EVENT_TYPE_ILL_CMD:
196 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
197 reset_iommu_command_buffer(iommu);
198 dump_command(address);
199 break;
200 case EVENT_TYPE_CMD_HARD_ERR:
201 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
202 "flags=0x%04x]\n", address, flags);
203 break;
204 case EVENT_TYPE_IOTLB_INV_TO:
205 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
206 "address=0x%016llx]\n",
207 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
208 address);
209 break;
210 case EVENT_TYPE_INV_DEV_REQ:
211 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
212 "address=0x%016llx flags=0x%04x]\n",
213 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
214 address, flags);
215 break;
216 default:
217 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
218 }
219 }
220
221 static void iommu_poll_events(struct amd_iommu *iommu)
222 {
223 u32 head, tail;
224 unsigned long flags;
225
226 spin_lock_irqsave(&iommu->lock, flags);
227
228 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
229 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
230
231 while (head != tail) {
232 iommu_print_event(iommu, iommu->evt_buf + head);
233 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
234 }
235
236 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
237
238 spin_unlock_irqrestore(&iommu->lock, flags);
239 }
240
241 irqreturn_t amd_iommu_int_handler(int irq, void *data)
242 {
243 struct amd_iommu *iommu;
244
245 for_each_iommu(iommu)
246 iommu_poll_events(iommu);
247
248 return IRQ_HANDLED;
249 }
250
251 /****************************************************************************
252 *
253 * IOMMU command queuing functions
254 *
255 ****************************************************************************/
256
257 /*
258 * Writes the command to the IOMMUs command buffer and informs the
259 * hardware about the new command. Must be called with iommu->lock held.
260 */
261 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
262 {
263 u32 tail, head;
264 u8 *target;
265
266 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
267 target = iommu->cmd_buf + tail;
268 memcpy_toio(target, cmd, sizeof(*cmd));
269 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
270 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
271 if (tail == head)
272 return -ENOMEM;
273 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
274
275 return 0;
276 }
277
278 /*
279 * General queuing function for commands. Takes iommu->lock and calls
280 * __iommu_queue_command().
281 */
282 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
283 {
284 unsigned long flags;
285 int ret;
286
287 spin_lock_irqsave(&iommu->lock, flags);
288 ret = __iommu_queue_command(iommu, cmd);
289 if (!ret)
290 iommu->need_sync = true;
291 spin_unlock_irqrestore(&iommu->lock, flags);
292
293 return ret;
294 }
295
296 /*
297 * This function waits until an IOMMU has completed a completion
298 * wait command
299 */
300 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
301 {
302 int ready = 0;
303 unsigned status = 0;
304 unsigned long i = 0;
305
306 INC_STATS_COUNTER(compl_wait);
307
308 while (!ready && (i < EXIT_LOOP_COUNT)) {
309 ++i;
310 /* wait for the bit to become one */
311 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
312 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
313 }
314
315 /* set bit back to zero */
316 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
317 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
318
319 if (unlikely(i == EXIT_LOOP_COUNT)) {
320 spin_unlock(&iommu->lock);
321 reset_iommu_command_buffer(iommu);
322 spin_lock(&iommu->lock);
323 }
324 }
325
326 /*
327 * This function queues a completion wait command into the command
328 * buffer of an IOMMU
329 */
330 static int __iommu_completion_wait(struct amd_iommu *iommu)
331 {
332 struct iommu_cmd cmd;
333
334 memset(&cmd, 0, sizeof(cmd));
335 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
336 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
337
338 return __iommu_queue_command(iommu, &cmd);
339 }
340
341 /*
342 * This function is called whenever we need to ensure that the IOMMU has
343 * completed execution of all commands we sent. It sends a
344 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
345 * us about that by writing a value to a physical address we pass with
346 * the command.
347 */
348 static int iommu_completion_wait(struct amd_iommu *iommu)
349 {
350 int ret = 0;
351 unsigned long flags;
352
353 spin_lock_irqsave(&iommu->lock, flags);
354
355 if (!iommu->need_sync)
356 goto out;
357
358 ret = __iommu_completion_wait(iommu);
359
360 iommu->need_sync = false;
361
362 if (ret)
363 goto out;
364
365 __iommu_wait_for_completion(iommu);
366
367 out:
368 spin_unlock_irqrestore(&iommu->lock, flags);
369
370 return 0;
371 }
372
373 static void iommu_flush_complete(struct protection_domain *domain)
374 {
375 int i;
376
377 for (i = 0; i < amd_iommus_present; ++i) {
378 if (!domain->dev_iommu[i])
379 continue;
380
381 /*
382 * Devices of this domain are behind this IOMMU
383 * We need to wait for completion of all commands.
384 */
385 iommu_completion_wait(amd_iommus[i]);
386 }
387 }
388
389 /*
390 * Command send function for invalidating a device table entry
391 */
392 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
393 {
394 struct iommu_cmd cmd;
395 int ret;
396
397 BUG_ON(iommu == NULL);
398
399 memset(&cmd, 0, sizeof(cmd));
400 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
401 cmd.data[0] = devid;
402
403 ret = iommu_queue_command(iommu, &cmd);
404
405 return ret;
406 }
407
408 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
409 u16 domid, int pde, int s)
410 {
411 memset(cmd, 0, sizeof(*cmd));
412 address &= PAGE_MASK;
413 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
414 cmd->data[1] |= domid;
415 cmd->data[2] = lower_32_bits(address);
416 cmd->data[3] = upper_32_bits(address);
417 if (s) /* size bit - we flush more than one 4kb page */
418 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
419 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
420 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
421 }
422
423 /*
424 * Generic command send function for invalidaing TLB entries
425 */
426 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
427 u64 address, u16 domid, int pde, int s)
428 {
429 struct iommu_cmd cmd;
430 int ret;
431
432 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
433
434 ret = iommu_queue_command(iommu, &cmd);
435
436 return ret;
437 }
438
439 /*
440 * TLB invalidation function which is called from the mapping functions.
441 * It invalidates a single PTE if the range to flush is within a single
442 * page. Otherwise it flushes the whole TLB of the IOMMU.
443 */
444 static void __iommu_flush_pages(struct protection_domain *domain,
445 u64 address, size_t size, int pde)
446 {
447 int s = 0, i;
448 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
449
450 address &= PAGE_MASK;
451
452 if (pages > 1) {
453 /*
454 * If we have to flush more than one page, flush all
455 * TLB entries for this domain
456 */
457 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
458 s = 1;
459 }
460
461
462 for (i = 0; i < amd_iommus_present; ++i) {
463 if (!domain->dev_iommu[i])
464 continue;
465
466 /*
467 * Devices of this domain are behind this IOMMU
468 * We need a TLB flush
469 */
470 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
471 domain->id, pde, s);
472 }
473
474 return;
475 }
476
477 static void iommu_flush_pages(struct protection_domain *domain,
478 u64 address, size_t size)
479 {
480 __iommu_flush_pages(domain, address, size, 0);
481 }
482
483 /* Flush the whole IO/TLB for a given protection domain */
484 static void iommu_flush_tlb(struct protection_domain *domain)
485 {
486 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
487 }
488
489 /* Flush the whole IO/TLB for a given protection domain - including PDE */
490 static void iommu_flush_tlb_pde(struct protection_domain *domain)
491 {
492 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
493 }
494
495 /*
496 * This function flushes all domains that have devices on the given IOMMU
497 */
498 static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
499 {
500 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
501 struct protection_domain *domain;
502 unsigned long flags;
503
504 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
505
506 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
507 if (domain->dev_iommu[iommu->index] == 0)
508 continue;
509
510 spin_lock(&domain->lock);
511 iommu_queue_inv_iommu_pages(iommu, address, domain->id, 1, 1);
512 iommu_flush_complete(domain);
513 spin_unlock(&domain->lock);
514 }
515
516 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
517 }
518
519 /*
520 * This function uses heavy locking and may disable irqs for some time. But
521 * this is no issue because it is only called during resume.
522 */
523 void amd_iommu_flush_all_domains(void)
524 {
525 struct protection_domain *domain;
526 unsigned long flags;
527
528 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
529
530 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
531 spin_lock(&domain->lock);
532 iommu_flush_tlb_pde(domain);
533 iommu_flush_complete(domain);
534 spin_unlock(&domain->lock);
535 }
536
537 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
538 }
539
540 static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
541 {
542 int i;
543
544 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
545 if (iommu != amd_iommu_rlookup_table[i])
546 continue;
547
548 iommu_queue_inv_dev_entry(iommu, i);
549 iommu_completion_wait(iommu);
550 }
551 }
552
553 static void flush_devices_by_domain(struct protection_domain *domain)
554 {
555 struct amd_iommu *iommu;
556 int i;
557
558 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
559 if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
560 (amd_iommu_pd_table[i] != domain))
561 continue;
562
563 iommu = amd_iommu_rlookup_table[i];
564 if (!iommu)
565 continue;
566
567 iommu_queue_inv_dev_entry(iommu, i);
568 iommu_completion_wait(iommu);
569 }
570 }
571
572 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
573 {
574 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
575
576 if (iommu->reset_in_progress)
577 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
578
579 iommu->reset_in_progress = true;
580
581 amd_iommu_reset_cmd_buffer(iommu);
582 flush_all_devices_for_iommu(iommu);
583 flush_all_domains_on_iommu(iommu);
584
585 iommu->reset_in_progress = false;
586 }
587
588 void amd_iommu_flush_all_devices(void)
589 {
590 flush_devices_by_domain(NULL);
591 }
592
593 /****************************************************************************
594 *
595 * The functions below are used the create the page table mappings for
596 * unity mapped regions.
597 *
598 ****************************************************************************/
599
600 /*
601 * Generic mapping functions. It maps a physical address into a DMA
602 * address space. It allocates the page table pages if necessary.
603 * In the future it can be extended to a generic mapping function
604 * supporting all features of AMD IOMMU page tables like level skipping
605 * and full 64 bit address spaces.
606 */
607 static int iommu_map_page(struct protection_domain *dom,
608 unsigned long bus_addr,
609 unsigned long phys_addr,
610 int prot,
611 int map_size)
612 {
613 u64 __pte, *pte;
614
615 bus_addr = PAGE_ALIGN(bus_addr);
616 phys_addr = PAGE_ALIGN(phys_addr);
617
618 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
619 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
620
621 if (!(prot & IOMMU_PROT_MASK))
622 return -EINVAL;
623
624 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
625
626 if (IOMMU_PTE_PRESENT(*pte))
627 return -EBUSY;
628
629 __pte = phys_addr | IOMMU_PTE_P;
630 if (prot & IOMMU_PROT_IR)
631 __pte |= IOMMU_PTE_IR;
632 if (prot & IOMMU_PROT_IW)
633 __pte |= IOMMU_PTE_IW;
634
635 *pte = __pte;
636
637 update_domain(dom);
638
639 return 0;
640 }
641
642 static void iommu_unmap_page(struct protection_domain *dom,
643 unsigned long bus_addr, int map_size)
644 {
645 u64 *pte = fetch_pte(dom, bus_addr, map_size);
646
647 if (pte)
648 *pte = 0;
649 }
650
651 /*
652 * This function checks if a specific unity mapping entry is needed for
653 * this specific IOMMU.
654 */
655 static int iommu_for_unity_map(struct amd_iommu *iommu,
656 struct unity_map_entry *entry)
657 {
658 u16 bdf, i;
659
660 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
661 bdf = amd_iommu_alias_table[i];
662 if (amd_iommu_rlookup_table[bdf] == iommu)
663 return 1;
664 }
665
666 return 0;
667 }
668
669 /*
670 * Init the unity mappings for a specific IOMMU in the system
671 *
672 * Basically iterates over all unity mapping entries and applies them to
673 * the default domain DMA of that IOMMU if necessary.
674 */
675 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
676 {
677 struct unity_map_entry *entry;
678 int ret;
679
680 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
681 if (!iommu_for_unity_map(iommu, entry))
682 continue;
683 ret = dma_ops_unity_map(iommu->default_dom, entry);
684 if (ret)
685 return ret;
686 }
687
688 return 0;
689 }
690
691 /*
692 * This function actually applies the mapping to the page table of the
693 * dma_ops domain.
694 */
695 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
696 struct unity_map_entry *e)
697 {
698 u64 addr;
699 int ret;
700
701 for (addr = e->address_start; addr < e->address_end;
702 addr += PAGE_SIZE) {
703 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
704 PM_MAP_4k);
705 if (ret)
706 return ret;
707 /*
708 * if unity mapping is in aperture range mark the page
709 * as allocated in the aperture
710 */
711 if (addr < dma_dom->aperture_size)
712 __set_bit(addr >> PAGE_SHIFT,
713 dma_dom->aperture[0]->bitmap);
714 }
715
716 return 0;
717 }
718
719 /*
720 * Inits the unity mappings required for a specific device
721 */
722 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
723 u16 devid)
724 {
725 struct unity_map_entry *e;
726 int ret;
727
728 list_for_each_entry(e, &amd_iommu_unity_map, list) {
729 if (!(devid >= e->devid_start && devid <= e->devid_end))
730 continue;
731 ret = dma_ops_unity_map(dma_dom, e);
732 if (ret)
733 return ret;
734 }
735
736 return 0;
737 }
738
739 /****************************************************************************
740 *
741 * The next functions belong to the address allocator for the dma_ops
742 * interface functions. They work like the allocators in the other IOMMU
743 * drivers. Its basically a bitmap which marks the allocated pages in
744 * the aperture. Maybe it could be enhanced in the future to a more
745 * efficient allocator.
746 *
747 ****************************************************************************/
748
749 /*
750 * The address allocator core functions.
751 *
752 * called with domain->lock held
753 */
754
755 /*
756 * This function checks if there is a PTE for a given dma address. If
757 * there is one, it returns the pointer to it.
758 */
759 static u64 *fetch_pte(struct protection_domain *domain,
760 unsigned long address, int map_size)
761 {
762 int level;
763 u64 *pte;
764
765 level = domain->mode - 1;
766 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
767
768 while (level > map_size) {
769 if (!IOMMU_PTE_PRESENT(*pte))
770 return NULL;
771
772 level -= 1;
773
774 pte = IOMMU_PTE_PAGE(*pte);
775 pte = &pte[PM_LEVEL_INDEX(level, address)];
776
777 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
778 pte = NULL;
779 break;
780 }
781 }
782
783 return pte;
784 }
785
786 /*
787 * This function is used to add a new aperture range to an existing
788 * aperture in case of dma_ops domain allocation or address allocation
789 * failure.
790 */
791 static int alloc_new_range(struct dma_ops_domain *dma_dom,
792 bool populate, gfp_t gfp)
793 {
794 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
795 struct amd_iommu *iommu;
796 int i;
797
798 #ifdef CONFIG_IOMMU_STRESS
799 populate = false;
800 #endif
801
802 if (index >= APERTURE_MAX_RANGES)
803 return -ENOMEM;
804
805 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
806 if (!dma_dom->aperture[index])
807 return -ENOMEM;
808
809 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
810 if (!dma_dom->aperture[index]->bitmap)
811 goto out_free;
812
813 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
814
815 if (populate) {
816 unsigned long address = dma_dom->aperture_size;
817 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
818 u64 *pte, *pte_page;
819
820 for (i = 0; i < num_ptes; ++i) {
821 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
822 &pte_page, gfp);
823 if (!pte)
824 goto out_free;
825
826 dma_dom->aperture[index]->pte_pages[i] = pte_page;
827
828 address += APERTURE_RANGE_SIZE / 64;
829 }
830 }
831
832 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
833
834 /* Intialize the exclusion range if necessary */
835 for_each_iommu(iommu) {
836 if (iommu->exclusion_start &&
837 iommu->exclusion_start >= dma_dom->aperture[index]->offset
838 && iommu->exclusion_start < dma_dom->aperture_size) {
839 unsigned long startpage;
840 int pages = iommu_num_pages(iommu->exclusion_start,
841 iommu->exclusion_length,
842 PAGE_SIZE);
843 startpage = iommu->exclusion_start >> PAGE_SHIFT;
844 dma_ops_reserve_addresses(dma_dom, startpage, pages);
845 }
846 }
847
848 /*
849 * Check for areas already mapped as present in the new aperture
850 * range and mark those pages as reserved in the allocator. Such
851 * mappings may already exist as a result of requested unity
852 * mappings for devices.
853 */
854 for (i = dma_dom->aperture[index]->offset;
855 i < dma_dom->aperture_size;
856 i += PAGE_SIZE) {
857 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
858 if (!pte || !IOMMU_PTE_PRESENT(*pte))
859 continue;
860
861 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
862 }
863
864 update_domain(&dma_dom->domain);
865
866 return 0;
867
868 out_free:
869 update_domain(&dma_dom->domain);
870
871 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
872
873 kfree(dma_dom->aperture[index]);
874 dma_dom->aperture[index] = NULL;
875
876 return -ENOMEM;
877 }
878
879 static unsigned long dma_ops_area_alloc(struct device *dev,
880 struct dma_ops_domain *dom,
881 unsigned int pages,
882 unsigned long align_mask,
883 u64 dma_mask,
884 unsigned long start)
885 {
886 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
887 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
888 int i = start >> APERTURE_RANGE_SHIFT;
889 unsigned long boundary_size;
890 unsigned long address = -1;
891 unsigned long limit;
892
893 next_bit >>= PAGE_SHIFT;
894
895 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
896 PAGE_SIZE) >> PAGE_SHIFT;
897
898 for (;i < max_index; ++i) {
899 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
900
901 if (dom->aperture[i]->offset >= dma_mask)
902 break;
903
904 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
905 dma_mask >> PAGE_SHIFT);
906
907 address = iommu_area_alloc(dom->aperture[i]->bitmap,
908 limit, next_bit, pages, 0,
909 boundary_size, align_mask);
910 if (address != -1) {
911 address = dom->aperture[i]->offset +
912 (address << PAGE_SHIFT);
913 dom->next_address = address + (pages << PAGE_SHIFT);
914 break;
915 }
916
917 next_bit = 0;
918 }
919
920 return address;
921 }
922
923 static unsigned long dma_ops_alloc_addresses(struct device *dev,
924 struct dma_ops_domain *dom,
925 unsigned int pages,
926 unsigned long align_mask,
927 u64 dma_mask)
928 {
929 unsigned long address;
930
931 #ifdef CONFIG_IOMMU_STRESS
932 dom->next_address = 0;
933 dom->need_flush = true;
934 #endif
935
936 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
937 dma_mask, dom->next_address);
938
939 if (address == -1) {
940 dom->next_address = 0;
941 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
942 dma_mask, 0);
943 dom->need_flush = true;
944 }
945
946 if (unlikely(address == -1))
947 address = DMA_ERROR_CODE;
948
949 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
950
951 return address;
952 }
953
954 /*
955 * The address free function.
956 *
957 * called with domain->lock held
958 */
959 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
960 unsigned long address,
961 unsigned int pages)
962 {
963 unsigned i = address >> APERTURE_RANGE_SHIFT;
964 struct aperture_range *range = dom->aperture[i];
965
966 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
967
968 #ifdef CONFIG_IOMMU_STRESS
969 if (i < 4)
970 return;
971 #endif
972
973 if (address >= dom->next_address)
974 dom->need_flush = true;
975
976 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
977
978 iommu_area_free(range->bitmap, address, pages);
979
980 }
981
982 /****************************************************************************
983 *
984 * The next functions belong to the domain allocation. A domain is
985 * allocated for every IOMMU as the default domain. If device isolation
986 * is enabled, every device get its own domain. The most important thing
987 * about domains is the page table mapping the DMA address space they
988 * contain.
989 *
990 ****************************************************************************/
991
992 /*
993 * This function adds a protection domain to the global protection domain list
994 */
995 static void add_domain_to_list(struct protection_domain *domain)
996 {
997 unsigned long flags;
998
999 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1000 list_add(&domain->list, &amd_iommu_pd_list);
1001 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1002 }
1003
1004 /*
1005 * This function removes a protection domain to the global
1006 * protection domain list
1007 */
1008 static void del_domain_from_list(struct protection_domain *domain)
1009 {
1010 unsigned long flags;
1011
1012 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1013 list_del(&domain->list);
1014 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1015 }
1016
1017 static u16 domain_id_alloc(void)
1018 {
1019 unsigned long flags;
1020 int id;
1021
1022 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1023 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1024 BUG_ON(id == 0);
1025 if (id > 0 && id < MAX_DOMAIN_ID)
1026 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1027 else
1028 id = 0;
1029 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1030
1031 return id;
1032 }
1033
1034 static void domain_id_free(int id)
1035 {
1036 unsigned long flags;
1037
1038 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1039 if (id > 0 && id < MAX_DOMAIN_ID)
1040 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1041 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1042 }
1043
1044 /*
1045 * Used to reserve address ranges in the aperture (e.g. for exclusion
1046 * ranges.
1047 */
1048 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1049 unsigned long start_page,
1050 unsigned int pages)
1051 {
1052 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1053
1054 if (start_page + pages > last_page)
1055 pages = last_page - start_page;
1056
1057 for (i = start_page; i < start_page + pages; ++i) {
1058 int index = i / APERTURE_RANGE_PAGES;
1059 int page = i % APERTURE_RANGE_PAGES;
1060 __set_bit(page, dom->aperture[index]->bitmap);
1061 }
1062 }
1063
1064 static void free_pagetable(struct protection_domain *domain)
1065 {
1066 int i, j;
1067 u64 *p1, *p2, *p3;
1068
1069 p1 = domain->pt_root;
1070
1071 if (!p1)
1072 return;
1073
1074 for (i = 0; i < 512; ++i) {
1075 if (!IOMMU_PTE_PRESENT(p1[i]))
1076 continue;
1077
1078 p2 = IOMMU_PTE_PAGE(p1[i]);
1079 for (j = 0; j < 512; ++j) {
1080 if (!IOMMU_PTE_PRESENT(p2[j]))
1081 continue;
1082 p3 = IOMMU_PTE_PAGE(p2[j]);
1083 free_page((unsigned long)p3);
1084 }
1085
1086 free_page((unsigned long)p2);
1087 }
1088
1089 free_page((unsigned long)p1);
1090
1091 domain->pt_root = NULL;
1092 }
1093
1094 /*
1095 * Free a domain, only used if something went wrong in the
1096 * allocation path and we need to free an already allocated page table
1097 */
1098 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1099 {
1100 int i;
1101
1102 if (!dom)
1103 return;
1104
1105 del_domain_from_list(&dom->domain);
1106
1107 free_pagetable(&dom->domain);
1108
1109 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1110 if (!dom->aperture[i])
1111 continue;
1112 free_page((unsigned long)dom->aperture[i]->bitmap);
1113 kfree(dom->aperture[i]);
1114 }
1115
1116 kfree(dom);
1117 }
1118
1119 /*
1120 * Allocates a new protection domain usable for the dma_ops functions.
1121 * It also intializes the page table and the address allocator data
1122 * structures required for the dma_ops interface
1123 */
1124 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1125 {
1126 struct dma_ops_domain *dma_dom;
1127
1128 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1129 if (!dma_dom)
1130 return NULL;
1131
1132 spin_lock_init(&dma_dom->domain.lock);
1133
1134 dma_dom->domain.id = domain_id_alloc();
1135 if (dma_dom->domain.id == 0)
1136 goto free_dma_dom;
1137 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1138 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1139 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1140 dma_dom->domain.priv = dma_dom;
1141 if (!dma_dom->domain.pt_root)
1142 goto free_dma_dom;
1143
1144 dma_dom->need_flush = false;
1145 dma_dom->target_dev = 0xffff;
1146
1147 add_domain_to_list(&dma_dom->domain);
1148
1149 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1150 goto free_dma_dom;
1151
1152 /*
1153 * mark the first page as allocated so we never return 0 as
1154 * a valid dma-address. So we can use 0 as error value
1155 */
1156 dma_dom->aperture[0]->bitmap[0] = 1;
1157 dma_dom->next_address = 0;
1158
1159
1160 return dma_dom;
1161
1162 free_dma_dom:
1163 dma_ops_domain_free(dma_dom);
1164
1165 return NULL;
1166 }
1167
1168 /*
1169 * little helper function to check whether a given protection domain is a
1170 * dma_ops domain
1171 */
1172 static bool dma_ops_domain(struct protection_domain *domain)
1173 {
1174 return domain->flags & PD_DMA_OPS_MASK;
1175 }
1176
1177 /*
1178 * Find out the protection domain structure for a given PCI device. This
1179 * will give us the pointer to the page table root for example.
1180 */
1181 static struct protection_domain *domain_for_device(u16 devid)
1182 {
1183 struct protection_domain *dom;
1184 unsigned long flags;
1185
1186 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1187 dom = amd_iommu_pd_table[devid];
1188 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1189
1190 return dom;
1191 }
1192
1193 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1194 {
1195 u64 pte_root = virt_to_phys(domain->pt_root);
1196
1197 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1198 << DEV_ENTRY_MODE_SHIFT;
1199 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1200
1201 amd_iommu_dev_table[devid].data[2] = domain->id;
1202 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1203 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1204
1205 amd_iommu_pd_table[devid] = domain;
1206 }
1207
1208 /*
1209 * If a device is not yet associated with a domain, this function does
1210 * assigns it visible for the hardware
1211 */
1212 static void __attach_device(struct amd_iommu *iommu,
1213 struct protection_domain *domain,
1214 u16 devid)
1215 {
1216 /* lock domain */
1217 spin_lock(&domain->lock);
1218
1219 /* update DTE entry */
1220 set_dte_entry(devid, domain);
1221
1222 /* Do reference counting */
1223 domain->dev_iommu[iommu->index] += 1;
1224 domain->dev_cnt += 1;
1225
1226 /* ready */
1227 spin_unlock(&domain->lock);
1228 }
1229
1230 /*
1231 * If a device is not yet associated with a domain, this function does
1232 * assigns it visible for the hardware
1233 */
1234 static void attach_device(struct amd_iommu *iommu,
1235 struct protection_domain *domain,
1236 u16 devid)
1237 {
1238 unsigned long flags;
1239
1240 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1241 __attach_device(iommu, domain, devid);
1242 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1243
1244 /*
1245 * We might boot into a crash-kernel here. The crashed kernel
1246 * left the caches in the IOMMU dirty. So we have to flush
1247 * here to evict all dirty stuff.
1248 */
1249 iommu_queue_inv_dev_entry(iommu, devid);
1250 iommu_flush_tlb_pde(domain);
1251 }
1252
1253 /*
1254 * Removes a device from a protection domain (unlocked)
1255 */
1256 static void __detach_device(struct protection_domain *domain, u16 devid)
1257 {
1258 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1259
1260 BUG_ON(!iommu);
1261
1262 /* lock domain */
1263 spin_lock(&domain->lock);
1264
1265 /* remove domain from the lookup table */
1266 amd_iommu_pd_table[devid] = NULL;
1267
1268 /* remove entry from the device table seen by the hardware */
1269 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1270 amd_iommu_dev_table[devid].data[1] = 0;
1271 amd_iommu_dev_table[devid].data[2] = 0;
1272
1273 amd_iommu_apply_erratum_63(devid);
1274
1275 /* decrease reference counters */
1276 domain->dev_iommu[iommu->index] -= 1;
1277 domain->dev_cnt -= 1;
1278
1279 /* ready */
1280 spin_unlock(&domain->lock);
1281
1282 /*
1283 * If we run in passthrough mode the device must be assigned to the
1284 * passthrough domain if it is detached from any other domain
1285 */
1286 if (iommu_pass_through) {
1287 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1288 __attach_device(iommu, pt_domain, devid);
1289 }
1290 }
1291
1292 /*
1293 * Removes a device from a protection domain (with devtable_lock held)
1294 */
1295 static void detach_device(struct protection_domain *domain, u16 devid)
1296 {
1297 unsigned long flags;
1298
1299 /* lock device table */
1300 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1301 __detach_device(domain, devid);
1302 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1303 }
1304
1305 static int device_change_notifier(struct notifier_block *nb,
1306 unsigned long action, void *data)
1307 {
1308 struct device *dev = data;
1309 struct pci_dev *pdev = to_pci_dev(dev);
1310 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1311 struct protection_domain *domain;
1312 struct dma_ops_domain *dma_domain;
1313 struct amd_iommu *iommu;
1314 unsigned long flags;
1315
1316 if (devid > amd_iommu_last_bdf)
1317 goto out;
1318
1319 devid = amd_iommu_alias_table[devid];
1320
1321 iommu = amd_iommu_rlookup_table[devid];
1322 if (iommu == NULL)
1323 goto out;
1324
1325 domain = domain_for_device(devid);
1326
1327 if (domain && !dma_ops_domain(domain))
1328 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1329 "to a non-dma-ops domain\n", dev_name(dev));
1330
1331 switch (action) {
1332 case BUS_NOTIFY_UNBOUND_DRIVER:
1333 if (!domain)
1334 goto out;
1335 if (iommu_pass_through)
1336 break;
1337 detach_device(domain, devid);
1338 break;
1339 case BUS_NOTIFY_ADD_DEVICE:
1340 /* allocate a protection domain if a device is added */
1341 dma_domain = find_protection_domain(devid);
1342 if (dma_domain)
1343 goto out;
1344 dma_domain = dma_ops_domain_alloc(iommu);
1345 if (!dma_domain)
1346 goto out;
1347 dma_domain->target_dev = devid;
1348
1349 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1350 list_add_tail(&dma_domain->list, &iommu_pd_list);
1351 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1352
1353 break;
1354 default:
1355 goto out;
1356 }
1357
1358 iommu_queue_inv_dev_entry(iommu, devid);
1359 iommu_completion_wait(iommu);
1360
1361 out:
1362 return 0;
1363 }
1364
1365 static struct notifier_block device_nb = {
1366 .notifier_call = device_change_notifier,
1367 };
1368
1369 /*****************************************************************************
1370 *
1371 * The next functions belong to the dma_ops mapping/unmapping code.
1372 *
1373 *****************************************************************************/
1374
1375 /*
1376 * This function checks if the driver got a valid device from the caller to
1377 * avoid dereferencing invalid pointers.
1378 */
1379 static bool check_device(struct device *dev)
1380 {
1381 u16 bdf;
1382 struct pci_dev *pcidev;
1383
1384 if (!dev || !dev->dma_mask)
1385 return false;
1386
1387 /* No device or no PCI device */
1388 if (!dev || dev->bus != &pci_bus_type)
1389 return false;
1390
1391 pcidev = to_pci_dev(dev);
1392
1393 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1394
1395 /* Out of our scope? */
1396 if (bdf > amd_iommu_last_bdf)
1397 return false;
1398
1399 if (amd_iommu_rlookup_table[bdf] == NULL)
1400 return false;
1401
1402 return true;
1403 }
1404
1405 /*
1406 * In this function the list of preallocated protection domains is traversed to
1407 * find the domain for a specific device
1408 */
1409 static struct dma_ops_domain *find_protection_domain(u16 devid)
1410 {
1411 struct dma_ops_domain *entry, *ret = NULL;
1412 unsigned long flags;
1413
1414 if (list_empty(&iommu_pd_list))
1415 return NULL;
1416
1417 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1418
1419 list_for_each_entry(entry, &iommu_pd_list, list) {
1420 if (entry->target_dev == devid) {
1421 ret = entry;
1422 break;
1423 }
1424 }
1425
1426 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1427
1428 return ret;
1429 }
1430
1431 /*
1432 * In the dma_ops path we only have the struct device. This function
1433 * finds the corresponding IOMMU, the protection domain and the
1434 * requestor id for a given device.
1435 * If the device is not yet associated with a domain this is also done
1436 * in this function.
1437 */
1438 static bool get_device_resources(struct device *dev,
1439 struct protection_domain **domain,
1440 u16 *bdf)
1441 {
1442 struct dma_ops_domain *dma_dom;
1443 struct amd_iommu *iommu;
1444 struct pci_dev *pcidev;
1445 u16 _bdf;
1446
1447 if (!check_device(dev))
1448 return false;
1449
1450 pcidev = to_pci_dev(dev);
1451 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1452 *bdf = amd_iommu_alias_table[_bdf];
1453 iommu = amd_iommu_rlookup_table[*bdf];
1454 *domain = domain_for_device(*bdf);
1455
1456 if (*domain == NULL) {
1457 dma_dom = find_protection_domain(*bdf);
1458 if (!dma_dom)
1459 dma_dom = iommu->default_dom;
1460 *domain = &dma_dom->domain;
1461 attach_device(iommu, *domain, *bdf);
1462 DUMP_printk("Using protection domain %d for device %s\n",
1463 (*domain)->id, dev_name(dev));
1464 }
1465
1466 if (domain_for_device(_bdf) == NULL)
1467 attach_device(iommu, *domain, _bdf);
1468
1469 return true;
1470 }
1471
1472 static void update_device_table(struct protection_domain *domain)
1473 {
1474 unsigned long flags;
1475 int i;
1476
1477 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1478 if (amd_iommu_pd_table[i] != domain)
1479 continue;
1480 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1481 set_dte_entry(i, domain);
1482 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1483 }
1484 }
1485
1486 static void update_domain(struct protection_domain *domain)
1487 {
1488 if (!domain->updated)
1489 return;
1490
1491 update_device_table(domain);
1492 flush_devices_by_domain(domain);
1493 iommu_flush_tlb_pde(domain);
1494
1495 domain->updated = false;
1496 }
1497
1498 /*
1499 * This function is used to add another level to an IO page table. Adding
1500 * another level increases the size of the address space by 9 bits to a size up
1501 * to 64 bits.
1502 */
1503 static bool increase_address_space(struct protection_domain *domain,
1504 gfp_t gfp)
1505 {
1506 u64 *pte;
1507
1508 if (domain->mode == PAGE_MODE_6_LEVEL)
1509 /* address space already 64 bit large */
1510 return false;
1511
1512 pte = (void *)get_zeroed_page(gfp);
1513 if (!pte)
1514 return false;
1515
1516 *pte = PM_LEVEL_PDE(domain->mode,
1517 virt_to_phys(domain->pt_root));
1518 domain->pt_root = pte;
1519 domain->mode += 1;
1520 domain->updated = true;
1521
1522 return true;
1523 }
1524
1525 static u64 *alloc_pte(struct protection_domain *domain,
1526 unsigned long address,
1527 int end_lvl,
1528 u64 **pte_page,
1529 gfp_t gfp)
1530 {
1531 u64 *pte, *page;
1532 int level;
1533
1534 while (address > PM_LEVEL_SIZE(domain->mode))
1535 increase_address_space(domain, gfp);
1536
1537 level = domain->mode - 1;
1538 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1539
1540 while (level > end_lvl) {
1541 if (!IOMMU_PTE_PRESENT(*pte)) {
1542 page = (u64 *)get_zeroed_page(gfp);
1543 if (!page)
1544 return NULL;
1545 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1546 }
1547
1548 level -= 1;
1549
1550 pte = IOMMU_PTE_PAGE(*pte);
1551
1552 if (pte_page && level == end_lvl)
1553 *pte_page = pte;
1554
1555 pte = &pte[PM_LEVEL_INDEX(level, address)];
1556 }
1557
1558 return pte;
1559 }
1560
1561 /*
1562 * This function fetches the PTE for a given address in the aperture
1563 */
1564 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1565 unsigned long address)
1566 {
1567 struct aperture_range *aperture;
1568 u64 *pte, *pte_page;
1569
1570 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1571 if (!aperture)
1572 return NULL;
1573
1574 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1575 if (!pte) {
1576 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1577 GFP_ATOMIC);
1578 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1579 } else
1580 pte += PM_LEVEL_INDEX(0, address);
1581
1582 update_domain(&dom->domain);
1583
1584 return pte;
1585 }
1586
1587 /*
1588 * This is the generic map function. It maps one 4kb page at paddr to
1589 * the given address in the DMA address space for the domain.
1590 */
1591 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1592 unsigned long address,
1593 phys_addr_t paddr,
1594 int direction)
1595 {
1596 u64 *pte, __pte;
1597
1598 WARN_ON(address > dom->aperture_size);
1599
1600 paddr &= PAGE_MASK;
1601
1602 pte = dma_ops_get_pte(dom, address);
1603 if (!pte)
1604 return DMA_ERROR_CODE;
1605
1606 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1607
1608 if (direction == DMA_TO_DEVICE)
1609 __pte |= IOMMU_PTE_IR;
1610 else if (direction == DMA_FROM_DEVICE)
1611 __pte |= IOMMU_PTE_IW;
1612 else if (direction == DMA_BIDIRECTIONAL)
1613 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1614
1615 WARN_ON(*pte);
1616
1617 *pte = __pte;
1618
1619 return (dma_addr_t)address;
1620 }
1621
1622 /*
1623 * The generic unmapping function for on page in the DMA address space.
1624 */
1625 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1626 unsigned long address)
1627 {
1628 struct aperture_range *aperture;
1629 u64 *pte;
1630
1631 if (address >= dom->aperture_size)
1632 return;
1633
1634 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1635 if (!aperture)
1636 return;
1637
1638 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1639 if (!pte)
1640 return;
1641
1642 pte += PM_LEVEL_INDEX(0, address);
1643
1644 WARN_ON(!*pte);
1645
1646 *pte = 0ULL;
1647 }
1648
1649 /*
1650 * This function contains common code for mapping of a physically
1651 * contiguous memory region into DMA address space. It is used by all
1652 * mapping functions provided with this IOMMU driver.
1653 * Must be called with the domain lock held.
1654 */
1655 static dma_addr_t __map_single(struct device *dev,
1656 struct dma_ops_domain *dma_dom,
1657 phys_addr_t paddr,
1658 size_t size,
1659 int dir,
1660 bool align,
1661 u64 dma_mask)
1662 {
1663 dma_addr_t offset = paddr & ~PAGE_MASK;
1664 dma_addr_t address, start, ret;
1665 unsigned int pages;
1666 unsigned long align_mask = 0;
1667 int i;
1668
1669 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1670 paddr &= PAGE_MASK;
1671
1672 INC_STATS_COUNTER(total_map_requests);
1673
1674 if (pages > 1)
1675 INC_STATS_COUNTER(cross_page);
1676
1677 if (align)
1678 align_mask = (1UL << get_order(size)) - 1;
1679
1680 retry:
1681 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1682 dma_mask);
1683 if (unlikely(address == DMA_ERROR_CODE)) {
1684 /*
1685 * setting next_address here will let the address
1686 * allocator only scan the new allocated range in the
1687 * first run. This is a small optimization.
1688 */
1689 dma_dom->next_address = dma_dom->aperture_size;
1690
1691 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1692 goto out;
1693
1694 /*
1695 * aperture was sucessfully enlarged by 128 MB, try
1696 * allocation again
1697 */
1698 goto retry;
1699 }
1700
1701 start = address;
1702 for (i = 0; i < pages; ++i) {
1703 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1704 if (ret == DMA_ERROR_CODE)
1705 goto out_unmap;
1706
1707 paddr += PAGE_SIZE;
1708 start += PAGE_SIZE;
1709 }
1710 address += offset;
1711
1712 ADD_STATS_COUNTER(alloced_io_mem, size);
1713
1714 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1715 iommu_flush_tlb(&dma_dom->domain);
1716 dma_dom->need_flush = false;
1717 } else if (unlikely(amd_iommu_np_cache))
1718 iommu_flush_pages(&dma_dom->domain, address, size);
1719
1720 out:
1721 return address;
1722
1723 out_unmap:
1724
1725 for (--i; i >= 0; --i) {
1726 start -= PAGE_SIZE;
1727 dma_ops_domain_unmap(dma_dom, start);
1728 }
1729
1730 dma_ops_free_addresses(dma_dom, address, pages);
1731
1732 return DMA_ERROR_CODE;
1733 }
1734
1735 /*
1736 * Does the reverse of the __map_single function. Must be called with
1737 * the domain lock held too
1738 */
1739 static void __unmap_single(struct dma_ops_domain *dma_dom,
1740 dma_addr_t dma_addr,
1741 size_t size,
1742 int dir)
1743 {
1744 dma_addr_t i, start;
1745 unsigned int pages;
1746
1747 if ((dma_addr == DMA_ERROR_CODE) ||
1748 (dma_addr + size > dma_dom->aperture_size))
1749 return;
1750
1751 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1752 dma_addr &= PAGE_MASK;
1753 start = dma_addr;
1754
1755 for (i = 0; i < pages; ++i) {
1756 dma_ops_domain_unmap(dma_dom, start);
1757 start += PAGE_SIZE;
1758 }
1759
1760 SUB_STATS_COUNTER(alloced_io_mem, size);
1761
1762 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1763
1764 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1765 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1766 dma_dom->need_flush = false;
1767 }
1768 }
1769
1770 /*
1771 * The exported map_single function for dma_ops.
1772 */
1773 static dma_addr_t map_page(struct device *dev, struct page *page,
1774 unsigned long offset, size_t size,
1775 enum dma_data_direction dir,
1776 struct dma_attrs *attrs)
1777 {
1778 unsigned long flags;
1779 struct protection_domain *domain;
1780 u16 devid;
1781 dma_addr_t addr;
1782 u64 dma_mask;
1783 phys_addr_t paddr = page_to_phys(page) + offset;
1784
1785 INC_STATS_COUNTER(cnt_map_single);
1786
1787 if (!get_device_resources(dev, &domain, &devid))
1788 /* device not handled by any AMD IOMMU */
1789 return (dma_addr_t)paddr;
1790
1791 dma_mask = *dev->dma_mask;
1792
1793 if (!dma_ops_domain(domain))
1794 return DMA_ERROR_CODE;
1795
1796 spin_lock_irqsave(&domain->lock, flags);
1797 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1798 dma_mask);
1799 if (addr == DMA_ERROR_CODE)
1800 goto out;
1801
1802 iommu_flush_complete(domain);
1803
1804 out:
1805 spin_unlock_irqrestore(&domain->lock, flags);
1806
1807 return addr;
1808 }
1809
1810 /*
1811 * The exported unmap_single function for dma_ops.
1812 */
1813 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1814 enum dma_data_direction dir, struct dma_attrs *attrs)
1815 {
1816 unsigned long flags;
1817 struct protection_domain *domain;
1818 u16 devid;
1819
1820 INC_STATS_COUNTER(cnt_unmap_single);
1821
1822 if (!get_device_resources(dev, &domain, &devid))
1823 /* device not handled by any AMD IOMMU */
1824 return;
1825
1826 if (!dma_ops_domain(domain))
1827 return;
1828
1829 spin_lock_irqsave(&domain->lock, flags);
1830
1831 __unmap_single(domain->priv, dma_addr, size, dir);
1832
1833 iommu_flush_complete(domain);
1834
1835 spin_unlock_irqrestore(&domain->lock, flags);
1836 }
1837
1838 /*
1839 * This is a special map_sg function which is used if we should map a
1840 * device which is not handled by an AMD IOMMU in the system.
1841 */
1842 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1843 int nelems, int dir)
1844 {
1845 struct scatterlist *s;
1846 int i;
1847
1848 for_each_sg(sglist, s, nelems, i) {
1849 s->dma_address = (dma_addr_t)sg_phys(s);
1850 s->dma_length = s->length;
1851 }
1852
1853 return nelems;
1854 }
1855
1856 /*
1857 * The exported map_sg function for dma_ops (handles scatter-gather
1858 * lists).
1859 */
1860 static int map_sg(struct device *dev, struct scatterlist *sglist,
1861 int nelems, enum dma_data_direction dir,
1862 struct dma_attrs *attrs)
1863 {
1864 unsigned long flags;
1865 struct protection_domain *domain;
1866 u16 devid;
1867 int i;
1868 struct scatterlist *s;
1869 phys_addr_t paddr;
1870 int mapped_elems = 0;
1871 u64 dma_mask;
1872
1873 INC_STATS_COUNTER(cnt_map_sg);
1874
1875 if (!get_device_resources(dev, &domain, &devid))
1876 return map_sg_no_iommu(dev, sglist, nelems, dir);
1877
1878 dma_mask = *dev->dma_mask;
1879
1880 if (!dma_ops_domain(domain))
1881 return 0;
1882
1883 spin_lock_irqsave(&domain->lock, flags);
1884
1885 for_each_sg(sglist, s, nelems, i) {
1886 paddr = sg_phys(s);
1887
1888 s->dma_address = __map_single(dev, domain->priv,
1889 paddr, s->length, dir, false,
1890 dma_mask);
1891
1892 if (s->dma_address) {
1893 s->dma_length = s->length;
1894 mapped_elems++;
1895 } else
1896 goto unmap;
1897 }
1898
1899 iommu_flush_complete(domain);
1900
1901 out:
1902 spin_unlock_irqrestore(&domain->lock, flags);
1903
1904 return mapped_elems;
1905 unmap:
1906 for_each_sg(sglist, s, mapped_elems, i) {
1907 if (s->dma_address)
1908 __unmap_single(domain->priv, s->dma_address,
1909 s->dma_length, dir);
1910 s->dma_address = s->dma_length = 0;
1911 }
1912
1913 mapped_elems = 0;
1914
1915 goto out;
1916 }
1917
1918 /*
1919 * The exported map_sg function for dma_ops (handles scatter-gather
1920 * lists).
1921 */
1922 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1923 int nelems, enum dma_data_direction dir,
1924 struct dma_attrs *attrs)
1925 {
1926 unsigned long flags;
1927 struct protection_domain *domain;
1928 struct scatterlist *s;
1929 u16 devid;
1930 int i;
1931
1932 INC_STATS_COUNTER(cnt_unmap_sg);
1933
1934 if (!get_device_resources(dev, &domain, &devid))
1935 return;
1936
1937 if (!dma_ops_domain(domain))
1938 return;
1939
1940 spin_lock_irqsave(&domain->lock, flags);
1941
1942 for_each_sg(sglist, s, nelems, i) {
1943 __unmap_single(domain->priv, s->dma_address,
1944 s->dma_length, dir);
1945 s->dma_address = s->dma_length = 0;
1946 }
1947
1948 iommu_flush_complete(domain);
1949
1950 spin_unlock_irqrestore(&domain->lock, flags);
1951 }
1952
1953 /*
1954 * The exported alloc_coherent function for dma_ops.
1955 */
1956 static void *alloc_coherent(struct device *dev, size_t size,
1957 dma_addr_t *dma_addr, gfp_t flag)
1958 {
1959 unsigned long flags;
1960 void *virt_addr;
1961 struct protection_domain *domain;
1962 u16 devid;
1963 phys_addr_t paddr;
1964 u64 dma_mask = dev->coherent_dma_mask;
1965
1966 INC_STATS_COUNTER(cnt_alloc_coherent);
1967
1968 if (!get_device_resources(dev, &domain, &devid)) {
1969 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1970 *dma_addr = __pa(virt_addr);
1971 return virt_addr;
1972 }
1973
1974 dma_mask = dev->coherent_dma_mask;
1975 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1976 flag |= __GFP_ZERO;
1977
1978 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1979 if (!virt_addr)
1980 return NULL;
1981
1982 paddr = virt_to_phys(virt_addr);
1983
1984 if (!dma_ops_domain(domain))
1985 goto out_free;
1986
1987 if (!dma_mask)
1988 dma_mask = *dev->dma_mask;
1989
1990 spin_lock_irqsave(&domain->lock, flags);
1991
1992 *dma_addr = __map_single(dev, domain->priv, paddr,
1993 size, DMA_BIDIRECTIONAL, true, dma_mask);
1994
1995 if (*dma_addr == DMA_ERROR_CODE) {
1996 spin_unlock_irqrestore(&domain->lock, flags);
1997 goto out_free;
1998 }
1999
2000 iommu_flush_complete(domain);
2001
2002 spin_unlock_irqrestore(&domain->lock, flags);
2003
2004 return virt_addr;
2005
2006 out_free:
2007
2008 free_pages((unsigned long)virt_addr, get_order(size));
2009
2010 return NULL;
2011 }
2012
2013 /*
2014 * The exported free_coherent function for dma_ops.
2015 */
2016 static void free_coherent(struct device *dev, size_t size,
2017 void *virt_addr, dma_addr_t dma_addr)
2018 {
2019 unsigned long flags;
2020 struct protection_domain *domain;
2021 u16 devid;
2022
2023 INC_STATS_COUNTER(cnt_free_coherent);
2024
2025 if (!get_device_resources(dev, &domain, &devid))
2026 goto free_mem;
2027
2028 if (!dma_ops_domain(domain))
2029 goto free_mem;
2030
2031 spin_lock_irqsave(&domain->lock, flags);
2032
2033 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2034
2035 iommu_flush_complete(domain);
2036
2037 spin_unlock_irqrestore(&domain->lock, flags);
2038
2039 free_mem:
2040 free_pages((unsigned long)virt_addr, get_order(size));
2041 }
2042
2043 /*
2044 * This function is called by the DMA layer to find out if we can handle a
2045 * particular device. It is part of the dma_ops.
2046 */
2047 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2048 {
2049 return check_device(dev);
2050 }
2051
2052 /*
2053 * The function for pre-allocating protection domains.
2054 *
2055 * If the driver core informs the DMA layer if a driver grabs a device
2056 * we don't need to preallocate the protection domains anymore.
2057 * For now we have to.
2058 */
2059 static void prealloc_protection_domains(void)
2060 {
2061 struct pci_dev *dev = NULL;
2062 struct dma_ops_domain *dma_dom;
2063 struct amd_iommu *iommu;
2064 u16 devid, __devid;
2065
2066 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2067 __devid = devid = calc_devid(dev->bus->number, dev->devfn);
2068 if (devid > amd_iommu_last_bdf)
2069 continue;
2070 devid = amd_iommu_alias_table[devid];
2071 if (domain_for_device(devid))
2072 continue;
2073 iommu = amd_iommu_rlookup_table[devid];
2074 if (!iommu)
2075 continue;
2076 dma_dom = dma_ops_domain_alloc(iommu);
2077 if (!dma_dom)
2078 continue;
2079 init_unity_mappings_for_device(dma_dom, devid);
2080 dma_dom->target_dev = devid;
2081
2082 attach_device(iommu, &dma_dom->domain, devid);
2083 if (__devid != devid)
2084 attach_device(iommu, &dma_dom->domain, __devid);
2085
2086 list_add_tail(&dma_dom->list, &iommu_pd_list);
2087 }
2088 }
2089
2090 static struct dma_map_ops amd_iommu_dma_ops = {
2091 .alloc_coherent = alloc_coherent,
2092 .free_coherent = free_coherent,
2093 .map_page = map_page,
2094 .unmap_page = unmap_page,
2095 .map_sg = map_sg,
2096 .unmap_sg = unmap_sg,
2097 .dma_supported = amd_iommu_dma_supported,
2098 };
2099
2100 /*
2101 * The function which clues the AMD IOMMU driver into dma_ops.
2102 */
2103 int __init amd_iommu_init_dma_ops(void)
2104 {
2105 struct amd_iommu *iommu;
2106 int ret;
2107
2108 /*
2109 * first allocate a default protection domain for every IOMMU we
2110 * found in the system. Devices not assigned to any other
2111 * protection domain will be assigned to the default one.
2112 */
2113 for_each_iommu(iommu) {
2114 iommu->default_dom = dma_ops_domain_alloc(iommu);
2115 if (iommu->default_dom == NULL)
2116 return -ENOMEM;
2117 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2118 ret = iommu_init_unity_mappings(iommu);
2119 if (ret)
2120 goto free_domains;
2121 }
2122
2123 /*
2124 * If device isolation is enabled, pre-allocate the protection
2125 * domains for each device.
2126 */
2127 if (amd_iommu_isolate)
2128 prealloc_protection_domains();
2129
2130 iommu_detected = 1;
2131 swiotlb = 0;
2132 #ifdef CONFIG_GART_IOMMU
2133 gart_iommu_aperture_disabled = 1;
2134 gart_iommu_aperture = 0;
2135 #endif
2136
2137 /* Make the driver finally visible to the drivers */
2138 dma_ops = &amd_iommu_dma_ops;
2139
2140 register_iommu(&amd_iommu_ops);
2141
2142 bus_register_notifier(&pci_bus_type, &device_nb);
2143
2144 amd_iommu_stats_init();
2145
2146 return 0;
2147
2148 free_domains:
2149
2150 for_each_iommu(iommu) {
2151 if (iommu->default_dom)
2152 dma_ops_domain_free(iommu->default_dom);
2153 }
2154
2155 return ret;
2156 }
2157
2158 /*****************************************************************************
2159 *
2160 * The following functions belong to the exported interface of AMD IOMMU
2161 *
2162 * This interface allows access to lower level functions of the IOMMU
2163 * like protection domain handling and assignement of devices to domains
2164 * which is not possible with the dma_ops interface.
2165 *
2166 *****************************************************************************/
2167
2168 static void cleanup_domain(struct protection_domain *domain)
2169 {
2170 unsigned long flags;
2171 u16 devid;
2172
2173 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2174
2175 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2176 if (amd_iommu_pd_table[devid] == domain)
2177 __detach_device(domain, devid);
2178
2179 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2180 }
2181
2182 static void protection_domain_free(struct protection_domain *domain)
2183 {
2184 if (!domain)
2185 return;
2186
2187 del_domain_from_list(domain);
2188
2189 if (domain->id)
2190 domain_id_free(domain->id);
2191
2192 kfree(domain);
2193 }
2194
2195 static struct protection_domain *protection_domain_alloc(void)
2196 {
2197 struct protection_domain *domain;
2198
2199 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2200 if (!domain)
2201 return NULL;
2202
2203 spin_lock_init(&domain->lock);
2204 domain->id = domain_id_alloc();
2205 if (!domain->id)
2206 goto out_err;
2207
2208 add_domain_to_list(domain);
2209
2210 return domain;
2211
2212 out_err:
2213 kfree(domain);
2214
2215 return NULL;
2216 }
2217
2218 static int amd_iommu_domain_init(struct iommu_domain *dom)
2219 {
2220 struct protection_domain *domain;
2221
2222 domain = protection_domain_alloc();
2223 if (!domain)
2224 goto out_free;
2225
2226 domain->mode = PAGE_MODE_3_LEVEL;
2227 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2228 if (!domain->pt_root)
2229 goto out_free;
2230
2231 dom->priv = domain;
2232
2233 return 0;
2234
2235 out_free:
2236 protection_domain_free(domain);
2237
2238 return -ENOMEM;
2239 }
2240
2241 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2242 {
2243 struct protection_domain *domain = dom->priv;
2244
2245 if (!domain)
2246 return;
2247
2248 if (domain->dev_cnt > 0)
2249 cleanup_domain(domain);
2250
2251 BUG_ON(domain->dev_cnt != 0);
2252
2253 free_pagetable(domain);
2254
2255 domain_id_free(domain->id);
2256
2257 kfree(domain);
2258
2259 dom->priv = NULL;
2260 }
2261
2262 static void amd_iommu_detach_device(struct iommu_domain *dom,
2263 struct device *dev)
2264 {
2265 struct protection_domain *domain = dom->priv;
2266 struct amd_iommu *iommu;
2267 struct pci_dev *pdev;
2268 u16 devid;
2269
2270 if (dev->bus != &pci_bus_type)
2271 return;
2272
2273 pdev = to_pci_dev(dev);
2274
2275 devid = calc_devid(pdev->bus->number, pdev->devfn);
2276
2277 if (devid > 0)
2278 detach_device(domain, devid);
2279
2280 iommu = amd_iommu_rlookup_table[devid];
2281 if (!iommu)
2282 return;
2283
2284 iommu_queue_inv_dev_entry(iommu, devid);
2285 iommu_completion_wait(iommu);
2286 }
2287
2288 static int amd_iommu_attach_device(struct iommu_domain *dom,
2289 struct device *dev)
2290 {
2291 struct protection_domain *domain = dom->priv;
2292 struct protection_domain *old_domain;
2293 struct amd_iommu *iommu;
2294 struct pci_dev *pdev;
2295 u16 devid;
2296
2297 if (dev->bus != &pci_bus_type)
2298 return -EINVAL;
2299
2300 pdev = to_pci_dev(dev);
2301
2302 devid = calc_devid(pdev->bus->number, pdev->devfn);
2303
2304 if (devid >= amd_iommu_last_bdf ||
2305 devid != amd_iommu_alias_table[devid])
2306 return -EINVAL;
2307
2308 iommu = amd_iommu_rlookup_table[devid];
2309 if (!iommu)
2310 return -EINVAL;
2311
2312 old_domain = domain_for_device(devid);
2313 if (old_domain)
2314 detach_device(old_domain, devid);
2315
2316 attach_device(iommu, domain, devid);
2317
2318 iommu_completion_wait(iommu);
2319
2320 return 0;
2321 }
2322
2323 static int amd_iommu_map_range(struct iommu_domain *dom,
2324 unsigned long iova, phys_addr_t paddr,
2325 size_t size, int iommu_prot)
2326 {
2327 struct protection_domain *domain = dom->priv;
2328 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2329 int prot = 0;
2330 int ret;
2331
2332 if (iommu_prot & IOMMU_READ)
2333 prot |= IOMMU_PROT_IR;
2334 if (iommu_prot & IOMMU_WRITE)
2335 prot |= IOMMU_PROT_IW;
2336
2337 iova &= PAGE_MASK;
2338 paddr &= PAGE_MASK;
2339
2340 for (i = 0; i < npages; ++i) {
2341 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2342 if (ret)
2343 return ret;
2344
2345 iova += PAGE_SIZE;
2346 paddr += PAGE_SIZE;
2347 }
2348
2349 return 0;
2350 }
2351
2352 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2353 unsigned long iova, size_t size)
2354 {
2355
2356 struct protection_domain *domain = dom->priv;
2357 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2358
2359 iova &= PAGE_MASK;
2360
2361 for (i = 0; i < npages; ++i) {
2362 iommu_unmap_page(domain, iova, PM_MAP_4k);
2363 iova += PAGE_SIZE;
2364 }
2365
2366 iommu_flush_tlb_pde(domain);
2367 }
2368
2369 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2370 unsigned long iova)
2371 {
2372 struct protection_domain *domain = dom->priv;
2373 unsigned long offset = iova & ~PAGE_MASK;
2374 phys_addr_t paddr;
2375 u64 *pte;
2376
2377 pte = fetch_pte(domain, iova, PM_MAP_4k);
2378
2379 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2380 return 0;
2381
2382 paddr = *pte & IOMMU_PAGE_MASK;
2383 paddr |= offset;
2384
2385 return paddr;
2386 }
2387
2388 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2389 unsigned long cap)
2390 {
2391 return 0;
2392 }
2393
2394 static struct iommu_ops amd_iommu_ops = {
2395 .domain_init = amd_iommu_domain_init,
2396 .domain_destroy = amd_iommu_domain_destroy,
2397 .attach_dev = amd_iommu_attach_device,
2398 .detach_dev = amd_iommu_detach_device,
2399 .map = amd_iommu_map_range,
2400 .unmap = amd_iommu_unmap_range,
2401 .iova_to_phys = amd_iommu_iova_to_phys,
2402 .domain_has_cap = amd_iommu_domain_has_cap,
2403 };
2404
2405 /*****************************************************************************
2406 *
2407 * The next functions do a basic initialization of IOMMU for pass through
2408 * mode
2409 *
2410 * In passthrough mode the IOMMU is initialized and enabled but not used for
2411 * DMA-API translation.
2412 *
2413 *****************************************************************************/
2414
2415 int __init amd_iommu_init_passthrough(void)
2416 {
2417 struct pci_dev *dev = NULL;
2418 u16 devid, devid2;
2419
2420 /* allocate passthroug domain */
2421 pt_domain = protection_domain_alloc();
2422 if (!pt_domain)
2423 return -ENOMEM;
2424
2425 pt_domain->mode |= PAGE_MODE_NONE;
2426
2427 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2428 struct amd_iommu *iommu;
2429
2430 devid = calc_devid(dev->bus->number, dev->devfn);
2431 if (devid > amd_iommu_last_bdf)
2432 continue;
2433
2434 devid2 = amd_iommu_alias_table[devid];
2435
2436 iommu = amd_iommu_rlookup_table[devid2];
2437 if (!iommu)
2438 continue;
2439
2440 __attach_device(iommu, pt_domain, devid);
2441 __attach_device(iommu, pt_domain, devid2);
2442 }
2443
2444 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2445
2446 return 0;
2447 }
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