2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
34 * definitions for the ACPI scanning code
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed
));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed
));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed
));
120 static int __initdata amd_iommu_detected
;
122 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
124 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
126 #ifdef CONFIG_IOMMU_STRESS
127 bool amd_iommu_isolate
= false;
129 bool amd_iommu_isolate
= true; /* if true, device isolation is
133 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
135 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
139 * Pointer to the device table which is shared by all AMD IOMMUs
140 * it is indexed by the PCI device id or the HT unit id and contains
141 * information about the domain the device belongs to as well as the
142 * page table root pointer.
144 struct dev_table_entry
*amd_iommu_dev_table
;
147 * The alias table is a driver specific data structure which contains the
148 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
149 * More than one device can share the same requestor id.
151 u16
*amd_iommu_alias_table
;
154 * The rlookup table is used to find the IOMMU which is responsible
155 * for a specific device. It is also indexed by the PCI device id.
157 struct amd_iommu
**amd_iommu_rlookup_table
;
160 * The pd table (protection domain table) is used to find the protection domain
161 * data structure a device belongs to. Indexed with the PCI device id too.
163 struct protection_domain
**amd_iommu_pd_table
;
166 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
167 * to know which ones are already in use.
169 unsigned long *amd_iommu_pd_alloc_bitmap
;
171 static u32 dev_table_size
; /* size of the device table */
172 static u32 alias_table_size
; /* size of the alias table */
173 static u32 rlookup_table_size
; /* size if the rlookup table */
175 static inline void update_last_devid(u16 devid
)
177 if (devid
> amd_iommu_last_bdf
)
178 amd_iommu_last_bdf
= devid
;
181 static inline unsigned long tbl_size(int entry_size
)
183 unsigned shift
= PAGE_SHIFT
+
184 get_order(((int)amd_iommu_last_bdf
+ 1) * entry_size
);
189 /****************************************************************************
191 * AMD IOMMU MMIO register space handling functions
193 * These functions are used to program the IOMMU device registers in
194 * MMIO space required for that driver.
196 ****************************************************************************/
199 * This function set the exclusion range in the IOMMU. DMA accesses to the
200 * exclusion range are passed through untranslated
202 static void iommu_set_exclusion_range(struct amd_iommu
*iommu
)
204 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
205 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
208 if (!iommu
->exclusion_start
)
211 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
212 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
213 &entry
, sizeof(entry
));
216 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
217 &entry
, sizeof(entry
));
220 /* Programs the physical address of the device table into the IOMMU hardware */
221 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
225 BUG_ON(iommu
->mmio_base
== NULL
);
227 entry
= virt_to_phys(amd_iommu_dev_table
);
228 entry
|= (dev_table_size
>> 12) - 1;
229 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
230 &entry
, sizeof(entry
));
233 /* Generic functions to enable/disable certain features of the IOMMU. */
234 static void iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
238 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
240 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
243 static void iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
247 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
249 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
252 /* Function to enable the hardware */
253 static void iommu_enable(struct amd_iommu
*iommu
)
255 printk(KERN_INFO
"AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
256 dev_name(&iommu
->dev
->dev
), iommu
->cap_ptr
);
258 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
261 static void iommu_disable(struct amd_iommu
*iommu
)
263 /* Disable command buffer */
264 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
266 /* Disable event logging and event interrupts */
267 iommu_feature_disable(iommu
, CONTROL_EVT_INT_EN
);
268 iommu_feature_disable(iommu
, CONTROL_EVT_LOG_EN
);
270 /* Disable IOMMU hardware itself */
271 iommu_feature_disable(iommu
, CONTROL_IOMMU_EN
);
275 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
276 * the system has one.
278 static u8
* __init
iommu_map_mmio_space(u64 address
)
282 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
285 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
289 release_mem_region(address
, MMIO_REGION_LENGTH
);
294 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
296 if (iommu
->mmio_base
)
297 iounmap(iommu
->mmio_base
);
298 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
301 /****************************************************************************
303 * The functions below belong to the first pass of AMD IOMMU ACPI table
304 * parsing. In this pass we try to find out the highest device id this
305 * code has to handle. Upon this information the size of the shared data
306 * structures is determined later.
308 ****************************************************************************/
311 * This function calculates the length of a given IVHD entry
313 static inline int ivhd_entry_length(u8
*ivhd
)
315 return 0x04 << (*ivhd
>> 6);
319 * This function reads the last device id the IOMMU has to handle from the PCI
320 * capability header for this IOMMU
322 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
326 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
327 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
333 * After reading the highest device id from the IOMMU PCI capability header
334 * this function looks if there is a higher device id defined in the ACPI table
336 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
338 u8
*p
= (void *)h
, *end
= (void *)h
;
339 struct ivhd_entry
*dev
;
344 find_last_devid_on_pci(PCI_BUS(h
->devid
),
350 dev
= (struct ivhd_entry
*)p
;
352 case IVHD_DEV_SELECT
:
353 case IVHD_DEV_RANGE_END
:
355 case IVHD_DEV_EXT_SELECT
:
356 /* all the above subfield types refer to device ids */
357 update_last_devid(dev
->devid
);
362 p
+= ivhd_entry_length(p
);
371 * Iterate over all IVHD entries in the ACPI table and find the highest device
372 * id which we need to handle. This is the first of three functions which parse
373 * the ACPI table. So we check the checksum here.
375 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
378 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
379 struct ivhd_header
*h
;
382 * Validate checksum here so we don't need to do it when
383 * we actually parse the table
385 for (i
= 0; i
< table
->length
; ++i
)
388 /* ACPI table corrupt */
391 p
+= IVRS_HEADER_LENGTH
;
393 end
+= table
->length
;
395 h
= (struct ivhd_header
*)p
;
398 find_last_devid_from_ivhd(h
);
410 /****************************************************************************
412 * The following functions belong the the code path which parses the ACPI table
413 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
414 * data structures, initialize the device/alias/rlookup table and also
415 * basically initialize the hardware.
417 ****************************************************************************/
420 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
421 * write commands to that buffer later and the IOMMU will execute them
424 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
426 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
427 get_order(CMD_BUFFER_SIZE
));
432 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
438 * This function resets the command buffer if the IOMMU stopped fetching
441 void amd_iommu_reset_cmd_buffer(struct amd_iommu
*iommu
)
443 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
445 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
446 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
448 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
452 * This function writes the command buffer address to the hardware and
455 static void iommu_enable_command_buffer(struct amd_iommu
*iommu
)
459 BUG_ON(iommu
->cmd_buf
== NULL
);
461 entry
= (u64
)virt_to_phys(iommu
->cmd_buf
);
462 entry
|= MMIO_CMD_SIZE_512
;
464 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
465 &entry
, sizeof(entry
));
467 amd_iommu_reset_cmd_buffer(iommu
);
470 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
472 free_pages((unsigned long)iommu
->cmd_buf
,
473 get_order(iommu
->cmd_buf_size
));
476 /* allocates the memory where the IOMMU will log its events to */
477 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
479 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
480 get_order(EVT_BUFFER_SIZE
));
482 if (iommu
->evt_buf
== NULL
)
485 iommu
->evt_buf_size
= EVT_BUFFER_SIZE
;
487 return iommu
->evt_buf
;
490 static void iommu_enable_event_buffer(struct amd_iommu
*iommu
)
494 BUG_ON(iommu
->evt_buf
== NULL
);
496 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
498 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
499 &entry
, sizeof(entry
));
501 /* set head and tail to zero manually */
502 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
503 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
505 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
508 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
510 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
513 /* sets a specific bit in the device table entry. */
514 static void set_dev_entry_bit(u16 devid
, u8 bit
)
516 int i
= (bit
>> 5) & 0x07;
517 int _bit
= bit
& 0x1f;
519 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
522 static int get_dev_entry_bit(u16 devid
, u8 bit
)
524 int i
= (bit
>> 5) & 0x07;
525 int _bit
= bit
& 0x1f;
527 return (amd_iommu_dev_table
[devid
].data
[i
] & (1 << _bit
)) >> _bit
;
531 void amd_iommu_apply_erratum_63(u16 devid
)
535 sysmgt
= get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
) |
536 (get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
) << 1);
539 set_dev_entry_bit(devid
, DEV_ENTRY_IW
);
542 /* Writes the specific IOMMU for a device into the rlookup table */
543 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
545 amd_iommu_rlookup_table
[devid
] = iommu
;
549 * This function takes the device specific flags read from the ACPI
550 * table and sets up the device table entry with that information
552 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
553 u16 devid
, u32 flags
, u32 ext_flags
)
555 if (flags
& ACPI_DEVFLAG_INITPASS
)
556 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
557 if (flags
& ACPI_DEVFLAG_EXTINT
)
558 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
559 if (flags
& ACPI_DEVFLAG_NMI
)
560 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
561 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
562 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
563 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
564 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
565 if (flags
& ACPI_DEVFLAG_LINT0
)
566 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
567 if (flags
& ACPI_DEVFLAG_LINT1
)
568 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
570 amd_iommu_apply_erratum_63(devid
);
572 set_iommu_for_device(iommu
, devid
);
576 * Reads the device exclusion range from ACPI and initialize IOMMU with
579 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
581 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
583 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
588 * We only can configure exclusion ranges per IOMMU, not
589 * per device. But we can enable the exclusion range per
590 * device. This is done here
592 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
593 iommu
->exclusion_start
= m
->range_start
;
594 iommu
->exclusion_length
= m
->range_length
;
599 * This function reads some important data from the IOMMU PCI space and
600 * initializes the driver data structure with it. It reads the hardware
601 * capabilities and the first/last device entries
603 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
605 int cap_ptr
= iommu
->cap_ptr
;
608 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
610 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
612 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
615 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
617 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
619 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
623 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
624 * initializes the hardware and our data structures with it.
626 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
627 struct ivhd_header
*h
)
630 u8
*end
= p
, flags
= 0;
631 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
634 struct ivhd_entry
*e
;
637 * First set the recommended feature enable bits from ACPI
638 * into the IOMMU control registers
640 h
->flags
& IVHD_FLAG_HT_TUN_EN_MASK
?
641 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
642 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
644 h
->flags
& IVHD_FLAG_PASSPW_EN_MASK
?
645 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
646 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
648 h
->flags
& IVHD_FLAG_RESPASSPW_EN_MASK
?
649 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
650 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
652 h
->flags
& IVHD_FLAG_ISOC_EN_MASK
?
653 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
654 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
657 * make IOMMU memory accesses cache coherent
659 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
662 * Done. Now parse the device entries
664 p
+= sizeof(struct ivhd_header
);
669 e
= (struct ivhd_entry
*)p
;
673 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
674 " last device %02x:%02x.%x flags: %02x\n",
675 PCI_BUS(iommu
->first_device
),
676 PCI_SLOT(iommu
->first_device
),
677 PCI_FUNC(iommu
->first_device
),
678 PCI_BUS(iommu
->last_device
),
679 PCI_SLOT(iommu
->last_device
),
680 PCI_FUNC(iommu
->last_device
),
683 for (dev_i
= iommu
->first_device
;
684 dev_i
<= iommu
->last_device
; ++dev_i
)
685 set_dev_entry_from_acpi(iommu
, dev_i
,
688 case IVHD_DEV_SELECT
:
690 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
698 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
700 case IVHD_DEV_SELECT_RANGE_START
:
702 DUMP_printk(" DEV_SELECT_RANGE_START\t "
703 "devid: %02x:%02x.%x flags: %02x\n",
709 devid_start
= e
->devid
;
716 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
717 "flags: %02x devid_to: %02x:%02x.%x\n",
722 PCI_BUS(e
->ext
>> 8),
723 PCI_SLOT(e
->ext
>> 8),
724 PCI_FUNC(e
->ext
>> 8));
727 devid_to
= e
->ext
>> 8;
728 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
729 set_dev_entry_from_acpi(iommu
, devid_to
, e
->flags
, 0);
730 amd_iommu_alias_table
[devid
] = devid_to
;
732 case IVHD_DEV_ALIAS_RANGE
:
734 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
735 "devid: %02x:%02x.%x flags: %02x "
736 "devid_to: %02x:%02x.%x\n",
741 PCI_BUS(e
->ext
>> 8),
742 PCI_SLOT(e
->ext
>> 8),
743 PCI_FUNC(e
->ext
>> 8));
745 devid_start
= e
->devid
;
747 devid_to
= e
->ext
>> 8;
751 case IVHD_DEV_EXT_SELECT
:
753 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
754 "flags: %02x ext: %08x\n",
761 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
764 case IVHD_DEV_EXT_SELECT_RANGE
:
766 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
767 "%02x:%02x.%x flags: %02x ext: %08x\n",
773 devid_start
= e
->devid
;
778 case IVHD_DEV_RANGE_END
:
780 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
786 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
788 amd_iommu_alias_table
[dev_i
] = devid_to
;
789 set_dev_entry_from_acpi(iommu
,
790 devid_to
, flags
, ext_flags
);
792 set_dev_entry_from_acpi(iommu
, dev_i
,
800 p
+= ivhd_entry_length(p
);
804 /* Initializes the device->iommu mapping for the driver */
805 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
809 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
810 set_iommu_for_device(iommu
, i
);
815 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
817 free_command_buffer(iommu
);
818 free_event_buffer(iommu
);
819 iommu_unmap_mmio_space(iommu
);
822 static void __init
free_iommu_all(void)
824 struct amd_iommu
*iommu
, *next
;
826 for_each_iommu_safe(iommu
, next
) {
827 list_del(&iommu
->list
);
828 free_iommu_one(iommu
);
834 * This function clues the initialization function for one IOMMU
835 * together and also allocates the command buffer and programs the
836 * hardware. It does NOT enable the IOMMU. This is done afterwards.
838 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
840 spin_lock_init(&iommu
->lock
);
841 list_add_tail(&iommu
->list
, &amd_iommu_list
);
844 * Copy data from ACPI table entry to the iommu struct
846 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
850 iommu
->cap_ptr
= h
->cap_ptr
;
851 iommu
->pci_seg
= h
->pci_seg
;
852 iommu
->mmio_phys
= h
->mmio_phys
;
853 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
854 if (!iommu
->mmio_base
)
857 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
861 iommu
->evt_buf
= alloc_event_buffer(iommu
);
865 iommu
->int_enabled
= false;
867 init_iommu_from_pci(iommu
);
868 init_iommu_from_acpi(iommu
, h
);
869 init_iommu_devices(iommu
);
871 return pci_enable_device(iommu
->dev
);
875 * Iterates over all IOMMU entries in the ACPI table, allocates the
876 * IOMMU structure and initializes it with init_iommu_one()
878 static int __init
init_iommu_all(struct acpi_table_header
*table
)
880 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
881 struct ivhd_header
*h
;
882 struct amd_iommu
*iommu
;
885 end
+= table
->length
;
886 p
+= IVRS_HEADER_LENGTH
;
889 h
= (struct ivhd_header
*)p
;
893 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
894 "seg: %d flags: %01x info %04x\n",
895 PCI_BUS(h
->devid
), PCI_SLOT(h
->devid
),
896 PCI_FUNC(h
->devid
), h
->cap_ptr
,
897 h
->pci_seg
, h
->flags
, h
->info
);
898 DUMP_printk(" mmio-addr: %016llx\n",
901 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
904 ret
= init_iommu_one(iommu
, h
);
919 /****************************************************************************
921 * The following functions initialize the MSI interrupts for all IOMMUs
922 * in the system. Its a bit challenging because there could be multiple
923 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
926 ****************************************************************************/
928 static int __init
iommu_setup_msi(struct amd_iommu
*iommu
)
932 if (pci_enable_msi(iommu
->dev
))
935 r
= request_irq(iommu
->dev
->irq
, amd_iommu_int_handler
,
941 pci_disable_msi(iommu
->dev
);
945 iommu
->int_enabled
= true;
946 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
951 static int iommu_init_msi(struct amd_iommu
*iommu
)
953 if (iommu
->int_enabled
)
956 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
957 return iommu_setup_msi(iommu
);
962 /****************************************************************************
964 * The next functions belong to the third pass of parsing the ACPI
965 * table. In this last pass the memory mapping requirements are
966 * gathered (like exclusion and unity mapping reanges).
968 ****************************************************************************/
970 static void __init
free_unity_maps(void)
972 struct unity_map_entry
*entry
, *next
;
974 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
975 list_del(&entry
->list
);
980 /* called when we find an exclusion range definition in ACPI */
981 static int __init
init_exclusion_range(struct ivmd_header
*m
)
987 set_device_exclusion_range(m
->devid
, m
);
989 case ACPI_IVMD_TYPE_ALL
:
990 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
991 set_device_exclusion_range(i
, m
);
993 case ACPI_IVMD_TYPE_RANGE
:
994 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
995 set_device_exclusion_range(i
, m
);
1004 /* called for unity map ACPI definition */
1005 static int __init
init_unity_map_range(struct ivmd_header
*m
)
1007 struct unity_map_entry
*e
= 0;
1010 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
1018 case ACPI_IVMD_TYPE
:
1019 s
= "IVMD_TYPEi\t\t\t";
1020 e
->devid_start
= e
->devid_end
= m
->devid
;
1022 case ACPI_IVMD_TYPE_ALL
:
1023 s
= "IVMD_TYPE_ALL\t\t";
1025 e
->devid_end
= amd_iommu_last_bdf
;
1027 case ACPI_IVMD_TYPE_RANGE
:
1028 s
= "IVMD_TYPE_RANGE\t\t";
1029 e
->devid_start
= m
->devid
;
1030 e
->devid_end
= m
->aux
;
1033 e
->address_start
= PAGE_ALIGN(m
->range_start
);
1034 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
1035 e
->prot
= m
->flags
>> 1;
1037 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1038 " range_start: %016llx range_end: %016llx flags: %x\n", s
,
1039 PCI_BUS(e
->devid_start
), PCI_SLOT(e
->devid_start
),
1040 PCI_FUNC(e
->devid_start
), PCI_BUS(e
->devid_end
),
1041 PCI_SLOT(e
->devid_end
), PCI_FUNC(e
->devid_end
),
1042 e
->address_start
, e
->address_end
, m
->flags
);
1044 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
1049 /* iterates over all memory definitions we find in the ACPI table */
1050 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
1052 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
1053 struct ivmd_header
*m
;
1055 end
+= table
->length
;
1056 p
+= IVRS_HEADER_LENGTH
;
1059 m
= (struct ivmd_header
*)p
;
1060 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
1061 init_exclusion_range(m
);
1062 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
1063 init_unity_map_range(m
);
1072 * Init the device table to not allow DMA access for devices and
1073 * suppress all page faults
1075 static void init_device_table(void)
1079 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
1080 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
1081 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
1086 * This function finally enables all IOMMUs found in the system after
1087 * they have been initialized
1089 static void enable_iommus(void)
1091 struct amd_iommu
*iommu
;
1093 for_each_iommu(iommu
) {
1094 iommu_disable(iommu
);
1095 iommu_set_device_table(iommu
);
1096 iommu_enable_command_buffer(iommu
);
1097 iommu_enable_event_buffer(iommu
);
1098 iommu_set_exclusion_range(iommu
);
1099 iommu_init_msi(iommu
);
1100 iommu_enable(iommu
);
1104 static void disable_iommus(void)
1106 struct amd_iommu
*iommu
;
1108 for_each_iommu(iommu
)
1109 iommu_disable(iommu
);
1113 * Suspend/Resume support
1114 * disable suspend until real resume implemented
1117 static int amd_iommu_resume(struct sys_device
*dev
)
1119 /* re-load the hardware */
1123 * we have to flush after the IOMMUs are enabled because a
1124 * disabled IOMMU will never execute the commands we send
1126 amd_iommu_flush_all_devices();
1127 amd_iommu_flush_all_domains();
1132 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
1134 /* disable IOMMUs to go out of the way for BIOS */
1140 static struct sysdev_class amd_iommu_sysdev_class
= {
1141 .name
= "amd_iommu",
1142 .suspend
= amd_iommu_suspend
,
1143 .resume
= amd_iommu_resume
,
1146 static struct sys_device device_amd_iommu
= {
1148 .cls
= &amd_iommu_sysdev_class
,
1152 * This is the core init function for AMD IOMMU hardware in the system.
1153 * This function is called from the generic x86 DMA layer initialization
1156 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1159 * 1 pass) Find the highest PCI device id the driver has to handle.
1160 * Upon this information the size of the data structures is
1161 * determined that needs to be allocated.
1163 * 2 pass) Initialize the data structures just allocated with the
1164 * information in the ACPI table about available AMD IOMMUs
1165 * in the system. It also maps the PCI devices in the
1166 * system to specific IOMMUs
1168 * 3 pass) After the basic data structures are allocated and
1169 * initialized we update them with information about memory
1170 * remapping requirements parsed out of the ACPI table in
1173 * After that the hardware is initialized and ready to go. In the last
1174 * step we do some Linux specific things like registering the driver in
1175 * the dma_ops interface and initializing the suspend/resume support
1176 * functions. Finally it prints some information about AMD IOMMUs and
1177 * the driver state and enables the hardware.
1179 int __init
amd_iommu_init(void)
1185 printk(KERN_INFO
"AMD-Vi disabled by kernel command line\n");
1189 if (!amd_iommu_detected
)
1193 * First parse ACPI tables to find the largest Bus/Dev/Func
1194 * we need to handle. Upon this information the shared data
1195 * structures for the IOMMUs in the system will be allocated
1197 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1200 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1201 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1202 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1206 /* Device table - directly used by all IOMMUs */
1207 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1208 get_order(dev_table_size
));
1209 if (amd_iommu_dev_table
== NULL
)
1213 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1214 * IOMMU see for that device
1216 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1217 get_order(alias_table_size
));
1218 if (amd_iommu_alias_table
== NULL
)
1221 /* IOMMU rlookup table - find the IOMMU for a specific device */
1222 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1223 GFP_KERNEL
| __GFP_ZERO
,
1224 get_order(rlookup_table_size
));
1225 if (amd_iommu_rlookup_table
== NULL
)
1229 * Protection Domain table - maps devices to protection domains
1230 * This table has the same size as the rlookup_table
1232 amd_iommu_pd_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1233 get_order(rlookup_table_size
));
1234 if (amd_iommu_pd_table
== NULL
)
1237 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1238 GFP_KERNEL
| __GFP_ZERO
,
1239 get_order(MAX_DOMAIN_ID
/8));
1240 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1243 /* init the device table */
1244 init_device_table();
1247 * let all alias entries point to itself
1249 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1250 amd_iommu_alias_table
[i
] = i
;
1253 * never allocate domain 0 because its used as the non-allocated and
1254 * error value placeholder
1256 amd_iommu_pd_alloc_bitmap
[0] = 1;
1259 * now the data structures are allocated and basically initialized
1260 * start the real acpi table scan
1263 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1266 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1269 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
1273 ret
= sysdev_register(&device_amd_iommu
);
1277 if (iommu_pass_through
)
1278 ret
= amd_iommu_init_passthrough();
1280 ret
= amd_iommu_init_dma_ops();
1286 if (iommu_pass_through
)
1289 printk(KERN_INFO
"AMD-Vi: device isolation ");
1290 if (amd_iommu_isolate
)
1291 printk("enabled\n");
1293 printk("disabled\n");
1295 if (amd_iommu_unmap_flush
)
1296 printk(KERN_INFO
"AMD-Vi: IO/TLB flush on unmap enabled\n");
1298 printk(KERN_INFO
"AMD-Vi: Lazy IO/TLB flushing enabled\n");
1304 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1305 get_order(MAX_DOMAIN_ID
/8));
1307 free_pages((unsigned long)amd_iommu_pd_table
,
1308 get_order(rlookup_table_size
));
1310 free_pages((unsigned long)amd_iommu_rlookup_table
,
1311 get_order(rlookup_table_size
));
1313 free_pages((unsigned long)amd_iommu_alias_table
,
1314 get_order(alias_table_size
));
1316 free_pages((unsigned long)amd_iommu_dev_table
,
1317 get_order(dev_table_size
));
1326 void amd_iommu_shutdown(void)
1331 /****************************************************************************
1333 * Early detect code. This code runs at IOMMU detection time in the DMA
1334 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1337 ****************************************************************************/
1338 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1343 void __init
amd_iommu_detect(void)
1345 if (swiotlb
|| no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1348 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1350 amd_iommu_detected
= 1;
1351 #ifdef CONFIG_GART_IOMMU
1352 gart_iommu_aperture_disabled
= 1;
1353 gart_iommu_aperture
= 0;
1358 /****************************************************************************
1360 * Parsing functions for the AMD IOMMU specific kernel command line
1363 ****************************************************************************/
1365 static int __init
parse_amd_iommu_dump(char *str
)
1367 amd_iommu_dump
= true;
1372 static int __init
parse_amd_iommu_options(char *str
)
1374 for (; *str
; ++str
) {
1375 if (strncmp(str
, "isolate", 7) == 0)
1376 amd_iommu_isolate
= true;
1377 if (strncmp(str
, "share", 5) == 0)
1378 amd_iommu_isolate
= false;
1379 if (strncmp(str
, "fullflush", 9) == 0)
1380 amd_iommu_unmap_flush
= true;
1386 __setup("amd_iommu_dump", parse_amd_iommu_dump
);
1387 __setup("amd_iommu=", parse_amd_iommu_options
);