1 // SPDX-License-Identifier: GPL-2.0
3 * Firmware replacement code.
5 * Work around broken BIOSes that don't set an aperture, only set the
6 * aperture in the AGP bridge, or set too small aperture.
8 * If all fails map the aperture over some low memory. This is cheaper than
9 * doing bounce buffering. The memory is lost. This is done at early boot
10 * because only the bootmem allocator can allocate 32+MB.
12 * Copyright 2002 Andi Kleen, SuSE Labs.
14 #define pr_fmt(fmt) "AGP: " fmt
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/memblock.h>
20 #include <linux/mmzone.h>
21 #include <linux/pci_ids.h>
22 #include <linux/pci.h>
23 #include <linux/bitops.h>
24 #include <linux/suspend.h>
25 #include <asm/e820/api.h>
27 #include <asm/iommu.h>
29 #include <asm/pci-direct.h>
31 #include <asm/amd_nb.h>
32 #include <asm/x86_init.h>
35 * Using 512M as goal, in case kexec will load kernel_big
36 * that will do the on-position decompress, and could overlap with
37 * with the gart aperture that is used.
40 * ==> kexec (with kdump trigger path or gart still enabled)
41 * ==> kernel_small (gart area become e820_reserved)
42 * ==> kexec (with kdump trigger path or gart still enabled)
43 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
44 * So don't use 512M below as gart iommu, leave the space for kernel
47 #define GART_MIN_ADDR (512ULL << 20)
48 #define GART_MAX_ADDR (1ULL << 32)
50 int gart_iommu_aperture
;
51 int gart_iommu_aperture_disabled __initdata
;
52 int gart_iommu_aperture_allowed __initdata
;
54 int fallback_aper_order __initdata
= 1; /* 64MB */
55 int fallback_aper_force __initdata
;
57 int fix_aperture __initdata
= 1;
59 /* This code runs before the PCI subsystem is initialized, so just
60 access the northbridge directly. */
62 static u32 __init
allocate_aperture(void)
67 /* aper_size should <= 1G */
68 if (fallback_aper_order
> 5)
69 fallback_aper_order
= 5;
70 aper_size
= (32 * 1024 * 1024) << fallback_aper_order
;
73 * Aperture has to be naturally aligned. This means a 2GB aperture
74 * won't have much chance of finding a place in the lower 4GB of
75 * memory. Unfortunately we cannot move it up because that would
76 * make the IOMMU useless.
78 addr
= memblock_find_in_range(GART_MIN_ADDR
, GART_MAX_ADDR
,
79 aper_size
, aper_size
);
81 pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n",
82 addr
, addr
+ aper_size
- 1, aper_size
>> 10);
85 memblock_reserve(addr
, aper_size
);
86 pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n",
87 addr
, addr
+ aper_size
- 1, aper_size
>> 10);
88 register_nosave_region(addr
>> PAGE_SHIFT
,
89 (addr
+aper_size
) >> PAGE_SHIFT
);
95 /* Find a PCI capability */
96 static u32 __init
find_cap(int bus
, int slot
, int func
, int cap
)
101 if (!(read_pci_config_16(bus
, slot
, func
, PCI_STATUS
) &
102 PCI_STATUS_CAP_LIST
))
105 pos
= read_pci_config_byte(bus
, slot
, func
, PCI_CAPABILITY_LIST
);
106 for (bytes
= 0; bytes
< 48 && pos
>= 0x40; bytes
++) {
110 id
= read_pci_config_byte(bus
, slot
, func
, pos
+PCI_CAP_LIST_ID
);
115 pos
= read_pci_config_byte(bus
, slot
, func
,
116 pos
+PCI_CAP_LIST_NEXT
);
121 /* Read a standard AGPv3 bridge header */
122 static u32 __init
read_agp(int bus
, int slot
, int func
, int cap
, u32
*order
)
127 u32 aper_low
, aper_hi
;
131 pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus
, slot
, func
);
132 apsizereg
= read_pci_config_16(bus
, slot
, func
, cap
+ 0x14);
133 if (apsizereg
== 0xffffffff) {
134 pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n",
139 /* old_order could be the value from NB gart setting */
142 apsize
= apsizereg
& 0xfff;
143 /* Some BIOS use weird encodings not in the AGPv3 table. */
146 nbits
= hweight16(apsize
);
148 if ((int)*order
< 0) /* < 32MB */
151 aper_low
= read_pci_config(bus
, slot
, func
, 0x10);
152 aper_hi
= read_pci_config(bus
, slot
, func
, 0x14);
153 aper
= (aper_low
& ~((1<<22)-1)) | ((u64
)aper_hi
<< 32);
156 * On some sick chips, APSIZE is 0. It means it wants 4G
157 * so let double check that order, and lets trust AMD NB settings:
159 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n",
160 bus
, slot
, func
, aper
, aper
+ (32ULL << (old_order
+ 20)) - 1,
162 if (aper
+ (32ULL<<(20 + *order
)) > 0x100000000ULL
) {
163 pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n",
164 bus
, slot
, func
, 32 << *order
, apsizereg
);
168 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n",
169 bus
, slot
, func
, aper
, aper
+ (32ULL << (*order
+ 20)) - 1,
170 32 << *order
, apsizereg
);
172 if (!aperture_valid(aper
, (32*1024*1024) << *order
, 32<<20))
178 * Look for an AGP bridge. Windows only expects the aperture in the
179 * AGP bridge and some BIOS forget to initialize the Northbridge too.
180 * Work around this here.
182 * Do an PCI bus scan by hand because we're running before the PCI
185 * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
186 * generically. It's probably overkill to always scan all slots because
187 * the AGP bridges should be always an own bus on the HT hierarchy,
188 * but do it here for future safety.
190 static u32 __init
search_agp_bridge(u32
*order
, int *valid_agp
)
194 /* Poor man's PCI discovery */
195 for (bus
= 0; bus
< 256; bus
++) {
196 for (slot
= 0; slot
< 32; slot
++) {
197 for (func
= 0; func
< 8; func
++) {
200 class = read_pci_config(bus
, slot
, func
,
202 if (class == 0xffffffff)
205 switch (class >> 16) {
206 case PCI_CLASS_BRIDGE_HOST
:
207 case PCI_CLASS_BRIDGE_OTHER
: /* needed? */
209 cap
= find_cap(bus
, slot
, func
,
214 return read_agp(bus
, slot
, func
, cap
,
218 /* No multi-function device? */
219 type
= read_pci_config_byte(bus
, slot
, func
,
226 pr_info("No AGP bridge found\n");
231 static bool gart_fix_e820 __initdata
= true;
233 static int __init
parse_gart_mem(char *p
)
235 return kstrtobool(p
, &gart_fix_e820
);
237 early_param("gart_fix_e820", parse_gart_mem
);
239 void __init
early_gart_iommu_check(void)
242 * in case it is enabled before, esp for kexec/kdump,
243 * previous kernel already enable that. memset called
244 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
245 * or second kernel have different position for GART hole. and new
246 * kernel could use hole as RAM that is still used by GART set by
248 * or BIOS forget to put that in reserved.
249 * try to update e820 to make that region as reserved.
251 u32 agp_aper_order
= 0;
252 int i
, fix
, slot
, valid_agp
= 0;
254 u32 aper_size
= 0, aper_order
= 0, last_aper_order
= 0;
255 u64 aper_base
= 0, last_aper_base
= 0;
256 int aper_enabled
= 0, last_aper_enabled
= 0, last_valid
= 0;
258 if (!amd_gart_present())
261 if (!early_pci_allowed())
264 /* This is mostly duplicate of iommu_hole_init */
265 search_agp_bridge(&agp_aper_order
, &valid_agp
);
268 for (i
= 0; amd_nb_bus_dev_ranges
[i
].dev_limit
; i
++) {
270 int dev_base
, dev_limit
;
272 bus
= amd_nb_bus_dev_ranges
[i
].bus
;
273 dev_base
= amd_nb_bus_dev_ranges
[i
].dev_base
;
274 dev_limit
= amd_nb_bus_dev_ranges
[i
].dev_limit
;
276 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
277 if (!early_is_amd_nb(read_pci_config(bus
, slot
, 3, 0x00)))
280 ctl
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
);
281 aper_enabled
= ctl
& GARTEN
;
282 aper_order
= (ctl
>> 1) & 7;
283 aper_size
= (32 * 1024 * 1024) << aper_order
;
284 aper_base
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTUREBASE
) & 0x7fff;
288 if ((aper_order
!= last_aper_order
) ||
289 (aper_base
!= last_aper_base
) ||
290 (aper_enabled
!= last_aper_enabled
)) {
296 last_aper_order
= aper_order
;
297 last_aper_base
= aper_base
;
298 last_aper_enabled
= aper_enabled
;
303 if (!fix
&& !aper_enabled
)
306 if (!aper_base
|| !aper_size
|| aper_base
+ aper_size
> 0x100000000UL
)
309 if (gart_fix_e820
&& !fix
&& aper_enabled
) {
310 if (e820__mapped_any(aper_base
, aper_base
+ aper_size
,
312 /* reserve it, so we can reuse it in second kernel */
313 pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n",
314 aper_base
, aper_base
+ aper_size
- 1);
315 e820__range_add(aper_base
, aper_size
, E820_TYPE_RESERVED
);
316 e820__update_table_print();
323 /* disable them all at first */
324 for (i
= 0; i
< amd_nb_bus_dev_ranges
[i
].dev_limit
; i
++) {
326 int dev_base
, dev_limit
;
328 bus
= amd_nb_bus_dev_ranges
[i
].bus
;
329 dev_base
= amd_nb_bus_dev_ranges
[i
].dev_base
;
330 dev_limit
= amd_nb_bus_dev_ranges
[i
].dev_limit
;
332 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
333 if (!early_is_amd_nb(read_pci_config(bus
, slot
, 3, 0x00)))
336 ctl
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
);
338 write_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
, ctl
);
344 static int __initdata printed_gart_size_msg
;
346 int __init
gart_iommu_hole_init(void)
348 u32 agp_aper_base
= 0, agp_aper_order
= 0;
349 u32 aper_size
, aper_alloc
= 0, aper_order
= 0, last_aper_order
= 0;
350 u64 aper_base
, last_aper_base
= 0;
351 int fix
, slot
, valid_agp
= 0;
354 if (!amd_gart_present())
357 if (gart_iommu_aperture_disabled
|| !fix_aperture
||
358 !early_pci_allowed())
361 pr_info("Checking aperture...\n");
363 if (!fallback_aper_force
)
364 agp_aper_base
= search_agp_bridge(&agp_aper_order
, &valid_agp
);
368 for (i
= 0; i
< amd_nb_bus_dev_ranges
[i
].dev_limit
; i
++) {
370 int dev_base
, dev_limit
;
373 bus
= amd_nb_bus_dev_ranges
[i
].bus
;
374 dev_base
= amd_nb_bus_dev_ranges
[i
].dev_base
;
375 dev_limit
= amd_nb_bus_dev_ranges
[i
].dev_limit
;
377 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
378 if (!early_is_amd_nb(read_pci_config(bus
, slot
, 3, 0x00)))
382 gart_iommu_aperture
= 1;
383 x86_init
.iommu
.iommu_init
= gart_iommu_init
;
385 ctl
= read_pci_config(bus
, slot
, 3,
386 AMD64_GARTAPERTURECTL
);
389 * Before we do anything else disable the GART. It may
390 * still be enabled if we boot into a crash-kernel here.
391 * Reconfiguring the GART while it is enabled could have
392 * unknown side-effects.
395 write_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
, ctl
);
397 aper_order
= (ctl
>> 1) & 7;
398 aper_size
= (32 * 1024 * 1024) << aper_order
;
399 aper_base
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTUREBASE
) & 0x7fff;
402 pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n",
403 node
, aper_base
, aper_base
+ aper_size
- 1,
407 if (!aperture_valid(aper_base
, aper_size
, 64<<20)) {
408 if (valid_agp
&& agp_aper_base
&&
409 agp_aper_base
== aper_base
&&
410 agp_aper_order
== aper_order
) {
411 /* the same between two setting from NB and agp */
413 max_pfn
> MAX_DMA32_PFN
&&
414 !printed_gart_size_msg
) {
415 pr_err("you are using iommu with agp, but GART size is less than 64MB\n");
416 pr_err("please increase GART size in your BIOS setup\n");
417 pr_err("if BIOS doesn't have that option, contact your HW vendor!\n");
418 printed_gart_size_msg
= 1;
426 if ((last_aper_order
&& aper_order
!= last_aper_order
) ||
427 (last_aper_base
&& aper_base
!= last_aper_base
)) {
431 last_aper_order
= aper_order
;
432 last_aper_base
= aper_base
;
437 if (!fix
&& !fallback_aper_force
) {
443 if (!fallback_aper_force
) {
444 aper_alloc
= agp_aper_base
;
445 aper_order
= agp_aper_order
;
449 /* Got the aperture from the AGP bridge */
450 } else if ((!no_iommu
&& max_pfn
> MAX_DMA32_PFN
) ||
453 fallback_aper_force
) {
454 pr_info("Your BIOS doesn't leave an aperture memory hole\n");
455 pr_info("Please enable the IOMMU option in the BIOS setup\n");
456 pr_info("This costs you %dMB of RAM\n",
457 32 << fallback_aper_order
);
459 aper_order
= fallback_aper_order
;
460 aper_alloc
= allocate_aperture();
463 * Could disable AGP and IOMMU here, but it's
464 * probably not worth it. But the later users
465 * cannot deal with bad apertures and turning
466 * on the aperture over memory causes very
467 * strange problems, so it's better to panic
470 panic("Not enough memory for aperture");
476 /* Fix up the north bridges */
477 for (i
= 0; i
< amd_nb_bus_dev_ranges
[i
].dev_limit
; i
++) {
478 int bus
, dev_base
, dev_limit
;
481 * Don't enable translation yet but enable GART IO and CPU
482 * accesses and set DISTLBWALKPRB since GART table memory is UC.
484 u32 ctl
= aper_order
<< 1;
486 bus
= amd_nb_bus_dev_ranges
[i
].bus
;
487 dev_base
= amd_nb_bus_dev_ranges
[i
].dev_base
;
488 dev_limit
= amd_nb_bus_dev_ranges
[i
].dev_limit
;
489 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
490 if (!early_is_amd_nb(read_pci_config(bus
, slot
, 3, 0x00)))
493 write_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
, ctl
);
494 write_pci_config(bus
, slot
, 3, AMD64_GARTAPERTUREBASE
, aper_alloc
>> 25);
498 set_up_gart_resume(aper_order
, aper_alloc
);