2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
51 unsigned int num_processors
;
53 unsigned disabled_cpus __cpuinitdata
;
55 /* Processor that is doing the boot up */
56 unsigned int boot_cpu_physical_apicid
= -1U;
59 * The highest APIC ID seen during enumeration.
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
65 * If there's an APIC ID above 8, we use physical addressing.
67 unsigned int max_physical_apicid
;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map
;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
78 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
84 * Knob to control our willingness to enable the local APIC.
88 static int force_enable_local_apic
;
90 * APIC command line parameters
92 static int __init
parse_lapic(char *arg
)
94 force_enable_local_apic
= 1;
97 early_param("lapic", parse_lapic
);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase
;
104 static int apic_calibrate_pmtmr __initdata
;
105 static __init
int setup_apicpmtimer(char *s
)
107 apic_calibrate_pmtmr
= 1;
111 __setup("apicpmtimer", setup_apicpmtimer
);
114 #ifdef CONFIG_X86_X2APIC
116 /* x2apic enabled before OS handover */
117 static int x2apic_preenabled
;
118 static int disable_x2apic
;
119 static __init
int setup_nox2apic(char *str
)
122 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
125 early_param("nox2apic", setup_nox2apic
);
128 unsigned long mp_lapic_addr
;
130 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
131 static int disable_apic_timer __cpuinitdata
;
132 /* Local APIC timer works in C2 */
133 int local_apic_timer_c2_ok
;
134 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
136 int first_system_vector
= 0xfe;
139 * Debug level, exported for io_apic.c
141 unsigned int apic_verbosity
;
145 /* Have we found an MP table */
146 int smp_found_config
;
148 static struct resource lapic_resource
= {
149 .name
= "Local APIC",
150 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
153 static unsigned int calibration_result
;
155 static int lapic_next_event(unsigned long delta
,
156 struct clock_event_device
*evt
);
157 static void lapic_timer_setup(enum clock_event_mode mode
,
158 struct clock_event_device
*evt
);
159 static void lapic_timer_broadcast(const struct cpumask
*mask
);
160 static void apic_pm_activate(void);
163 * The local apic timer can be used for any function which is CPU local.
165 static struct clock_event_device lapic_clockevent
= {
167 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
168 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
170 .set_mode
= lapic_timer_setup
,
171 .set_next_event
= lapic_next_event
,
172 .broadcast
= lapic_timer_broadcast
,
176 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
178 static unsigned long apic_phys
;
181 * Get the LAPIC version
183 static inline int lapic_get_version(void)
185 return GET_APIC_VERSION(apic_read(APIC_LVR
));
189 * Check, if the APIC is integrated or a separate chip
191 static inline int lapic_is_integrated(void)
196 return APIC_INTEGRATED(lapic_get_version());
201 * Check, whether this is a modern or a first generation APIC
203 static int modern_apic(void)
205 /* AMD systems use old APIC versions, so check the CPU */
206 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
207 boot_cpu_data
.x86
>= 0xf)
209 return lapic_get_version() >= 0x14;
212 void native_apic_wait_icr_idle(void)
214 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
218 u32
native_safe_apic_wait_icr_idle(void)
225 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
229 } while (timeout
++ < 1000);
234 void native_apic_icr_write(u32 low
, u32 id
)
236 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
237 apic_write(APIC_ICR
, low
);
240 u64
native_apic_icr_read(void)
244 icr2
= apic_read(APIC_ICR2
);
245 icr1
= apic_read(APIC_ICR
);
247 return icr1
| ((u64
)icr2
<< 32);
251 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
253 void __cpuinit
enable_NMI_through_LVT0(void)
257 /* unmask and set to NMI */
260 /* Level triggered for 82489DX (32bit mode) */
261 if (!lapic_is_integrated())
262 v
|= APIC_LVT_LEVEL_TRIGGER
;
264 apic_write(APIC_LVT0
, v
);
269 * get_physical_broadcast - Get number of physical broadcast IDs
271 int get_physical_broadcast(void)
273 return modern_apic() ? 0xff : 0xf;
278 * lapic_get_maxlvt - get the maximum number of local vector table entries
280 int lapic_get_maxlvt(void)
284 v
= apic_read(APIC_LVR
);
286 * - we always have APIC integrated on 64bit mode
287 * - 82489DXs do not report # of LVT entries
289 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
297 #define APIC_DIVISOR 16
300 * This function sets up the local APIC timer, with a timeout of
301 * 'clocks' APIC bus clock. During calibration we actually call
302 * this function twice on the boot CPU, once with a bogus timeout
303 * value, second time for real. The other (noncalibrating) CPUs
304 * call this function only once, with the real, calibrated value.
306 * We do reads before writes even if unnecessary, to get around the
307 * P5 APIC double write bug.
309 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
311 unsigned int lvtt_value
, tmp_value
;
313 lvtt_value
= LOCAL_TIMER_VECTOR
;
315 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
316 if (!lapic_is_integrated())
317 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
320 lvtt_value
|= APIC_LVT_MASKED
;
322 apic_write(APIC_LVTT
, lvtt_value
);
327 tmp_value
= apic_read(APIC_TDCR
);
328 apic_write(APIC_TDCR
,
329 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
333 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
337 * Setup extended LVT, AMD specific (K8, family 10h)
339 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
340 * MCE interrupts are supported. Thus MCE offset must be set to 0.
342 * If mask=1, the LVT entry does not generate interrupts while mask=0
343 * enables the vector. See also the BKDGs.
346 #define APIC_EILVT_LVTOFF_MCE 0
347 #define APIC_EILVT_LVTOFF_IBS 1
349 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
351 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
352 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
357 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
359 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
360 return APIC_EILVT_LVTOFF_MCE
;
363 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
365 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
366 return APIC_EILVT_LVTOFF_IBS
;
368 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
371 * Program the next event, relative to now
373 static int lapic_next_event(unsigned long delta
,
374 struct clock_event_device
*evt
)
376 apic_write(APIC_TMICT
, delta
);
381 * Setup the lapic timer in periodic or oneshot mode
383 static void lapic_timer_setup(enum clock_event_mode mode
,
384 struct clock_event_device
*evt
)
389 /* Lapic used as dummy for broadcast ? */
390 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
393 local_irq_save(flags
);
396 case CLOCK_EVT_MODE_PERIODIC
:
397 case CLOCK_EVT_MODE_ONESHOT
:
398 __setup_APIC_LVTT(calibration_result
,
399 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
401 case CLOCK_EVT_MODE_UNUSED
:
402 case CLOCK_EVT_MODE_SHUTDOWN
:
403 v
= apic_read(APIC_LVTT
);
404 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
405 apic_write(APIC_LVTT
, v
);
406 apic_write(APIC_TMICT
, 0xffffffff);
408 case CLOCK_EVT_MODE_RESUME
:
409 /* Nothing to do here */
413 local_irq_restore(flags
);
417 * Local APIC timer broadcast function
419 static void lapic_timer_broadcast(const struct cpumask
*mask
)
422 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
427 * Setup the local APIC timer for this CPU. Copy the initilized values
428 * of the boot CPU and register the clock event in the framework.
430 static void __cpuinit
setup_APIC_timer(void)
432 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
434 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
435 levt
->cpumask
= cpumask_of(smp_processor_id());
437 clockevents_register_device(levt
);
441 * In this functions we calibrate APIC bus clocks to the external timer.
443 * We want to do the calibration only once since we want to have local timer
444 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
447 * This was previously done by reading the PIT/HPET and waiting for a wrap
448 * around to find out, that a tick has elapsed. I have a box, where the PIT
449 * readout is broken, so it never gets out of the wait loop again. This was
450 * also reported by others.
452 * Monitoring the jiffies value is inaccurate and the clockevents
453 * infrastructure allows us to do a simple substitution of the interrupt
456 * The calibration routine also uses the pm_timer when possible, as the PIT
457 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
458 * back to normal later in the boot process).
461 #define LAPIC_CAL_LOOPS (HZ/10)
463 static __initdata
int lapic_cal_loops
= -1;
464 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
465 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
466 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
467 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
470 * Temporary interrupt handler.
472 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
474 unsigned long long tsc
= 0;
475 long tapic
= apic_read(APIC_TMCCT
);
476 unsigned long pm
= acpi_pm_read_early();
481 switch (lapic_cal_loops
++) {
483 lapic_cal_t1
= tapic
;
484 lapic_cal_tsc1
= tsc
;
486 lapic_cal_j1
= jiffies
;
489 case LAPIC_CAL_LOOPS
:
490 lapic_cal_t2
= tapic
;
491 lapic_cal_tsc2
= tsc
;
492 if (pm
< lapic_cal_pm1
)
493 pm
+= ACPI_PM_OVRRUN
;
495 lapic_cal_j2
= jiffies
;
501 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
503 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
504 const long pm_thresh
= pm_100ms
/ 100;
508 #ifndef CONFIG_X86_PM_TIMER
512 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
514 /* Check, if the PM timer is available */
518 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
520 if (deltapm
> (pm_100ms
- pm_thresh
) &&
521 deltapm
< (pm_100ms
+ pm_thresh
)) {
522 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
526 res
= (((u64
)deltapm
) * mult
) >> 22;
527 do_div(res
, 1000000);
528 pr_warning("APIC calibration not consistent "
529 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
531 /* Correct the lapic counter value */
532 res
= (((u64
)(*delta
)) * pm_100ms
);
533 do_div(res
, deltapm
);
534 pr_info("APIC delta adjusted to PM-Timer: "
535 "%lu (%ld)\n", (unsigned long)res
, *delta
);
538 /* Correct the tsc counter value */
540 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
541 do_div(res
, deltapm
);
542 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
543 "PM-Timer: %lu (%ld) \n",
544 (unsigned long)res
, *deltatsc
);
545 *deltatsc
= (long)res
;
551 static int __init
calibrate_APIC_clock(void)
553 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
554 void (*real_handler
)(struct clock_event_device
*dev
);
555 unsigned long deltaj
;
556 long delta
, deltatsc
;
557 int pm_referenced
= 0;
561 /* Replace the global interrupt handler */
562 real_handler
= global_clock_event
->event_handler
;
563 global_clock_event
->event_handler
= lapic_cal_handler
;
566 * Setup the APIC counter to maximum. There is no way the lapic
567 * can underflow in the 100ms detection time frame
569 __setup_APIC_LVTT(0xffffffff, 0, 0);
571 /* Let the interrupts run */
574 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
579 /* Restore the real event handler */
580 global_clock_event
->event_handler
= real_handler
;
582 /* Build delta t1-t2 as apic timer counts down */
583 delta
= lapic_cal_t1
- lapic_cal_t2
;
584 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
586 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
588 /* we trust the PM based calibration if possible */
589 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
592 /* Calculate the scaled math multiplication factor */
593 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
594 lapic_clockevent
.shift
);
595 lapic_clockevent
.max_delta_ns
=
596 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
597 lapic_clockevent
.min_delta_ns
=
598 clockevent_delta2ns(0xF, &lapic_clockevent
);
600 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
602 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
603 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
604 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
608 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
610 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
611 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
614 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
616 calibration_result
/ (1000000 / HZ
),
617 calibration_result
% (1000000 / HZ
));
620 * Do a sanity check on the APIC calibration result
622 if (calibration_result
< (1000000 / HZ
)) {
624 pr_warning("APIC frequency too slow, disabling apic timer\n");
628 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
631 * PM timer calibration failed or not turned on
632 * so lets try APIC timer based calibration
634 if (!pm_referenced
) {
635 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
638 * Setup the apic timer manually
640 levt
->event_handler
= lapic_cal_handler
;
641 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
642 lapic_cal_loops
= -1;
644 /* Let the interrupts run */
647 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
650 /* Stop the lapic timer */
651 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
654 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
655 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
657 /* Check, if the jiffies result is consistent */
658 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
659 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
661 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
665 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
666 pr_warning("APIC timer disabled due to verification failure\n");
674 * Setup the boot APIC
676 * Calibrate and verify the result.
678 void __init
setup_boot_APIC_clock(void)
681 * The local apic timer can be disabled via the kernel
682 * commandline or from the CPU detection code. Register the lapic
683 * timer as a dummy clock event source on SMP systems, so the
684 * broadcast mechanism is used. On UP systems simply ignore it.
686 if (disable_apic_timer
) {
687 pr_info("Disabling APIC timer\n");
688 /* No broadcast on UP ! */
689 if (num_possible_cpus() > 1) {
690 lapic_clockevent
.mult
= 1;
696 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
697 "calibrating APIC timer ...\n");
699 if (calibrate_APIC_clock()) {
700 /* No broadcast on UP ! */
701 if (num_possible_cpus() > 1)
707 * If nmi_watchdog is set to IO_APIC, we need the
708 * PIT/HPET going. Otherwise register lapic as a dummy
711 if (nmi_watchdog
!= NMI_IO_APIC
)
712 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
714 pr_warning("APIC timer registered as dummy,"
715 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
717 /* Setup the lapic or request the broadcast */
721 void __cpuinit
setup_secondary_APIC_clock(void)
727 * The guts of the apic timer interrupt
729 static void local_apic_timer_interrupt(void)
731 int cpu
= smp_processor_id();
732 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
735 * Normally we should not be here till LAPIC has been initialized but
736 * in some cases like kdump, its possible that there is a pending LAPIC
737 * timer interrupt from previous kernel's context and is delivered in
738 * new kernel the moment interrupts are enabled.
740 * Interrupts are enabled early and LAPIC is setup much later, hence
741 * its possible that when we get here evt->event_handler is NULL.
742 * Check for event_handler being NULL and discard the interrupt as
745 if (!evt
->event_handler
) {
746 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
748 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
753 * the NMI deadlock-detector uses this.
755 inc_irq_stat(apic_timer_irqs
);
757 evt
->event_handler(evt
);
761 * Local APIC timer interrupt. This is the most natural way for doing
762 * local interrupts, but local timer interrupts can be emulated by
763 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
765 * [ if a single-CPU system runs an SMP kernel then we call the local
766 * interrupt as well. Thus we cannot inline the local irq ... ]
768 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
770 struct pt_regs
*old_regs
= set_irq_regs(regs
);
773 * NOTE! We'd better ACK the irq immediately,
774 * because timer handling can be slow.
778 * update_process_times() expects us to have done irq_enter().
779 * Besides, if we don't timer interrupts ignore the global
780 * interrupt lock, which is the WrongThing (tm) to do.
784 local_apic_timer_interrupt();
787 set_irq_regs(old_regs
);
790 int setup_profiling_timer(unsigned int multiplier
)
796 * Local APIC start and shutdown
800 * clear_local_APIC - shutdown the local APIC
802 * This is called, when a CPU is disabled and before rebooting, so the state of
803 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
804 * leftovers during boot.
806 void clear_local_APIC(void)
811 /* APIC hasn't been mapped yet */
812 if (!x2apic
&& !apic_phys
)
815 maxlvt
= lapic_get_maxlvt();
817 * Masking an LVT entry can trigger a local APIC error
818 * if the vector is zero. Mask LVTERR first to prevent this.
821 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
822 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
825 * Careful: we have to set masks only first to deassert
826 * any level-triggered sources.
828 v
= apic_read(APIC_LVTT
);
829 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
830 v
= apic_read(APIC_LVT0
);
831 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
832 v
= apic_read(APIC_LVT1
);
833 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
835 v
= apic_read(APIC_LVTPC
);
836 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
839 /* lets not touch this if we didn't frob it */
840 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
842 v
= apic_read(APIC_LVTTHMR
);
843 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
846 #ifdef CONFIG_X86_MCE_INTEL
848 v
= apic_read(APIC_LVTCMCI
);
849 if (!(v
& APIC_LVT_MASKED
))
850 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
855 * Clean APIC state for other OSs:
857 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
858 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
859 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
861 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
863 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
865 /* Integrated APIC (!82489DX) ? */
866 if (lapic_is_integrated()) {
868 /* Clear ESR due to Pentium errata 3AP and 11AP */
869 apic_write(APIC_ESR
, 0);
875 * disable_local_APIC - clear and disable the local APIC
877 void disable_local_APIC(void)
881 /* APIC hasn't been mapped yet */
888 * Disable APIC (implies clearing of registers
891 value
= apic_read(APIC_SPIV
);
892 value
&= ~APIC_SPIV_APIC_ENABLED
;
893 apic_write(APIC_SPIV
, value
);
897 * When LAPIC was disabled by the BIOS and enabled by the kernel,
898 * restore the disabled state.
900 if (enabled_via_apicbase
) {
903 rdmsr(MSR_IA32_APICBASE
, l
, h
);
904 l
&= ~MSR_IA32_APICBASE_ENABLE
;
905 wrmsr(MSR_IA32_APICBASE
, l
, h
);
911 * If Linux enabled the LAPIC against the BIOS default disable it down before
912 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
913 * not power-off. Additionally clear all LVT entries before disable_local_APIC
914 * for the case where Linux didn't enable the LAPIC.
916 void lapic_shutdown(void)
923 local_irq_save(flags
);
926 if (!enabled_via_apicbase
)
930 disable_local_APIC();
933 local_irq_restore(flags
);
937 * This is to verify that we're looking at a real local APIC.
938 * Check these against your board if the CPUs aren't getting
939 * started for no apparent reason.
941 int __init
verify_local_APIC(void)
943 unsigned int reg0
, reg1
;
946 * The version register is read-only in a real APIC.
948 reg0
= apic_read(APIC_LVR
);
949 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
950 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
951 reg1
= apic_read(APIC_LVR
);
952 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
955 * The two version reads above should print the same
956 * numbers. If the second one is different, then we
957 * poke at a non-APIC.
963 * Check if the version looks reasonably.
965 reg1
= GET_APIC_VERSION(reg0
);
966 if (reg1
== 0x00 || reg1
== 0xff)
968 reg1
= lapic_get_maxlvt();
969 if (reg1
< 0x02 || reg1
== 0xff)
973 * The ID register is read/write in a real APIC.
975 reg0
= apic_read(APIC_ID
);
976 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
977 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
978 reg1
= apic_read(APIC_ID
);
979 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
980 apic_write(APIC_ID
, reg0
);
981 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
985 * The next two are just to see if we have sane values.
986 * They're only really relevant if we're in Virtual Wire
987 * compatibility mode, but most boxes are anymore.
989 reg0
= apic_read(APIC_LVT0
);
990 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
991 reg1
= apic_read(APIC_LVT1
);
992 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
998 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1000 void __init
sync_Arb_IDs(void)
1003 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1006 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1012 apic_wait_icr_idle();
1014 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1015 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1016 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1020 * An initial setup of the virtual wire mode.
1022 void __init
init_bsp_APIC(void)
1027 * Don't do the setup now if we have a SMP BIOS as the
1028 * through-I/O-APIC virtual wire mode might be active.
1030 if (smp_found_config
|| !cpu_has_apic
)
1034 * Do not trust the local APIC being empty at bootup.
1041 value
= apic_read(APIC_SPIV
);
1042 value
&= ~APIC_VECTOR_MASK
;
1043 value
|= APIC_SPIV_APIC_ENABLED
;
1045 #ifdef CONFIG_X86_32
1046 /* This bit is reserved on P4/Xeon and should be cleared */
1047 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1048 (boot_cpu_data
.x86
== 15))
1049 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1052 value
|= APIC_SPIV_FOCUS_DISABLED
;
1053 value
|= SPURIOUS_APIC_VECTOR
;
1054 apic_write(APIC_SPIV
, value
);
1057 * Set up the virtual wire mode.
1059 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1060 value
= APIC_DM_NMI
;
1061 if (!lapic_is_integrated()) /* 82489DX */
1062 value
|= APIC_LVT_LEVEL_TRIGGER
;
1063 apic_write(APIC_LVT1
, value
);
1066 static void __cpuinit
lapic_setup_esr(void)
1068 unsigned int oldvalue
, value
, maxlvt
;
1070 if (!lapic_is_integrated()) {
1071 pr_info("No ESR for 82489DX.\n");
1075 if (apic
->disable_esr
) {
1077 * Something untraceable is creating bad interrupts on
1078 * secondary quads ... for the moment, just leave the
1079 * ESR disabled - we can't do anything useful with the
1080 * errors anyway - mbligh
1082 pr_info("Leaving ESR disabled.\n");
1086 maxlvt
= lapic_get_maxlvt();
1087 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1088 apic_write(APIC_ESR
, 0);
1089 oldvalue
= apic_read(APIC_ESR
);
1091 /* enables sending errors */
1092 value
= ERROR_APIC_VECTOR
;
1093 apic_write(APIC_LVTERR
, value
);
1096 * spec says clear errors after enabling vector.
1099 apic_write(APIC_ESR
, 0);
1100 value
= apic_read(APIC_ESR
);
1101 if (value
!= oldvalue
)
1102 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1103 "vector: 0x%08x after: 0x%08x\n",
1109 * setup_local_APIC - setup the local APIC
1111 void __cpuinit
setup_local_APIC(void)
1117 arch_disable_smp_support();
1121 #ifdef CONFIG_X86_32
1122 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1123 if (lapic_is_integrated() && apic
->disable_esr
) {
1124 apic_write(APIC_ESR
, 0);
1125 apic_write(APIC_ESR
, 0);
1126 apic_write(APIC_ESR
, 0);
1127 apic_write(APIC_ESR
, 0);
1134 * Double-check whether this APIC is really registered.
1135 * This is meaningless in clustered apic mode, so we skip it.
1137 if (!apic
->apic_id_registered())
1141 * Intel recommends to set DFR, LDR and TPR before enabling
1142 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1143 * document number 292116). So here it goes...
1145 apic
->init_apic_ldr();
1148 * Set Task Priority to 'accept all'. We never change this
1151 value
= apic_read(APIC_TASKPRI
);
1152 value
&= ~APIC_TPRI_MASK
;
1153 apic_write(APIC_TASKPRI
, value
);
1156 * After a crash, we no longer service the interrupts and a pending
1157 * interrupt from previous kernel might still have ISR bit set.
1159 * Most probably by now CPU has serviced that pending interrupt and
1160 * it might not have done the ack_APIC_irq() because it thought,
1161 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1162 * does not clear the ISR bit and cpu thinks it has already serivced
1163 * the interrupt. Hence a vector might get locked. It was noticed
1164 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1166 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1167 value
= apic_read(APIC_ISR
+ i
*0x10);
1168 for (j
= 31; j
>= 0; j
--) {
1175 * Now that we are all set up, enable the APIC
1177 value
= apic_read(APIC_SPIV
);
1178 value
&= ~APIC_VECTOR_MASK
;
1182 value
|= APIC_SPIV_APIC_ENABLED
;
1184 #ifdef CONFIG_X86_32
1186 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1187 * certain networking cards. If high frequency interrupts are
1188 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1189 * entry is masked/unmasked at a high rate as well then sooner or
1190 * later IOAPIC line gets 'stuck', no more interrupts are received
1191 * from the device. If focus CPU is disabled then the hang goes
1194 * [ This bug can be reproduced easily with a level-triggered
1195 * PCI Ne2000 networking cards and PII/PIII processors, dual
1199 * Actually disabling the focus CPU check just makes the hang less
1200 * frequent as it makes the interrupt distributon model be more
1201 * like LRU than MRU (the short-term load is more even across CPUs).
1202 * See also the comment in end_level_ioapic_irq(). --macro
1206 * - enable focus processor (bit==0)
1207 * - 64bit mode always use processor focus
1208 * so no need to set it
1210 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1214 * Set spurious IRQ vector
1216 value
|= SPURIOUS_APIC_VECTOR
;
1217 apic_write(APIC_SPIV
, value
);
1220 * Set up LVT0, LVT1:
1222 * set up through-local-APIC on the BP's LINT0. This is not
1223 * strictly necessary in pure symmetric-IO mode, but sometimes
1224 * we delegate interrupts to the 8259A.
1227 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1229 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1230 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1231 value
= APIC_DM_EXTINT
;
1232 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1233 smp_processor_id());
1235 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1236 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1237 smp_processor_id());
1239 apic_write(APIC_LVT0
, value
);
1242 * only the BP should see the LINT1 NMI signal, obviously.
1244 if (!smp_processor_id())
1245 value
= APIC_DM_NMI
;
1247 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1248 if (!lapic_is_integrated()) /* 82489DX */
1249 value
|= APIC_LVT_LEVEL_TRIGGER
;
1250 apic_write(APIC_LVT1
, value
);
1254 #ifdef CONFIG_X86_MCE_INTEL
1255 /* Recheck CMCI information after local APIC is up on CPU #0 */
1256 if (smp_processor_id() == 0)
1261 void __cpuinit
end_local_APIC_setup(void)
1265 #ifdef CONFIG_X86_32
1268 /* Disable the local apic timer */
1269 value
= apic_read(APIC_LVTT
);
1270 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1271 apic_write(APIC_LVTT
, value
);
1275 setup_apic_nmi_watchdog(NULL
);
1279 #ifdef CONFIG_X86_X2APIC
1280 void check_x2apic(void)
1282 if (x2apic_enabled()) {
1283 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1284 x2apic_preenabled
= x2apic
= 1;
1288 void enable_x2apic(void)
1295 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1296 if (!(msr
& X2APIC_ENABLE
)) {
1297 pr_info("Enabling x2apic\n");
1298 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1302 void __init
enable_IR_x2apic(void)
1304 #ifdef CONFIG_INTR_REMAP
1306 unsigned long flags
;
1307 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1309 if (!cpu_has_x2apic
)
1312 if (!x2apic_preenabled
&& disable_x2apic
) {
1313 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1314 "because of nox2apic\n");
1318 if (x2apic_preenabled
&& disable_x2apic
)
1319 panic("Bios already enabled x2apic, can't enforce nox2apic");
1321 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1322 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1323 "because of skipping io-apic setup\n");
1327 ret
= dmar_table_init();
1329 pr_info("dmar_table_init() failed with %d:\n", ret
);
1331 if (x2apic_preenabled
)
1332 panic("x2apic enabled by bios. But IR enabling failed");
1334 pr_info("Not enabling x2apic,Intr-remapping\n");
1338 ioapic_entries
= alloc_ioapic_entries();
1339 if (!ioapic_entries
) {
1340 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1344 ret
= save_IO_APIC_setup(ioapic_entries
);
1346 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1350 local_irq_save(flags
);
1351 mask_IO_APIC_setup(ioapic_entries
);
1354 ret
= enable_intr_remapping(EIM_32BIT_APIC_ID
);
1356 if (ret
&& x2apic_preenabled
) {
1357 local_irq_restore(flags
);
1358 panic("x2apic enabled by bios. But IR enabling failed");
1372 * IR enabling failed
1374 restore_IO_APIC_setup(ioapic_entries
);
1376 reinit_intr_remapped_IO_APIC(x2apic_preenabled
, ioapic_entries
);
1379 local_irq_restore(flags
);
1383 if (!x2apic_preenabled
)
1384 pr_info("Enabled x2apic and interrupt-remapping\n");
1386 pr_info("Enabled Interrupt-remapping\n");
1388 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1390 free_ioapic_entries(ioapic_entries
);
1392 if (!cpu_has_x2apic
)
1395 if (x2apic_preenabled
)
1396 panic("x2apic enabled prior OS handover,"
1397 " enable CONFIG_INTR_REMAP");
1399 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1405 #endif /* CONFIG_X86_X2APIC */
1407 #ifdef CONFIG_X86_64
1409 * Detect and enable local APICs on non-SMP boards.
1410 * Original code written by Keir Fraser.
1411 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1412 * not correctly set up (usually the APIC timer won't work etc.)
1414 static int __init
detect_init_APIC(void)
1416 if (!cpu_has_apic
) {
1417 pr_info("No local APIC present\n");
1421 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1422 boot_cpu_physical_apicid
= 0;
1427 * Detect and initialize APIC
1429 static int __init
detect_init_APIC(void)
1433 /* Disabled by kernel option? */
1437 switch (boot_cpu_data
.x86_vendor
) {
1438 case X86_VENDOR_AMD
:
1439 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1440 (boot_cpu_data
.x86
>= 15))
1443 case X86_VENDOR_INTEL
:
1444 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1445 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1452 if (!cpu_has_apic
) {
1454 * Over-ride BIOS and try to enable the local APIC only if
1455 * "lapic" specified.
1457 if (!force_enable_local_apic
) {
1458 pr_info("Local APIC disabled by BIOS -- "
1459 "you can enable it with \"lapic\"\n");
1463 * Some BIOSes disable the local APIC in the APIC_BASE
1464 * MSR. This can only be done in software for Intel P6 or later
1465 * and AMD K7 (Model > 1) or later.
1467 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1468 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1469 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1470 l
&= ~MSR_IA32_APICBASE_BASE
;
1471 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1472 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1473 enabled_via_apicbase
= 1;
1477 * The APIC feature bit should now be enabled
1480 features
= cpuid_edx(1);
1481 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1482 pr_warning("Could not enable APIC!\n");
1485 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1486 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1488 /* The BIOS may have set up the APIC at some other address */
1489 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1490 if (l
& MSR_IA32_APICBASE_ENABLE
)
1491 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1493 pr_info("Found and enabled local APIC!\n");
1500 pr_info("No local APIC present or hardware disabled\n");
1505 #ifdef CONFIG_X86_64
1506 void __init
early_init_lapic_mapping(void)
1508 unsigned long phys_addr
;
1511 * If no local APIC can be found then go out
1512 * : it means there is no mpatable and MADT
1514 if (!smp_found_config
)
1517 phys_addr
= mp_lapic_addr
;
1519 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1520 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1521 APIC_BASE
, phys_addr
);
1524 * Fetch the APIC ID of the BSP in case we have a
1525 * default configuration (or the MP table is broken).
1527 boot_cpu_physical_apicid
= read_apic_id();
1532 * init_apic_mappings - initialize APIC mappings
1534 void __init
init_apic_mappings(void)
1537 boot_cpu_physical_apicid
= read_apic_id();
1542 * If no local APIC can be found then set up a fake all
1543 * zeroes page to simulate the local APIC and another
1544 * one for the IO-APIC.
1546 if (!smp_found_config
&& detect_init_APIC()) {
1547 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1548 apic_phys
= __pa(apic_phys
);
1550 apic_phys
= mp_lapic_addr
;
1552 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1553 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1554 APIC_BASE
, apic_phys
);
1557 * Fetch the APIC ID of the BSP in case we have a
1558 * default configuration (or the MP table is broken).
1560 if (boot_cpu_physical_apicid
== -1U)
1561 boot_cpu_physical_apicid
= read_apic_id();
1565 * This initializes the IO-APIC and APIC hardware if this is
1568 int apic_version
[MAX_APICS
];
1570 int __init
APIC_init_uniprocessor(void)
1573 pr_info("Apic disabled\n");
1576 #ifdef CONFIG_X86_64
1577 if (!cpu_has_apic
) {
1579 pr_info("Apic disabled by BIOS\n");
1583 if (!smp_found_config
&& !cpu_has_apic
)
1587 * Complain if the BIOS pretends there is one.
1589 if (!cpu_has_apic
&&
1590 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1591 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1592 boot_cpu_physical_apicid
);
1593 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1599 #ifdef CONFIG_X86_64
1600 default_setup_apic_routing();
1603 verify_local_APIC();
1606 #ifdef CONFIG_X86_64
1607 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1610 * Hack: In case of kdump, after a crash, kernel might be booting
1611 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1612 * might be zero if read from MP tables. Get it from LAPIC.
1614 # ifdef CONFIG_CRASH_DUMP
1615 boot_cpu_physical_apicid
= read_apic_id();
1618 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1621 #ifdef CONFIG_X86_IO_APIC
1623 * Now enable IO-APICs, actually call clear_IO_APIC
1624 * We need clear_IO_APIC before enabling error vector
1626 if (!skip_ioapic_setup
&& nr_ioapics
)
1630 end_local_APIC_setup();
1632 #ifdef CONFIG_X86_IO_APIC
1633 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1637 localise_nmi_watchdog();
1640 localise_nmi_watchdog();
1644 #ifdef CONFIG_X86_64
1645 check_nmi_watchdog();
1652 * Local APIC interrupts
1656 * This interrupt should _never_ happen with our APIC/SMP architecture
1658 void smp_spurious_interrupt(struct pt_regs
*regs
)
1665 * Check if this really is a spurious interrupt and ACK it
1666 * if it is a vectored one. Just in case...
1667 * Spurious interrupts should not be ACKed.
1669 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1670 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1673 inc_irq_stat(irq_spurious_count
);
1675 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1676 pr_info("spurious APIC interrupt on CPU#%d, "
1677 "should never happen.\n", smp_processor_id());
1682 * This interrupt should never happen with our APIC/SMP architecture
1684 void smp_error_interrupt(struct pt_regs
*regs
)
1690 /* First tickle the hardware, only then report what went on. -- REW */
1691 v
= apic_read(APIC_ESR
);
1692 apic_write(APIC_ESR
, 0);
1693 v1
= apic_read(APIC_ESR
);
1695 atomic_inc(&irq_err_count
);
1698 * Here is what the APIC error bits mean:
1700 * 1: Receive CS error
1701 * 2: Send accept error
1702 * 3: Receive accept error
1704 * 5: Send illegal vector
1705 * 6: Received illegal vector
1706 * 7: Illegal register address
1708 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1709 smp_processor_id(), v
, v1
);
1714 * connect_bsp_APIC - attach the APIC to the interrupt system
1716 void __init
connect_bsp_APIC(void)
1718 #ifdef CONFIG_X86_32
1721 * Do not trust the local APIC being empty at bootup.
1725 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1726 * local APIC to INT and NMI lines.
1728 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1729 "enabling APIC mode.\n");
1734 if (apic
->enable_apic_mode
)
1735 apic
->enable_apic_mode();
1739 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1740 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1742 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1745 void disconnect_bsp_APIC(int virt_wire_setup
)
1749 #ifdef CONFIG_X86_32
1752 * Put the board back into PIC mode (has an effect only on
1753 * certain older boards). Note that APIC interrupts, including
1754 * IPIs, won't work beyond this point! The only exception are
1757 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1758 "entering PIC mode.\n");
1765 /* Go back to Virtual Wire compatibility mode */
1767 /* For the spurious interrupt use vector F, and enable it */
1768 value
= apic_read(APIC_SPIV
);
1769 value
&= ~APIC_VECTOR_MASK
;
1770 value
|= APIC_SPIV_APIC_ENABLED
;
1772 apic_write(APIC_SPIV
, value
);
1774 if (!virt_wire_setup
) {
1776 * For LVT0 make it edge triggered, active high,
1777 * external and enabled
1779 value
= apic_read(APIC_LVT0
);
1780 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1781 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1782 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1783 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1784 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1785 apic_write(APIC_LVT0
, value
);
1788 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1792 * For LVT1 make it edge triggered, active high,
1795 value
= apic_read(APIC_LVT1
);
1796 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1797 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1798 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1799 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1800 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1801 apic_write(APIC_LVT1
, value
);
1804 void __cpuinit
generic_processor_info(int apicid
, int version
)
1811 if (version
== 0x0) {
1812 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1813 "fixing up to 0x10. (tell your hw vendor)\n",
1817 apic_version
[apicid
] = version
;
1819 if (num_processors
>= nr_cpu_ids
) {
1820 int max
= nr_cpu_ids
;
1821 int thiscpu
= max
+ disabled_cpus
;
1824 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1825 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1832 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1834 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1836 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1837 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1839 physid_set(apicid
, phys_cpu_present_map
);
1840 if (apicid
== boot_cpu_physical_apicid
) {
1842 * x86_bios_cpu_apicid is required to have processors listed
1843 * in same order as logical cpu numbers. Hence the first
1844 * entry is BSP, and so on.
1848 if (apicid
> max_physical_apicid
)
1849 max_physical_apicid
= apicid
;
1851 #ifdef CONFIG_X86_32
1853 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1854 * but we need to work other dependencies like SMP_SUSPEND etc
1855 * before this can be done without some confusion.
1856 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1857 * - Ashok Raj <ashok.raj@intel.com>
1859 if (max_physical_apicid
>= 8) {
1860 switch (boot_cpu_data
.x86_vendor
) {
1861 case X86_VENDOR_INTEL
:
1862 if (!APIC_XAPIC(version
)) {
1866 /* If P4 and above fall through */
1867 case X86_VENDOR_AMD
:
1873 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1874 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1875 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1878 set_cpu_possible(cpu
, true);
1879 set_cpu_present(cpu
, true);
1882 int hard_smp_processor_id(void)
1884 return read_apic_id();
1887 void default_init_apic_ldr(void)
1891 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1892 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1893 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1894 apic_write(APIC_LDR
, val
);
1897 #ifdef CONFIG_X86_32
1898 int default_apicid_to_node(int logical_apicid
)
1901 return apicid_2_node
[hard_smp_processor_id()];
1915 * 'active' is true if the local APIC was enabled by us and
1916 * not the BIOS; this signifies that we are also responsible
1917 * for disabling it before entering apm/acpi suspend
1920 /* r/w apic fields */
1921 unsigned int apic_id
;
1922 unsigned int apic_taskpri
;
1923 unsigned int apic_ldr
;
1924 unsigned int apic_dfr
;
1925 unsigned int apic_spiv
;
1926 unsigned int apic_lvtt
;
1927 unsigned int apic_lvtpc
;
1928 unsigned int apic_lvt0
;
1929 unsigned int apic_lvt1
;
1930 unsigned int apic_lvterr
;
1931 unsigned int apic_tmict
;
1932 unsigned int apic_tdcr
;
1933 unsigned int apic_thmr
;
1936 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1938 unsigned long flags
;
1941 if (!apic_pm_state
.active
)
1944 maxlvt
= lapic_get_maxlvt();
1946 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1947 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1948 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1949 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1950 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1951 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1953 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1954 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1955 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1956 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1957 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1958 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1959 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1961 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1964 local_irq_save(flags
);
1965 disable_local_APIC();
1966 #ifdef CONFIG_INTR_REMAP
1967 if (intr_remapping_enabled
)
1968 disable_intr_remapping();
1970 local_irq_restore(flags
);
1974 static int lapic_resume(struct sys_device
*dev
)
1977 unsigned long flags
;
1980 #ifdef CONFIG_INTR_REMAP
1982 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1984 if (!apic_pm_state
.active
)
1987 local_irq_save(flags
);
1989 ioapic_entries
= alloc_ioapic_entries();
1990 if (!ioapic_entries
) {
1991 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
1995 ret
= save_IO_APIC_setup(ioapic_entries
);
1997 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
1998 free_ioapic_entries(ioapic_entries
);
2002 mask_IO_APIC_setup(ioapic_entries
);
2007 if (!apic_pm_state
.active
)
2010 local_irq_save(flags
);
2017 * Make sure the APICBASE points to the right address
2019 * FIXME! This will be wrong if we ever support suspend on
2020 * SMP! We'll need to do this as part of the CPU restore!
2022 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2023 l
&= ~MSR_IA32_APICBASE_BASE
;
2024 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2025 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2028 maxlvt
= lapic_get_maxlvt();
2029 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2030 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2031 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2032 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2033 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2034 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2035 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2036 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2037 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2039 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2042 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2043 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2044 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2045 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2046 apic_write(APIC_ESR
, 0);
2047 apic_read(APIC_ESR
);
2048 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2049 apic_write(APIC_ESR
, 0);
2050 apic_read(APIC_ESR
);
2052 #ifdef CONFIG_INTR_REMAP
2053 if (intr_remapping_enabled
)
2054 reenable_intr_remapping(EIM_32BIT_APIC_ID
);
2058 restore_IO_APIC_setup(ioapic_entries
);
2059 free_ioapic_entries(ioapic_entries
);
2063 local_irq_restore(flags
);
2070 * This device has no shutdown method - fully functioning local APICs
2071 * are needed on every CPU up until machine_halt/restart/poweroff.
2074 static struct sysdev_class lapic_sysclass
= {
2076 .resume
= lapic_resume
,
2077 .suspend
= lapic_suspend
,
2080 static struct sys_device device_lapic
= {
2082 .cls
= &lapic_sysclass
,
2085 static void __cpuinit
apic_pm_activate(void)
2087 apic_pm_state
.active
= 1;
2090 static int __init
init_lapic_sysfs(void)
2096 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2098 error
= sysdev_class_register(&lapic_sysclass
);
2100 error
= sysdev_register(&device_lapic
);
2104 /* local apic needs to resume before other devices access its registers. */
2105 core_initcall(init_lapic_sysfs
);
2107 #else /* CONFIG_PM */
2109 static void apic_pm_activate(void) { }
2111 #endif /* CONFIG_PM */
2113 #ifdef CONFIG_X86_64
2115 * apic_is_clustered_box() -- Check if we can expect good TSC
2117 * Thus far, the major user of this is IBM's Summit2 series:
2119 * Clustered boxes may have unsynced TSC problems if they are
2120 * multi-chassis. Use available data to take a good guess.
2121 * If in doubt, go HPET.
2123 __cpuinit
int apic_is_clustered_box(void)
2125 int i
, clusters
, zeros
;
2127 u16
*bios_cpu_apicid
;
2128 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2131 * there is not this kind of box with AMD CPU yet.
2132 * Some AMD box with quadcore cpu and 8 sockets apicid
2133 * will be [4, 0x23] or [8, 0x27] could be thought to
2134 * vsmp box still need checking...
2136 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2139 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2140 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2142 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2143 /* are we being called early in kernel startup? */
2144 if (bios_cpu_apicid
) {
2145 id
= bios_cpu_apicid
[i
];
2146 } else if (i
< nr_cpu_ids
) {
2148 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2154 if (id
!= BAD_APICID
)
2155 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2158 /* Problem: Partially populated chassis may not have CPUs in some of
2159 * the APIC clusters they have been allocated. Only present CPUs have
2160 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2161 * Since clusters are allocated sequentially, count zeros only if
2162 * they are bounded by ones.
2166 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2167 if (test_bit(i
, clustermap
)) {
2168 clusters
+= 1 + zeros
;
2174 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2175 * not guaranteed to be synced between boards
2177 if (is_vsmp_box() && clusters
> 1)
2181 * If clusters > 2, then should be multi-chassis.
2182 * May have to revisit this when multi-core + hyperthreaded CPUs come
2183 * out, but AFAIK this will work even for them.
2185 return (clusters
> 2);
2190 * APIC command line parameters
2192 static int __init
setup_disableapic(char *arg
)
2195 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2198 early_param("disableapic", setup_disableapic
);
2200 /* same as disableapic, for compatibility */
2201 static int __init
setup_nolapic(char *arg
)
2203 return setup_disableapic(arg
);
2205 early_param("nolapic", setup_nolapic
);
2207 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2209 local_apic_timer_c2_ok
= 1;
2212 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2214 static int __init
parse_disable_apic_timer(char *arg
)
2216 disable_apic_timer
= 1;
2219 early_param("noapictimer", parse_disable_apic_timer
);
2221 static int __init
parse_nolapic_timer(char *arg
)
2223 disable_apic_timer
= 1;
2226 early_param("nolapic_timer", parse_nolapic_timer
);
2228 static int __init
apic_set_verbosity(char *arg
)
2231 #ifdef CONFIG_X86_64
2232 skip_ioapic_setup
= 0;
2238 if (strcmp("debug", arg
) == 0)
2239 apic_verbosity
= APIC_DEBUG
;
2240 else if (strcmp("verbose", arg
) == 0)
2241 apic_verbosity
= APIC_VERBOSE
;
2243 pr_warning("APIC Verbosity level %s not recognised"
2244 " use apic=verbose or apic=debug\n", arg
);
2250 early_param("apic", apic_set_verbosity
);
2252 static int __init
lapic_insert_resource(void)
2257 /* Put local APIC into the resource map. */
2258 lapic_resource
.start
= apic_phys
;
2259 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2260 insert_resource(&iomem_resource
, &lapic_resource
);
2266 * need call insert after e820_reserve_resources()
2267 * that is using request_resource
2269 late_initcall(lapic_insert_resource
);