2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
51 unsigned int num_processors
;
53 unsigned disabled_cpus __cpuinitdata
;
55 /* Processor that is doing the boot up */
56 unsigned int boot_cpu_physical_apicid
= -1U;
59 * The highest APIC ID seen during enumeration.
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
65 * If there's an APIC ID above 8, we use physical addressing.
67 unsigned int max_physical_apicid
;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map
;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
78 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
84 * Knob to control our willingness to enable the local APIC.
88 static int force_enable_local_apic
;
90 * APIC command line parameters
92 static int __init
parse_lapic(char *arg
)
94 force_enable_local_apic
= 1;
97 early_param("lapic", parse_lapic
);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase
;
102 * Handle interrupt mode configuration register (IMCR).
103 * This register controls whether the interrupt signals
104 * that reach the BSP come from the master PIC or from the
105 * local APIC. Before entering Symmetric I/O Mode, either
106 * the BIOS or the operating system must switch out of
107 * PIC Mode by changing the IMCR.
109 static inline void imcr_pic_to_apic(void)
111 /* select IMCR register */
113 /* NMI and 8259 INTR go through APIC */
117 static inline void imcr_apic_to_pic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go directly to BSP */
127 static int apic_calibrate_pmtmr __initdata
;
128 static __init
int setup_apicpmtimer(char *s
)
130 apic_calibrate_pmtmr
= 1;
134 __setup("apicpmtimer", setup_apicpmtimer
);
138 #ifdef CONFIG_X86_X2APIC
139 /* x2apic enabled before OS handover */
140 static int x2apic_preenabled
;
141 static int disable_x2apic
;
142 static __init
int setup_nox2apic(char *str
)
144 if (x2apic_enabled()) {
145 pr_warning("Bios already enabled x2apic, "
146 "can't enforce nox2apic");
151 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
154 early_param("nox2apic", setup_nox2apic
);
157 unsigned long mp_lapic_addr
;
159 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
160 static int disable_apic_timer __cpuinitdata
;
161 /* Local APIC timer works in C2 */
162 int local_apic_timer_c2_ok
;
163 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
165 int first_system_vector
= 0xfe;
168 * Debug level, exported for io_apic.c
170 unsigned int apic_verbosity
;
174 /* Have we found an MP table */
175 int smp_found_config
;
177 static struct resource lapic_resource
= {
178 .name
= "Local APIC",
179 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
182 static unsigned int calibration_result
;
184 static int lapic_next_event(unsigned long delta
,
185 struct clock_event_device
*evt
);
186 static void lapic_timer_setup(enum clock_event_mode mode
,
187 struct clock_event_device
*evt
);
188 static void lapic_timer_broadcast(const struct cpumask
*mask
);
189 static void apic_pm_activate(void);
192 * The local apic timer can be used for any function which is CPU local.
194 static struct clock_event_device lapic_clockevent
= {
196 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
197 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
199 .set_mode
= lapic_timer_setup
,
200 .set_next_event
= lapic_next_event
,
201 .broadcast
= lapic_timer_broadcast
,
205 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
207 static unsigned long apic_phys
;
210 * Get the LAPIC version
212 static inline int lapic_get_version(void)
214 return GET_APIC_VERSION(apic_read(APIC_LVR
));
218 * Check, if the APIC is integrated or a separate chip
220 static inline int lapic_is_integrated(void)
225 return APIC_INTEGRATED(lapic_get_version());
230 * Check, whether this is a modern or a first generation APIC
232 static int modern_apic(void)
234 /* AMD systems use old APIC versions, so check the CPU */
235 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
236 boot_cpu_data
.x86
>= 0xf)
238 return lapic_get_version() >= 0x14;
242 * bare function to substitute write operation
243 * and it's _that_ fast :)
245 void native_apic_write_dummy(u32 reg
, u32 v
)
247 WARN_ON_ONCE((cpu_has_apic
|| !disable_apic
));
251 * right after this call apic->write doesn't do anything
252 * note that there is no restore operation it works one way
254 void apic_disable(void)
256 apic
->write
= native_apic_write_dummy
;
259 void native_apic_wait_icr_idle(void)
261 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
265 u32
native_safe_apic_wait_icr_idle(void)
272 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
276 } while (timeout
++ < 1000);
281 void native_apic_icr_write(u32 low
, u32 id
)
283 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
284 apic_write(APIC_ICR
, low
);
287 u64
native_apic_icr_read(void)
291 icr2
= apic_read(APIC_ICR2
);
292 icr1
= apic_read(APIC_ICR
);
294 return icr1
| ((u64
)icr2
<< 32);
298 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
300 void __cpuinit
enable_NMI_through_LVT0(void)
304 /* unmask and set to NMI */
307 /* Level triggered for 82489DX (32bit mode) */
308 if (!lapic_is_integrated())
309 v
|= APIC_LVT_LEVEL_TRIGGER
;
311 apic_write(APIC_LVT0
, v
);
316 * get_physical_broadcast - Get number of physical broadcast IDs
318 int get_physical_broadcast(void)
320 return modern_apic() ? 0xff : 0xf;
325 * lapic_get_maxlvt - get the maximum number of local vector table entries
327 int lapic_get_maxlvt(void)
331 v
= apic_read(APIC_LVR
);
333 * - we always have APIC integrated on 64bit mode
334 * - 82489DXs do not report # of LVT entries
336 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
344 #define APIC_DIVISOR 16
347 * This function sets up the local APIC timer, with a timeout of
348 * 'clocks' APIC bus clock. During calibration we actually call
349 * this function twice on the boot CPU, once with a bogus timeout
350 * value, second time for real. The other (noncalibrating) CPUs
351 * call this function only once, with the real, calibrated value.
353 * We do reads before writes even if unnecessary, to get around the
354 * P5 APIC double write bug.
356 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
358 unsigned int lvtt_value
, tmp_value
;
360 lvtt_value
= LOCAL_TIMER_VECTOR
;
362 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
363 if (!lapic_is_integrated())
364 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
367 lvtt_value
|= APIC_LVT_MASKED
;
369 apic_write(APIC_LVTT
, lvtt_value
);
374 tmp_value
= apic_read(APIC_TDCR
);
375 apic_write(APIC_TDCR
,
376 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
380 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
384 * Setup extended LVT, AMD specific (K8, family 10h)
386 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
387 * MCE interrupts are supported. Thus MCE offset must be set to 0.
389 * If mask=1, the LVT entry does not generate interrupts while mask=0
390 * enables the vector. See also the BKDGs.
393 #define APIC_EILVT_LVTOFF_MCE 0
394 #define APIC_EILVT_LVTOFF_IBS 1
396 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
398 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVTn(0);
399 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
404 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
406 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
407 return APIC_EILVT_LVTOFF_MCE
;
410 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
412 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
413 return APIC_EILVT_LVTOFF_IBS
;
415 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
418 * Program the next event, relative to now
420 static int lapic_next_event(unsigned long delta
,
421 struct clock_event_device
*evt
)
423 apic_write(APIC_TMICT
, delta
);
428 * Setup the lapic timer in periodic or oneshot mode
430 static void lapic_timer_setup(enum clock_event_mode mode
,
431 struct clock_event_device
*evt
)
436 /* Lapic used as dummy for broadcast ? */
437 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
440 local_irq_save(flags
);
443 case CLOCK_EVT_MODE_PERIODIC
:
444 case CLOCK_EVT_MODE_ONESHOT
:
445 __setup_APIC_LVTT(calibration_result
,
446 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
448 case CLOCK_EVT_MODE_UNUSED
:
449 case CLOCK_EVT_MODE_SHUTDOWN
:
450 v
= apic_read(APIC_LVTT
);
451 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
452 apic_write(APIC_LVTT
, v
);
453 apic_write(APIC_TMICT
, 0xffffffff);
455 case CLOCK_EVT_MODE_RESUME
:
456 /* Nothing to do here */
460 local_irq_restore(flags
);
464 * Local APIC timer broadcast function
466 static void lapic_timer_broadcast(const struct cpumask
*mask
)
469 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
474 * Setup the local APIC timer for this CPU. Copy the initilized values
475 * of the boot CPU and register the clock event in the framework.
477 static void __cpuinit
setup_APIC_timer(void)
479 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
481 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
482 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
483 /* Make LAPIC timer preferrable over percpu HPET */
484 lapic_clockevent
.rating
= 150;
487 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
488 levt
->cpumask
= cpumask_of(smp_processor_id());
490 clockevents_register_device(levt
);
494 * In this functions we calibrate APIC bus clocks to the external timer.
496 * We want to do the calibration only once since we want to have local timer
497 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
500 * This was previously done by reading the PIT/HPET and waiting for a wrap
501 * around to find out, that a tick has elapsed. I have a box, where the PIT
502 * readout is broken, so it never gets out of the wait loop again. This was
503 * also reported by others.
505 * Monitoring the jiffies value is inaccurate and the clockevents
506 * infrastructure allows us to do a simple substitution of the interrupt
509 * The calibration routine also uses the pm_timer when possible, as the PIT
510 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
511 * back to normal later in the boot process).
514 #define LAPIC_CAL_LOOPS (HZ/10)
516 static __initdata
int lapic_cal_loops
= -1;
517 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
518 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
519 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
520 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
523 * Temporary interrupt handler.
525 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
527 unsigned long long tsc
= 0;
528 long tapic
= apic_read(APIC_TMCCT
);
529 unsigned long pm
= acpi_pm_read_early();
534 switch (lapic_cal_loops
++) {
536 lapic_cal_t1
= tapic
;
537 lapic_cal_tsc1
= tsc
;
539 lapic_cal_j1
= jiffies
;
542 case LAPIC_CAL_LOOPS
:
543 lapic_cal_t2
= tapic
;
544 lapic_cal_tsc2
= tsc
;
545 if (pm
< lapic_cal_pm1
)
546 pm
+= ACPI_PM_OVRRUN
;
548 lapic_cal_j2
= jiffies
;
554 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
556 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
557 const long pm_thresh
= pm_100ms
/ 100;
561 #ifndef CONFIG_X86_PM_TIMER
565 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
567 /* Check, if the PM timer is available */
571 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
573 if (deltapm
> (pm_100ms
- pm_thresh
) &&
574 deltapm
< (pm_100ms
+ pm_thresh
)) {
575 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
579 res
= (((u64
)deltapm
) * mult
) >> 22;
580 do_div(res
, 1000000);
581 pr_warning("APIC calibration not consistent "
582 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
584 /* Correct the lapic counter value */
585 res
= (((u64
)(*delta
)) * pm_100ms
);
586 do_div(res
, deltapm
);
587 pr_info("APIC delta adjusted to PM-Timer: "
588 "%lu (%ld)\n", (unsigned long)res
, *delta
);
591 /* Correct the tsc counter value */
593 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
594 do_div(res
, deltapm
);
595 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
596 "PM-Timer: %lu (%ld) \n",
597 (unsigned long)res
, *deltatsc
);
598 *deltatsc
= (long)res
;
604 static int __init
calibrate_APIC_clock(void)
606 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
607 void (*real_handler
)(struct clock_event_device
*dev
);
608 unsigned long deltaj
;
609 long delta
, deltatsc
;
610 int pm_referenced
= 0;
614 /* Replace the global interrupt handler */
615 real_handler
= global_clock_event
->event_handler
;
616 global_clock_event
->event_handler
= lapic_cal_handler
;
619 * Setup the APIC counter to maximum. There is no way the lapic
620 * can underflow in the 100ms detection time frame
622 __setup_APIC_LVTT(0xffffffff, 0, 0);
624 /* Let the interrupts run */
627 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
632 /* Restore the real event handler */
633 global_clock_event
->event_handler
= real_handler
;
635 /* Build delta t1-t2 as apic timer counts down */
636 delta
= lapic_cal_t1
- lapic_cal_t2
;
637 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
639 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
641 /* we trust the PM based calibration if possible */
642 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
645 /* Calculate the scaled math multiplication factor */
646 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
647 lapic_clockevent
.shift
);
648 lapic_clockevent
.max_delta_ns
=
649 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
650 lapic_clockevent
.min_delta_ns
=
651 clockevent_delta2ns(0xF, &lapic_clockevent
);
653 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
655 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
656 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
657 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
661 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
663 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
664 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
667 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
669 calibration_result
/ (1000000 / HZ
),
670 calibration_result
% (1000000 / HZ
));
673 * Do a sanity check on the APIC calibration result
675 if (calibration_result
< (1000000 / HZ
)) {
677 pr_warning("APIC frequency too slow, disabling apic timer\n");
681 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
684 * PM timer calibration failed or not turned on
685 * so lets try APIC timer based calibration
687 if (!pm_referenced
) {
688 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
691 * Setup the apic timer manually
693 levt
->event_handler
= lapic_cal_handler
;
694 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
695 lapic_cal_loops
= -1;
697 /* Let the interrupts run */
700 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
703 /* Stop the lapic timer */
704 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
707 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
708 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
710 /* Check, if the jiffies result is consistent */
711 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
712 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
714 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
718 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
719 pr_warning("APIC timer disabled due to verification failure\n");
727 * Setup the boot APIC
729 * Calibrate and verify the result.
731 void __init
setup_boot_APIC_clock(void)
734 * The local apic timer can be disabled via the kernel
735 * commandline or from the CPU detection code. Register the lapic
736 * timer as a dummy clock event source on SMP systems, so the
737 * broadcast mechanism is used. On UP systems simply ignore it.
739 if (disable_apic_timer
) {
740 pr_info("Disabling APIC timer\n");
741 /* No broadcast on UP ! */
742 if (num_possible_cpus() > 1) {
743 lapic_clockevent
.mult
= 1;
749 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
750 "calibrating APIC timer ...\n");
752 if (calibrate_APIC_clock()) {
753 /* No broadcast on UP ! */
754 if (num_possible_cpus() > 1)
760 * If nmi_watchdog is set to IO_APIC, we need the
761 * PIT/HPET going. Otherwise register lapic as a dummy
764 if (nmi_watchdog
!= NMI_IO_APIC
)
765 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
767 pr_warning("APIC timer registered as dummy,"
768 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
770 /* Setup the lapic or request the broadcast */
774 void __cpuinit
setup_secondary_APIC_clock(void)
780 * The guts of the apic timer interrupt
782 static void local_apic_timer_interrupt(void)
784 int cpu
= smp_processor_id();
785 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
788 * Normally we should not be here till LAPIC has been initialized but
789 * in some cases like kdump, its possible that there is a pending LAPIC
790 * timer interrupt from previous kernel's context and is delivered in
791 * new kernel the moment interrupts are enabled.
793 * Interrupts are enabled early and LAPIC is setup much later, hence
794 * its possible that when we get here evt->event_handler is NULL.
795 * Check for event_handler being NULL and discard the interrupt as
798 if (!evt
->event_handler
) {
799 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
801 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
806 * the NMI deadlock-detector uses this.
808 inc_irq_stat(apic_timer_irqs
);
810 evt
->event_handler(evt
);
814 * Local APIC timer interrupt. This is the most natural way for doing
815 * local interrupts, but local timer interrupts can be emulated by
816 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
818 * [ if a single-CPU system runs an SMP kernel then we call the local
819 * interrupt as well. Thus we cannot inline the local irq ... ]
821 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
823 struct pt_regs
*old_regs
= set_irq_regs(regs
);
826 * NOTE! We'd better ACK the irq immediately,
827 * because timer handling can be slow.
831 * update_process_times() expects us to have done irq_enter().
832 * Besides, if we don't timer interrupts ignore the global
833 * interrupt lock, which is the WrongThing (tm) to do.
837 local_apic_timer_interrupt();
840 set_irq_regs(old_regs
);
843 int setup_profiling_timer(unsigned int multiplier
)
849 * Local APIC start and shutdown
853 * clear_local_APIC - shutdown the local APIC
855 * This is called, when a CPU is disabled and before rebooting, so the state of
856 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
857 * leftovers during boot.
859 void clear_local_APIC(void)
864 /* APIC hasn't been mapped yet */
865 if (!x2apic_mode
&& !apic_phys
)
868 maxlvt
= lapic_get_maxlvt();
870 * Masking an LVT entry can trigger a local APIC error
871 * if the vector is zero. Mask LVTERR first to prevent this.
874 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
875 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
878 * Careful: we have to set masks only first to deassert
879 * any level-triggered sources.
881 v
= apic_read(APIC_LVTT
);
882 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
883 v
= apic_read(APIC_LVT0
);
884 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
885 v
= apic_read(APIC_LVT1
);
886 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
888 v
= apic_read(APIC_LVTPC
);
889 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
892 /* lets not touch this if we didn't frob it */
893 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
895 v
= apic_read(APIC_LVTTHMR
);
896 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
899 #ifdef CONFIG_X86_MCE_INTEL
901 v
= apic_read(APIC_LVTCMCI
);
902 if (!(v
& APIC_LVT_MASKED
))
903 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
908 * Clean APIC state for other OSs:
910 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
911 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
912 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
914 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
916 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
918 /* Integrated APIC (!82489DX) ? */
919 if (lapic_is_integrated()) {
921 /* Clear ESR due to Pentium errata 3AP and 11AP */
922 apic_write(APIC_ESR
, 0);
928 * disable_local_APIC - clear and disable the local APIC
930 void disable_local_APIC(void)
934 /* APIC hasn't been mapped yet */
941 * Disable APIC (implies clearing of registers
944 value
= apic_read(APIC_SPIV
);
945 value
&= ~APIC_SPIV_APIC_ENABLED
;
946 apic_write(APIC_SPIV
, value
);
950 * When LAPIC was disabled by the BIOS and enabled by the kernel,
951 * restore the disabled state.
953 if (enabled_via_apicbase
) {
956 rdmsr(MSR_IA32_APICBASE
, l
, h
);
957 l
&= ~MSR_IA32_APICBASE_ENABLE
;
958 wrmsr(MSR_IA32_APICBASE
, l
, h
);
964 * If Linux enabled the LAPIC against the BIOS default disable it down before
965 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
966 * not power-off. Additionally clear all LVT entries before disable_local_APIC
967 * for the case where Linux didn't enable the LAPIC.
969 void lapic_shutdown(void)
976 local_irq_save(flags
);
979 if (!enabled_via_apicbase
)
983 disable_local_APIC();
986 local_irq_restore(flags
);
990 * This is to verify that we're looking at a real local APIC.
991 * Check these against your board if the CPUs aren't getting
992 * started for no apparent reason.
994 int __init
verify_local_APIC(void)
996 unsigned int reg0
, reg1
;
999 * The version register is read-only in a real APIC.
1001 reg0
= apic_read(APIC_LVR
);
1002 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1003 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1004 reg1
= apic_read(APIC_LVR
);
1005 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1008 * The two version reads above should print the same
1009 * numbers. If the second one is different, then we
1010 * poke at a non-APIC.
1016 * Check if the version looks reasonably.
1018 reg1
= GET_APIC_VERSION(reg0
);
1019 if (reg1
== 0x00 || reg1
== 0xff)
1021 reg1
= lapic_get_maxlvt();
1022 if (reg1
< 0x02 || reg1
== 0xff)
1026 * The ID register is read/write in a real APIC.
1028 reg0
= apic_read(APIC_ID
);
1029 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1030 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1031 reg1
= apic_read(APIC_ID
);
1032 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1033 apic_write(APIC_ID
, reg0
);
1034 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1038 * The next two are just to see if we have sane values.
1039 * They're only really relevant if we're in Virtual Wire
1040 * compatibility mode, but most boxes are anymore.
1042 reg0
= apic_read(APIC_LVT0
);
1043 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1044 reg1
= apic_read(APIC_LVT1
);
1045 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1051 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1053 void __init
sync_Arb_IDs(void)
1056 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1059 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1065 apic_wait_icr_idle();
1067 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1068 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1069 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1073 * An initial setup of the virtual wire mode.
1075 void __init
init_bsp_APIC(void)
1080 * Don't do the setup now if we have a SMP BIOS as the
1081 * through-I/O-APIC virtual wire mode might be active.
1083 if (smp_found_config
|| !cpu_has_apic
)
1087 * Do not trust the local APIC being empty at bootup.
1094 value
= apic_read(APIC_SPIV
);
1095 value
&= ~APIC_VECTOR_MASK
;
1096 value
|= APIC_SPIV_APIC_ENABLED
;
1098 #ifdef CONFIG_X86_32
1099 /* This bit is reserved on P4/Xeon and should be cleared */
1100 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1101 (boot_cpu_data
.x86
== 15))
1102 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1105 value
|= APIC_SPIV_FOCUS_DISABLED
;
1106 value
|= SPURIOUS_APIC_VECTOR
;
1107 apic_write(APIC_SPIV
, value
);
1110 * Set up the virtual wire mode.
1112 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1113 value
= APIC_DM_NMI
;
1114 if (!lapic_is_integrated()) /* 82489DX */
1115 value
|= APIC_LVT_LEVEL_TRIGGER
;
1116 apic_write(APIC_LVT1
, value
);
1119 static void __cpuinit
lapic_setup_esr(void)
1121 unsigned int oldvalue
, value
, maxlvt
;
1123 if (!lapic_is_integrated()) {
1124 pr_info("No ESR for 82489DX.\n");
1128 if (apic
->disable_esr
) {
1130 * Something untraceable is creating bad interrupts on
1131 * secondary quads ... for the moment, just leave the
1132 * ESR disabled - we can't do anything useful with the
1133 * errors anyway - mbligh
1135 pr_info("Leaving ESR disabled.\n");
1139 maxlvt
= lapic_get_maxlvt();
1140 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1141 apic_write(APIC_ESR
, 0);
1142 oldvalue
= apic_read(APIC_ESR
);
1144 /* enables sending errors */
1145 value
= ERROR_APIC_VECTOR
;
1146 apic_write(APIC_LVTERR
, value
);
1149 * spec says clear errors after enabling vector.
1152 apic_write(APIC_ESR
, 0);
1153 value
= apic_read(APIC_ESR
);
1154 if (value
!= oldvalue
)
1155 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1156 "vector: 0x%08x after: 0x%08x\n",
1162 * setup_local_APIC - setup the local APIC
1164 void __cpuinit
setup_local_APIC(void)
1170 arch_disable_smp_support();
1174 #ifdef CONFIG_X86_32
1175 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1176 if (lapic_is_integrated() && apic
->disable_esr
) {
1177 apic_write(APIC_ESR
, 0);
1178 apic_write(APIC_ESR
, 0);
1179 apic_write(APIC_ESR
, 0);
1180 apic_write(APIC_ESR
, 0);
1187 * Double-check whether this APIC is really registered.
1188 * This is meaningless in clustered apic mode, so we skip it.
1190 if (!apic
->apic_id_registered())
1194 * Intel recommends to set DFR, LDR and TPR before enabling
1195 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1196 * document number 292116). So here it goes...
1198 apic
->init_apic_ldr();
1201 * Set Task Priority to 'accept all'. We never change this
1204 value
= apic_read(APIC_TASKPRI
);
1205 value
&= ~APIC_TPRI_MASK
;
1206 apic_write(APIC_TASKPRI
, value
);
1209 * After a crash, we no longer service the interrupts and a pending
1210 * interrupt from previous kernel might still have ISR bit set.
1212 * Most probably by now CPU has serviced that pending interrupt and
1213 * it might not have done the ack_APIC_irq() because it thought,
1214 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1215 * does not clear the ISR bit and cpu thinks it has already serivced
1216 * the interrupt. Hence a vector might get locked. It was noticed
1217 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1219 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1220 value
= apic_read(APIC_ISR
+ i
*0x10);
1221 for (j
= 31; j
>= 0; j
--) {
1228 * Now that we are all set up, enable the APIC
1230 value
= apic_read(APIC_SPIV
);
1231 value
&= ~APIC_VECTOR_MASK
;
1235 value
|= APIC_SPIV_APIC_ENABLED
;
1237 #ifdef CONFIG_X86_32
1239 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1240 * certain networking cards. If high frequency interrupts are
1241 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1242 * entry is masked/unmasked at a high rate as well then sooner or
1243 * later IOAPIC line gets 'stuck', no more interrupts are received
1244 * from the device. If focus CPU is disabled then the hang goes
1247 * [ This bug can be reproduced easily with a level-triggered
1248 * PCI Ne2000 networking cards and PII/PIII processors, dual
1252 * Actually disabling the focus CPU check just makes the hang less
1253 * frequent as it makes the interrupt distributon model be more
1254 * like LRU than MRU (the short-term load is more even across CPUs).
1255 * See also the comment in end_level_ioapic_irq(). --macro
1259 * - enable focus processor (bit==0)
1260 * - 64bit mode always use processor focus
1261 * so no need to set it
1263 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1267 * Set spurious IRQ vector
1269 value
|= SPURIOUS_APIC_VECTOR
;
1270 apic_write(APIC_SPIV
, value
);
1273 * Set up LVT0, LVT1:
1275 * set up through-local-APIC on the BP's LINT0. This is not
1276 * strictly necessary in pure symmetric-IO mode, but sometimes
1277 * we delegate interrupts to the 8259A.
1280 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1282 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1283 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1284 value
= APIC_DM_EXTINT
;
1285 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1286 smp_processor_id());
1288 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1289 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1290 smp_processor_id());
1292 apic_write(APIC_LVT0
, value
);
1295 * only the BP should see the LINT1 NMI signal, obviously.
1297 if (!smp_processor_id())
1298 value
= APIC_DM_NMI
;
1300 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1301 if (!lapic_is_integrated()) /* 82489DX */
1302 value
|= APIC_LVT_LEVEL_TRIGGER
;
1303 apic_write(APIC_LVT1
, value
);
1307 #ifdef CONFIG_X86_MCE_INTEL
1308 /* Recheck CMCI information after local APIC is up on CPU #0 */
1309 if (smp_processor_id() == 0)
1314 void __cpuinit
end_local_APIC_setup(void)
1318 #ifdef CONFIG_X86_32
1321 /* Disable the local apic timer */
1322 value
= apic_read(APIC_LVTT
);
1323 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1324 apic_write(APIC_LVTT
, value
);
1328 setup_apic_nmi_watchdog(NULL
);
1332 #ifdef CONFIG_X86_X2APIC
1333 void check_x2apic(void)
1335 if (x2apic_enabled()) {
1336 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1337 x2apic_preenabled
= x2apic_mode
= 1;
1341 void enable_x2apic(void)
1348 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1349 if (!(msr
& X2APIC_ENABLE
)) {
1350 pr_info("Enabling x2apic\n");
1351 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1354 #endif /* CONFIG_X86_X2APIC */
1356 void __init
enable_IR_x2apic(void)
1358 #ifdef CONFIG_INTR_REMAP
1360 unsigned long flags
;
1361 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1363 ret
= dmar_table_init();
1365 pr_debug("dmar_table_init() failed with %d:\n", ret
);
1369 if (!intr_remapping_supported()) {
1370 pr_debug("intr-remapping not supported\n");
1375 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1376 pr_info("Skipped enabling intr-remap because of skipping "
1381 ioapic_entries
= alloc_ioapic_entries();
1382 if (!ioapic_entries
) {
1383 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1387 ret
= save_IO_APIC_setup(ioapic_entries
);
1389 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1393 local_irq_save(flags
);
1394 mask_IO_APIC_setup(ioapic_entries
);
1397 ret
= enable_intr_remapping(x2apic_supported());
1401 pr_info("Enabled Interrupt-remapping\n");
1403 if (x2apic_supported() && !x2apic_mode
) {
1406 pr_info("Enabled x2apic\n");
1412 * IR enabling failed
1414 restore_IO_APIC_setup(ioapic_entries
);
1417 local_irq_restore(flags
);
1421 free_ioapic_entries(ioapic_entries
);
1427 if (x2apic_preenabled
)
1428 panic("x2apic enabled by bios. But IR enabling failed");
1429 else if (cpu_has_x2apic
)
1430 pr_info("Not enabling x2apic,Intr-remapping\n");
1432 if (!cpu_has_x2apic
)
1435 if (x2apic_preenabled
)
1436 panic("x2apic enabled prior OS handover,"
1437 " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP");
1444 #ifdef CONFIG_X86_64
1446 * Detect and enable local APICs on non-SMP boards.
1447 * Original code written by Keir Fraser.
1448 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1449 * not correctly set up (usually the APIC timer won't work etc.)
1451 static int __init
detect_init_APIC(void)
1453 if (!cpu_has_apic
) {
1454 pr_info("No local APIC present\n");
1458 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1463 * Detect and initialize APIC
1465 static int __init
detect_init_APIC(void)
1469 /* Disabled by kernel option? */
1473 switch (boot_cpu_data
.x86_vendor
) {
1474 case X86_VENDOR_AMD
:
1475 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1476 (boot_cpu_data
.x86
>= 15))
1479 case X86_VENDOR_INTEL
:
1480 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1481 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1488 if (!cpu_has_apic
) {
1490 * Over-ride BIOS and try to enable the local APIC only if
1491 * "lapic" specified.
1493 if (!force_enable_local_apic
) {
1494 pr_info("Local APIC disabled by BIOS -- "
1495 "you can enable it with \"lapic\"\n");
1499 * Some BIOSes disable the local APIC in the APIC_BASE
1500 * MSR. This can only be done in software for Intel P6 or later
1501 * and AMD K7 (Model > 1) or later.
1503 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1504 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1505 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1506 l
&= ~MSR_IA32_APICBASE_BASE
;
1507 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1508 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1509 enabled_via_apicbase
= 1;
1513 * The APIC feature bit should now be enabled
1516 features
= cpuid_edx(1);
1517 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1518 pr_warning("Could not enable APIC!\n");
1521 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1522 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1524 /* The BIOS may have set up the APIC at some other address */
1525 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1526 if (l
& MSR_IA32_APICBASE_ENABLE
)
1527 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1529 pr_info("Found and enabled local APIC!\n");
1536 pr_info("No local APIC present or hardware disabled\n");
1541 #ifdef CONFIG_X86_64
1542 void __init
early_init_lapic_mapping(void)
1544 unsigned long phys_addr
;
1547 * If no local APIC can be found then go out
1548 * : it means there is no mpatable and MADT
1550 if (!smp_found_config
)
1553 phys_addr
= mp_lapic_addr
;
1555 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1556 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1557 APIC_BASE
, phys_addr
);
1560 * Fetch the APIC ID of the BSP in case we have a
1561 * default configuration (or the MP table is broken).
1563 boot_cpu_physical_apicid
= read_apic_id();
1568 * init_apic_mappings - initialize APIC mappings
1570 void __init
init_apic_mappings(void)
1572 unsigned int new_apicid
;
1575 boot_cpu_physical_apicid
= read_apic_id();
1580 * If no local APIC can be found then set up a fake all
1581 * zeroes page to simulate the local APIC and another
1582 * one for the IO-APIC.
1584 if (!smp_found_config
&& detect_init_APIC()) {
1585 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1586 apic_phys
= __pa(apic_phys
);
1588 apic_phys
= mp_lapic_addr
;
1590 /* lets check if we may NOP'ify apic operations */
1591 if (!cpu_has_apic
) {
1592 pr_info("APIC: disable apic facility\n");
1598 * acpi lapic path already maps that address in
1599 * acpi_register_lapic_address()
1602 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1604 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1605 APIC_BASE
, apic_phys
);
1607 * Fetch the APIC ID of the BSP in case we have a
1608 * default configuration (or the MP table is broken).
1610 new_apicid
= read_apic_id();
1611 if (boot_cpu_physical_apicid
!= new_apicid
) {
1612 boot_cpu_physical_apicid
= new_apicid
;
1613 apic_version
[new_apicid
] =
1614 GET_APIC_VERSION(apic_read(APIC_LVR
));
1619 * This initializes the IO-APIC and APIC hardware if this is
1622 int apic_version
[MAX_APICS
];
1624 int __init
APIC_init_uniprocessor(void)
1627 pr_info("Apic disabled\n");
1630 #ifdef CONFIG_X86_64
1631 if (!cpu_has_apic
) {
1633 pr_info("Apic disabled by BIOS\n");
1637 if (!smp_found_config
&& !cpu_has_apic
)
1641 * Complain if the BIOS pretends there is one.
1643 if (!cpu_has_apic
&&
1644 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1645 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1646 boot_cpu_physical_apicid
);
1647 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1653 #ifdef CONFIG_X86_64
1654 default_setup_apic_routing();
1657 verify_local_APIC();
1660 #ifdef CONFIG_X86_64
1661 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1664 * Hack: In case of kdump, after a crash, kernel might be booting
1665 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1666 * might be zero if read from MP tables. Get it from LAPIC.
1668 # ifdef CONFIG_CRASH_DUMP
1669 boot_cpu_physical_apicid
= read_apic_id();
1672 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1675 #ifdef CONFIG_X86_IO_APIC
1677 * Now enable IO-APICs, actually call clear_IO_APIC
1678 * We need clear_IO_APIC before enabling error vector
1680 if (!skip_ioapic_setup
&& nr_ioapics
)
1684 end_local_APIC_setup();
1686 #ifdef CONFIG_X86_IO_APIC
1687 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1691 localise_nmi_watchdog();
1694 localise_nmi_watchdog();
1698 #ifdef CONFIG_X86_64
1699 check_nmi_watchdog();
1706 * Local APIC interrupts
1710 * This interrupt should _never_ happen with our APIC/SMP architecture
1712 void smp_spurious_interrupt(struct pt_regs
*regs
)
1719 * Check if this really is a spurious interrupt and ACK it
1720 * if it is a vectored one. Just in case...
1721 * Spurious interrupts should not be ACKed.
1723 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1724 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1727 inc_irq_stat(irq_spurious_count
);
1729 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1730 pr_info("spurious APIC interrupt on CPU#%d, "
1731 "should never happen.\n", smp_processor_id());
1736 * This interrupt should never happen with our APIC/SMP architecture
1738 void smp_error_interrupt(struct pt_regs
*regs
)
1744 /* First tickle the hardware, only then report what went on. -- REW */
1745 v
= apic_read(APIC_ESR
);
1746 apic_write(APIC_ESR
, 0);
1747 v1
= apic_read(APIC_ESR
);
1749 atomic_inc(&irq_err_count
);
1752 * Here is what the APIC error bits mean:
1754 * 1: Receive CS error
1755 * 2: Send accept error
1756 * 3: Receive accept error
1758 * 5: Send illegal vector
1759 * 6: Received illegal vector
1760 * 7: Illegal register address
1762 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1763 smp_processor_id(), v
, v1
);
1768 * connect_bsp_APIC - attach the APIC to the interrupt system
1770 void __init
connect_bsp_APIC(void)
1772 #ifdef CONFIG_X86_32
1775 * Do not trust the local APIC being empty at bootup.
1779 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1780 * local APIC to INT and NMI lines.
1782 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1783 "enabling APIC mode.\n");
1787 if (apic
->enable_apic_mode
)
1788 apic
->enable_apic_mode();
1792 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1793 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1795 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1798 void disconnect_bsp_APIC(int virt_wire_setup
)
1802 #ifdef CONFIG_X86_32
1805 * Put the board back into PIC mode (has an effect only on
1806 * certain older boards). Note that APIC interrupts, including
1807 * IPIs, won't work beyond this point! The only exception are
1810 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1811 "entering PIC mode.\n");
1817 /* Go back to Virtual Wire compatibility mode */
1819 /* For the spurious interrupt use vector F, and enable it */
1820 value
= apic_read(APIC_SPIV
);
1821 value
&= ~APIC_VECTOR_MASK
;
1822 value
|= APIC_SPIV_APIC_ENABLED
;
1824 apic_write(APIC_SPIV
, value
);
1826 if (!virt_wire_setup
) {
1828 * For LVT0 make it edge triggered, active high,
1829 * external and enabled
1831 value
= apic_read(APIC_LVT0
);
1832 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1833 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1834 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1835 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1836 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1837 apic_write(APIC_LVT0
, value
);
1840 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1844 * For LVT1 make it edge triggered, active high,
1847 value
= apic_read(APIC_LVT1
);
1848 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1849 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1850 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1851 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1852 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1853 apic_write(APIC_LVT1
, value
);
1856 void __cpuinit
generic_processor_info(int apicid
, int version
)
1863 if (version
== 0x0) {
1864 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1865 "fixing up to 0x10. (tell your hw vendor)\n",
1869 apic_version
[apicid
] = version
;
1871 if (num_processors
>= nr_cpu_ids
) {
1872 int max
= nr_cpu_ids
;
1873 int thiscpu
= max
+ disabled_cpus
;
1876 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1877 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1884 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1886 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1888 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1889 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1891 physid_set(apicid
, phys_cpu_present_map
);
1892 if (apicid
== boot_cpu_physical_apicid
) {
1894 * x86_bios_cpu_apicid is required to have processors listed
1895 * in same order as logical cpu numbers. Hence the first
1896 * entry is BSP, and so on.
1900 if (apicid
> max_physical_apicid
)
1901 max_physical_apicid
= apicid
;
1903 #ifdef CONFIG_X86_32
1905 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1906 * but we need to work other dependencies like SMP_SUSPEND etc
1907 * before this can be done without some confusion.
1908 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1909 * - Ashok Raj <ashok.raj@intel.com>
1911 if (max_physical_apicid
>= 8) {
1912 switch (boot_cpu_data
.x86_vendor
) {
1913 case X86_VENDOR_INTEL
:
1914 if (!APIC_XAPIC(version
)) {
1918 /* If P4 and above fall through */
1919 case X86_VENDOR_AMD
:
1925 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1926 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1927 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1930 set_cpu_possible(cpu
, true);
1931 set_cpu_present(cpu
, true);
1934 int hard_smp_processor_id(void)
1936 return read_apic_id();
1939 void default_init_apic_ldr(void)
1943 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1944 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1945 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1946 apic_write(APIC_LDR
, val
);
1949 #ifdef CONFIG_X86_32
1950 int default_apicid_to_node(int logical_apicid
)
1953 return apicid_2_node
[hard_smp_processor_id()];
1967 * 'active' is true if the local APIC was enabled by us and
1968 * not the BIOS; this signifies that we are also responsible
1969 * for disabling it before entering apm/acpi suspend
1972 /* r/w apic fields */
1973 unsigned int apic_id
;
1974 unsigned int apic_taskpri
;
1975 unsigned int apic_ldr
;
1976 unsigned int apic_dfr
;
1977 unsigned int apic_spiv
;
1978 unsigned int apic_lvtt
;
1979 unsigned int apic_lvtpc
;
1980 unsigned int apic_lvt0
;
1981 unsigned int apic_lvt1
;
1982 unsigned int apic_lvterr
;
1983 unsigned int apic_tmict
;
1984 unsigned int apic_tdcr
;
1985 unsigned int apic_thmr
;
1988 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1990 unsigned long flags
;
1993 if (!apic_pm_state
.active
)
1996 maxlvt
= lapic_get_maxlvt();
1998 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1999 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2000 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2001 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2002 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2003 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2005 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2006 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2007 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2008 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2009 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2010 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2011 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2013 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2016 local_irq_save(flags
);
2017 disable_local_APIC();
2019 if (intr_remapping_enabled
)
2020 disable_intr_remapping();
2022 local_irq_restore(flags
);
2026 static int lapic_resume(struct sys_device
*dev
)
2029 unsigned long flags
;
2032 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2034 if (!apic_pm_state
.active
)
2037 local_irq_save(flags
);
2038 if (intr_remapping_enabled
) {
2039 ioapic_entries
= alloc_ioapic_entries();
2040 if (!ioapic_entries
) {
2041 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2045 ret
= save_IO_APIC_setup(ioapic_entries
);
2047 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2048 free_ioapic_entries(ioapic_entries
);
2052 mask_IO_APIC_setup(ioapic_entries
);
2060 * Make sure the APICBASE points to the right address
2062 * FIXME! This will be wrong if we ever support suspend on
2063 * SMP! We'll need to do this as part of the CPU restore!
2065 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2066 l
&= ~MSR_IA32_APICBASE_BASE
;
2067 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2068 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2071 maxlvt
= lapic_get_maxlvt();
2072 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2073 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2074 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2075 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2076 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2077 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2078 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2079 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2080 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2082 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2085 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2086 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2087 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2088 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2089 apic_write(APIC_ESR
, 0);
2090 apic_read(APIC_ESR
);
2091 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2092 apic_write(APIC_ESR
, 0);
2093 apic_read(APIC_ESR
);
2095 if (intr_remapping_enabled
) {
2096 reenable_intr_remapping(x2apic_mode
);
2098 restore_IO_APIC_setup(ioapic_entries
);
2099 free_ioapic_entries(ioapic_entries
);
2102 local_irq_restore(flags
);
2108 * This device has no shutdown method - fully functioning local APICs
2109 * are needed on every CPU up until machine_halt/restart/poweroff.
2112 static struct sysdev_class lapic_sysclass
= {
2114 .resume
= lapic_resume
,
2115 .suspend
= lapic_suspend
,
2118 static struct sys_device device_lapic
= {
2120 .cls
= &lapic_sysclass
,
2123 static void __cpuinit
apic_pm_activate(void)
2125 apic_pm_state
.active
= 1;
2128 static int __init
init_lapic_sysfs(void)
2134 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2136 error
= sysdev_class_register(&lapic_sysclass
);
2138 error
= sysdev_register(&device_lapic
);
2142 /* local apic needs to resume before other devices access its registers. */
2143 core_initcall(init_lapic_sysfs
);
2145 #else /* CONFIG_PM */
2147 static void apic_pm_activate(void) { }
2149 #endif /* CONFIG_PM */
2151 #ifdef CONFIG_X86_64
2153 static int __cpuinit
apic_cluster_num(void)
2155 int i
, clusters
, zeros
;
2157 u16
*bios_cpu_apicid
;
2158 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2160 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2161 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2163 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2164 /* are we being called early in kernel startup? */
2165 if (bios_cpu_apicid
) {
2166 id
= bios_cpu_apicid
[i
];
2167 } else if (i
< nr_cpu_ids
) {
2169 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2175 if (id
!= BAD_APICID
)
2176 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2179 /* Problem: Partially populated chassis may not have CPUs in some of
2180 * the APIC clusters they have been allocated. Only present CPUs have
2181 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2182 * Since clusters are allocated sequentially, count zeros only if
2183 * they are bounded by ones.
2187 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2188 if (test_bit(i
, clustermap
)) {
2189 clusters
+= 1 + zeros
;
2198 static int __cpuinitdata multi_checked
;
2199 static int __cpuinitdata multi
;
2201 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2205 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2210 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2212 .callback
= set_multi
,
2213 .ident
= "IBM System Summit2",
2215 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2216 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2222 static void __cpuinit
dmi_check_multi(void)
2227 dmi_check_system(multi_dmi_table
);
2232 * apic_is_clustered_box() -- Check if we can expect good TSC
2234 * Thus far, the major user of this is IBM's Summit2 series:
2235 * Clustered boxes may have unsynced TSC problems if they are
2237 * Use DMI to check them
2239 __cpuinit
int apic_is_clustered_box(void)
2249 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2250 * not guaranteed to be synced between boards
2252 if (apic_cluster_num() > 1)
2260 * APIC command line parameters
2262 static int __init
setup_disableapic(char *arg
)
2265 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2268 early_param("disableapic", setup_disableapic
);
2270 /* same as disableapic, for compatibility */
2271 static int __init
setup_nolapic(char *arg
)
2273 return setup_disableapic(arg
);
2275 early_param("nolapic", setup_nolapic
);
2277 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2279 local_apic_timer_c2_ok
= 1;
2282 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2284 static int __init
parse_disable_apic_timer(char *arg
)
2286 disable_apic_timer
= 1;
2289 early_param("noapictimer", parse_disable_apic_timer
);
2291 static int __init
parse_nolapic_timer(char *arg
)
2293 disable_apic_timer
= 1;
2296 early_param("nolapic_timer", parse_nolapic_timer
);
2298 static int __init
apic_set_verbosity(char *arg
)
2301 #ifdef CONFIG_X86_64
2302 skip_ioapic_setup
= 0;
2308 if (strcmp("debug", arg
) == 0)
2309 apic_verbosity
= APIC_DEBUG
;
2310 else if (strcmp("verbose", arg
) == 0)
2311 apic_verbosity
= APIC_VERBOSE
;
2313 pr_warning("APIC Verbosity level %s not recognised"
2314 " use apic=verbose or apic=debug\n", arg
);
2320 early_param("apic", apic_set_verbosity
);
2322 static int __init
lapic_insert_resource(void)
2327 /* Put local APIC into the resource map. */
2328 lapic_resource
.start
= apic_phys
;
2329 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2330 insert_resource(&iomem_resource
, &lapic_resource
);
2336 * need call insert after e820_reserve_resources()
2337 * that is using request_resource
2339 late_initcall(lapic_insert_resource
);