1 // SPDX-License-Identifier: GPL-2.0-only
3 * Local APIC handling, local APIC timers
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
15 * Mikael Pettersson : PM converted to driver model.
18 #include <linux/perf_event.h>
19 #include <linux/kernel_stat.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/acpi_pmtmr.h>
22 #include <linux/clockchips.h>
23 #include <linux/interrupt.h>
24 #include <linux/memblock.h>
25 #include <linux/ftrace.h>
26 #include <linux/ioport.h>
27 #include <linux/export.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/delay.h>
30 #include <linux/timex.h>
31 #include <linux/i8253.h>
32 #include <linux/dmar.h>
33 #include <linux/init.h>
34 #include <linux/cpu.h>
35 #include <linux/dmi.h>
36 #include <linux/smp.h>
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <asm/pgalloc.h>
44 #include <linux/atomic.h>
45 #include <asm/mpspec.h>
46 #include <asm/i8259.h>
47 #include <asm/proto.h>
48 #include <asm/traps.h>
50 #include <asm/io_apic.h>
58 #include <asm/hypervisor.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/intel-family.h>
61 #include <asm/irq_regs.h>
63 unsigned int num_processors
;
65 unsigned disabled_cpus
;
67 /* Processor that is doing the boot up */
68 unsigned int boot_cpu_physical_apicid
= -1U;
69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid
);
71 u8 boot_cpu_apic_version
;
74 * The highest APIC ID seen during enumeration.
76 static unsigned int max_physical_apicid
;
79 * Bitmask of physically existing CPUs:
81 physid_mask_t phys_cpu_present_map
;
84 * Processor to be disabled specified by kernel parameter
85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
86 * avoid undefined behaviour caused by sending INIT from AP to BSP.
88 static unsigned int disabled_cpu_apicid __read_mostly
= BAD_APICID
;
91 * This variable controls which CPUs receive external NMIs. By default,
92 * external NMIs are delivered only to the BSP.
94 static int apic_extnmi
= APIC_EXTNMI_BSP
;
97 * Map cpu index to physical APIC ID
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_cpu_to_apicid
, BAD_APICID
);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32
, x86_cpu_to_acpiid
, U32_MAX
);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid
);
109 * On x86_32, the mapping between cpu and logical apicid may vary
110 * depending on apic in use. The following early percpu variable is
111 * used for the mapping. This is where the behaviors of x86_64 and 32
112 * actually diverge. Let's keep it ugly for now.
114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid
, BAD_APICID
);
116 /* Local APIC was disabled by the BIOS and enabled by the kernel */
117 static int enabled_via_apicbase
;
120 * Handle interrupt mode configuration register (IMCR).
121 * This register controls whether the interrupt signals
122 * that reach the BSP come from the master PIC or from the
123 * local APIC. Before entering Symmetric I/O Mode, either
124 * the BIOS or the operating system must switch out of
125 * PIC Mode by changing the IMCR.
127 static inline void imcr_pic_to_apic(void)
129 /* select IMCR register */
131 /* NMI and 8259 INTR go through APIC */
135 static inline void imcr_apic_to_pic(void)
137 /* select IMCR register */
139 /* NMI and 8259 INTR go directly to BSP */
145 * Knob to control our willingness to enable the local APIC.
149 static int force_enable_local_apic __initdata
;
152 * APIC command line parameters
154 static int __init
parse_lapic(char *arg
)
156 if (IS_ENABLED(CONFIG_X86_32
) && !arg
)
157 force_enable_local_apic
= 1;
158 else if (arg
&& !strncmp(arg
, "notscdeadline", 13))
159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
162 early_param("lapic", parse_lapic
);
165 static int apic_calibrate_pmtmr __initdata
;
166 static __init
int setup_apicpmtimer(char *s
)
168 apic_calibrate_pmtmr
= 1;
172 __setup("apicpmtimer", setup_apicpmtimer
);
175 unsigned long mp_lapic_addr
;
177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
178 static int disable_apic_timer __initdata
;
179 /* Local APIC timer works in C2 */
180 int local_apic_timer_c2_ok
;
181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
184 * Debug level, exported for io_apic.c
190 /* Have we found an MP table */
191 int smp_found_config
;
193 static struct resource lapic_resource
= {
194 .name
= "Local APIC",
195 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
198 unsigned int lapic_timer_period
= 0;
200 static void apic_pm_activate(void);
202 static unsigned long apic_phys
;
205 * Get the LAPIC version
207 static inline int lapic_get_version(void)
209 return GET_APIC_VERSION(apic_read(APIC_LVR
));
213 * Check, if the APIC is integrated or a separate chip
215 static inline int lapic_is_integrated(void)
217 return APIC_INTEGRATED(lapic_get_version());
221 * Check, whether this is a modern or a first generation APIC
223 static int modern_apic(void)
225 /* AMD systems use old APIC versions, so check the CPU */
226 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
227 boot_cpu_data
.x86
>= 0xf)
230 /* Hygon systems use modern APIC */
231 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
)
234 return lapic_get_version() >= 0x14;
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
241 static void __init
apic_disable(void)
243 pr_info("APIC: switched to apic NOOP\n");
247 void native_apic_wait_icr_idle(void)
249 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
253 u32
native_safe_apic_wait_icr_idle(void)
260 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
263 inc_irq_stat(icr_read_retry_count
);
265 } while (timeout
++ < 1000);
270 void native_apic_icr_write(u32 low
, u32 id
)
274 local_irq_save(flags
);
275 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
276 apic_write(APIC_ICR
, low
);
277 local_irq_restore(flags
);
280 u64
native_apic_icr_read(void)
284 icr2
= apic_read(APIC_ICR2
);
285 icr1
= apic_read(APIC_ICR
);
287 return icr1
| ((u64
)icr2
<< 32);
292 * get_physical_broadcast - Get number of physical broadcast IDs
294 int get_physical_broadcast(void)
296 return modern_apic() ? 0xff : 0xf;
301 * lapic_get_maxlvt - get the maximum number of local vector table entries
303 int lapic_get_maxlvt(void)
306 * - we always have APIC integrated on 64bit mode
307 * - 82489DXs do not report # of LVT entries
309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR
)) : 2;
317 #define APIC_DIVISOR 16
318 #define TSC_DIVISOR 8
321 * This function sets up the local APIC timer, with a timeout of
322 * 'clocks' APIC bus clock. During calibration we actually call
323 * this function twice on the boot CPU, once with a bogus timeout
324 * value, second time for real. The other (noncalibrating) CPUs
325 * call this function only once, with the real, calibrated value.
327 * We do reads before writes even if unnecessary, to get around the
328 * P5 APIC double write bug.
330 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
332 unsigned int lvtt_value
, tmp_value
;
334 lvtt_value
= LOCAL_TIMER_VECTOR
;
336 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
338 lvtt_value
|= APIC_LVT_TIMER_TSCDEADLINE
;
340 if (!lapic_is_integrated())
341 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
344 lvtt_value
|= APIC_LVT_MASKED
;
346 apic_write(APIC_LVTT
, lvtt_value
);
348 if (lvtt_value
& APIC_LVT_TIMER_TSCDEADLINE
) {
350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
352 * According to Intel, MFENCE can do the serialization here.
354 asm volatile("mfence" : : : "memory");
356 printk_once(KERN_DEBUG
"TSC deadline timer enabled\n");
363 tmp_value
= apic_read(APIC_TDCR
);
364 apic_write(APIC_TDCR
,
365 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
369 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
373 * Setup extended LVT, AMD specific
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
392 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
394 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
396 return (old
& APIC_EILVT_MASKED
)
397 || (new == APIC_EILVT_MASKED
)
398 || ((new & ~APIC_EILVT_MASKED
) == old
);
401 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
403 unsigned int rsvd
, vector
;
405 if (offset
>= APIC_EILVT_NR_MAX
)
408 rsvd
= atomic_read(&eilvt_offsets
[offset
]);
410 vector
= rsvd
& ~APIC_EILVT_MASKED
; /* 0: unassigned */
411 if (vector
&& !eilvt_entry_is_changeable(vector
, new))
412 /* may not change if vectors are different */
414 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
415 } while (rsvd
!= new);
417 rsvd
&= ~APIC_EILVT_MASKED
;
418 if (rsvd
&& rsvd
!= vector
)
419 pr_info("LVT offset %d assigned for vector 0x%02x\n",
426 * If mask=1, the LVT entry does not generate interrupts while mask=0
427 * enables the vector. See also the BKDGs. Must be called with
428 * preemption disabled.
431 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
433 unsigned long reg
= APIC_EILVTn(offset
);
434 unsigned int new, old
, reserved
;
436 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
437 old
= apic_read(reg
);
438 reserved
= reserve_eilvt_offset(offset
, new);
440 if (reserved
!= new) {
441 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on another cpu\n",
444 smp_processor_id(), reg
, offset
, new, reserved
);
448 if (!eilvt_entry_is_changeable(old
, new)) {
449 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
450 "vector 0x%x, but the register is already in use for "
451 "vector 0x%x on this cpu\n",
452 smp_processor_id(), reg
, offset
, new, old
);
456 apic_write(reg
, new);
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
463 * Program the next event, relative to now
465 static int lapic_next_event(unsigned long delta
,
466 struct clock_event_device
*evt
)
468 apic_write(APIC_TMICT
, delta
);
472 static int lapic_next_deadline(unsigned long delta
,
473 struct clock_event_device
*evt
)
478 wrmsrl(MSR_IA32_TSC_DEADLINE
, tsc
+ (((u64
) delta
) * TSC_DIVISOR
));
482 static int lapic_timer_shutdown(struct clock_event_device
*evt
)
486 /* Lapic used as dummy for broadcast ? */
487 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
490 v
= apic_read(APIC_LVTT
);
491 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
492 apic_write(APIC_LVTT
, v
);
493 apic_write(APIC_TMICT
, 0);
498 lapic_timer_set_periodic_oneshot(struct clock_event_device
*evt
, bool oneshot
)
500 /* Lapic used as dummy for broadcast ? */
501 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
504 __setup_APIC_LVTT(lapic_timer_period
, oneshot
, 1);
508 static int lapic_timer_set_periodic(struct clock_event_device
*evt
)
510 return lapic_timer_set_periodic_oneshot(evt
, false);
513 static int lapic_timer_set_oneshot(struct clock_event_device
*evt
)
515 return lapic_timer_set_periodic_oneshot(evt
, true);
519 * Local APIC timer broadcast function
521 static void lapic_timer_broadcast(const struct cpumask
*mask
)
524 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
530 * The local apic timer can be used for any function which is CPU local.
532 static struct clock_event_device lapic_clockevent
= {
534 .features
= CLOCK_EVT_FEAT_PERIODIC
|
535 CLOCK_EVT_FEAT_ONESHOT
| CLOCK_EVT_FEAT_C3STOP
536 | CLOCK_EVT_FEAT_DUMMY
,
538 .set_state_shutdown
= lapic_timer_shutdown
,
539 .set_state_periodic
= lapic_timer_set_periodic
,
540 .set_state_oneshot
= lapic_timer_set_oneshot
,
541 .set_state_oneshot_stopped
= lapic_timer_shutdown
,
542 .set_next_event
= lapic_next_event
,
543 .broadcast
= lapic_timer_broadcast
,
547 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
549 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
552 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
555 static u32
hsx_deadline_rev(void)
557 switch (boot_cpu_data
.x86_stepping
) {
558 case 0x02: return 0x3a; /* EP */
559 case 0x04: return 0x0f; /* EX */
565 static u32
bdx_deadline_rev(void)
567 switch (boot_cpu_data
.x86_stepping
) {
568 case 0x02: return 0x00000011;
569 case 0x03: return 0x0700000e;
570 case 0x04: return 0x0f00000c;
571 case 0x05: return 0x0e000003;
577 static u32
skx_deadline_rev(void)
579 switch (boot_cpu_data
.x86_stepping
) {
580 case 0x03: return 0x01000136;
581 case 0x04: return 0x02000014;
584 if (boot_cpu_data
.x86_stepping
> 4)
590 static const struct x86_cpu_id deadline_match
[] = {
591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X
, hsx_deadline_rev
),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X
, 0x0b000020),
593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_D
, bdx_deadline_rev
),
594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X
, skx_deadline_rev
),
596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL
, 0x22),
597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_L
, 0x20),
598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_G
, 0x17),
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL
, 0x25),
601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_G
, 0x17),
603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_L
, 0xb2),
604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE
, 0xb2),
606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_L
, 0x52),
607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE
, 0x52),
612 static void apic_check_deadline_errata(void)
614 const struct x86_cpu_id
*m
;
617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
) ||
618 boot_cpu_has(X86_FEATURE_HYPERVISOR
))
621 m
= x86_match_cpu(deadline_match
);
626 * Function pointers will have the MSB set due to address layout,
627 * immediate revisions will not.
629 if ((long)m
->driver_data
< 0)
630 rev
= ((u32 (*)(void))(m
->driver_data
))();
632 rev
= (u32
)m
->driver_data
;
634 if (boot_cpu_data
.microcode
>= rev
)
637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
638 pr_err(FW_BUG
"TSC_DEADLINE disabled due to Errata; "
639 "please update microcode to version: 0x%x (or later)\n", rev
);
643 * Setup the local APIC timer for this CPU. Copy the initialized values
644 * of the boot CPU and register the clock event in the framework.
646 static void setup_APIC_timer(void)
648 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
650 if (this_cpu_has(X86_FEATURE_ARAT
)) {
651 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
652 /* Make LAPIC timer preferrable over percpu HPET */
653 lapic_clockevent
.rating
= 150;
656 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
657 levt
->cpumask
= cpumask_of(smp_processor_id());
659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
)) {
660 levt
->name
= "lapic-deadline";
661 levt
->features
&= ~(CLOCK_EVT_FEAT_PERIODIC
|
662 CLOCK_EVT_FEAT_DUMMY
);
663 levt
->set_next_event
= lapic_next_deadline
;
664 clockevents_config_and_register(levt
,
665 tsc_khz
* (1000 / TSC_DIVISOR
),
668 clockevents_register_device(levt
);
672 * Install the updated TSC frequency from recalibration at the TSC
673 * deadline clockevent devices.
675 static void __lapic_update_tsc_freq(void *info
)
677 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
682 clockevents_update_freq(levt
, tsc_khz
* (1000 / TSC_DIVISOR
));
685 void lapic_update_tsc_freq(void)
688 * The clockevent device's ->mult and ->shift can both be
689 * changed. In order to avoid races, schedule the frequency
690 * update code on each CPU.
692 on_each_cpu(__lapic_update_tsc_freq
, NULL
, 0);
696 * In this functions we calibrate APIC bus clocks to the external timer.
698 * We want to do the calibration only once since we want to have local timer
699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
702 * This was previously done by reading the PIT/HPET and waiting for a wrap
703 * around to find out, that a tick has elapsed. I have a box, where the PIT
704 * readout is broken, so it never gets out of the wait loop again. This was
705 * also reported by others.
707 * Monitoring the jiffies value is inaccurate and the clockevents
708 * infrastructure allows us to do a simple substitution of the interrupt
711 * The calibration routine also uses the pm_timer when possible, as the PIT
712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
713 * back to normal later in the boot process).
716 #define LAPIC_CAL_LOOPS (HZ/10)
718 static __initdata
int lapic_cal_loops
= -1;
719 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
720 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
721 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
722 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
725 * Temporary interrupt handler and polled calibration function.
727 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
729 unsigned long long tsc
= 0;
730 long tapic
= apic_read(APIC_TMCCT
);
731 unsigned long pm
= acpi_pm_read_early();
733 if (boot_cpu_has(X86_FEATURE_TSC
))
736 switch (lapic_cal_loops
++) {
738 lapic_cal_t1
= tapic
;
739 lapic_cal_tsc1
= tsc
;
741 lapic_cal_j1
= jiffies
;
744 case LAPIC_CAL_LOOPS
:
745 lapic_cal_t2
= tapic
;
746 lapic_cal_tsc2
= tsc
;
747 if (pm
< lapic_cal_pm1
)
748 pm
+= ACPI_PM_OVRRUN
;
750 lapic_cal_j2
= jiffies
;
756 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
758 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
759 const long pm_thresh
= pm_100ms
/ 100;
763 #ifndef CONFIG_X86_PM_TIMER
767 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
769 /* Check, if the PM timer is available */
773 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
775 if (deltapm
> (pm_100ms
- pm_thresh
) &&
776 deltapm
< (pm_100ms
+ pm_thresh
)) {
777 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
781 res
= (((u64
)deltapm
) * mult
) >> 22;
782 do_div(res
, 1000000);
783 pr_warning("APIC calibration not consistent "
784 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
786 /* Correct the lapic counter value */
787 res
= (((u64
)(*delta
)) * pm_100ms
);
788 do_div(res
, deltapm
);
789 pr_info("APIC delta adjusted to PM-Timer: "
790 "%lu (%ld)\n", (unsigned long)res
, *delta
);
793 /* Correct the tsc counter value */
794 if (boot_cpu_has(X86_FEATURE_TSC
)) {
795 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
796 do_div(res
, deltapm
);
797 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
798 "PM-Timer: %lu (%ld)\n",
799 (unsigned long)res
, *deltatsc
);
800 *deltatsc
= (long)res
;
806 static int __init
lapic_init_clockevent(void)
808 if (!lapic_timer_period
)
811 /* Calculate the scaled math multiplication factor */
812 lapic_clockevent
.mult
= div_sc(lapic_timer_period
/APIC_DIVISOR
,
813 TICK_NSEC
, lapic_clockevent
.shift
);
814 lapic_clockevent
.max_delta_ns
=
815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent
);
816 lapic_clockevent
.max_delta_ticks
= 0x7FFFFFFF;
817 lapic_clockevent
.min_delta_ns
=
818 clockevent_delta2ns(0xF, &lapic_clockevent
);
819 lapic_clockevent
.min_delta_ticks
= 0xF;
824 bool __init
apic_needs_pit(void)
827 * If the frequencies are not known, PIT is required for both TSC
828 * and apic timer calibration.
830 if (!tsc_khz
|| !cpu_khz
)
833 /* Is there an APIC at all? */
834 if (!boot_cpu_has(X86_FEATURE_APIC
))
837 /* Deadline timer is based on TSC so no further PIT action required */
838 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
841 /* APIC timer disabled? */
842 if (disable_apic_timer
)
845 * The APIC timer frequency is known already, no PIT calibration
846 * required. If unknown, let the PIT be initialized.
848 return lapic_timer_period
== 0;
851 static int __init
calibrate_APIC_clock(void)
853 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
854 u64 tsc_perj
= 0, tsc_start
= 0;
855 unsigned long jif_start
;
856 unsigned long deltaj
;
857 long delta
, deltatsc
;
858 int pm_referenced
= 0;
860 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
864 * Check if lapic timer has already been calibrated by platform
865 * specific routine, such as tsc calibration code. If so just fill
866 * in the clockevent structure and return.
868 if (!lapic_init_clockevent()) {
869 apic_printk(APIC_VERBOSE
, "lapic timer already calibrated %d\n",
872 * Direct calibration methods must have an always running
873 * local APIC timer, no need for broadcast timer.
875 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
879 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
880 "calibrating APIC timer ...\n");
883 * There are platforms w/o global clockevent devices. Instead of
884 * making the calibration conditional on that, use a polling based
885 * approach everywhere.
890 * Setup the APIC counter to maximum. There is no way the lapic
891 * can underflow in the 100ms detection time frame
893 __setup_APIC_LVTT(0xffffffff, 0, 0);
896 * Methods to terminate the calibration loop:
897 * 1) Global clockevent if available (jiffies)
898 * 2) TSC if available and frequency is known
900 jif_start
= READ_ONCE(jiffies
);
904 tsc_perj
= div_u64((u64
)tsc_khz
* 1000, HZ
);
908 * Enable interrupts so the tick can fire, if a global
909 * clockevent device is available
913 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
) {
914 /* Wait for a tick to elapse */
917 u64 tsc_now
= rdtsc();
918 if ((tsc_now
- tsc_start
) >= tsc_perj
) {
919 tsc_start
+= tsc_perj
;
923 unsigned long jif_now
= READ_ONCE(jiffies
);
925 if (time_after(jif_now
, jif_start
)) {
933 /* Invoke the calibration routine */
935 lapic_cal_handler(NULL
);
941 /* Build delta t1-t2 as apic timer counts down */
942 delta
= lapic_cal_t1
- lapic_cal_t2
;
943 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
945 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
947 /* we trust the PM based calibration if possible */
948 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
951 lapic_timer_period
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
952 lapic_init_clockevent();
954 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
955 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
956 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
959 if (boot_cpu_has(X86_FEATURE_TSC
)) {
960 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
962 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
963 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
966 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
968 lapic_timer_period
/ (1000000 / HZ
),
969 lapic_timer_period
% (1000000 / HZ
));
972 * Do a sanity check on the APIC calibration result
974 if (lapic_timer_period
< (1000000 / HZ
)) {
976 pr_warning("APIC frequency too slow, disabling apic timer\n");
980 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
983 * PM timer calibration failed or not turned on so lets try APIC
984 * timer based calibration, if a global clockevent device is
987 if (!pm_referenced
&& global_clock_event
) {
988 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
991 * Setup the apic timer manually
993 levt
->event_handler
= lapic_cal_handler
;
994 lapic_timer_set_periodic(levt
);
995 lapic_cal_loops
= -1;
997 /* Let the interrupts run */
1000 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
1003 /* Stop the lapic timer */
1004 local_irq_disable();
1005 lapic_timer_shutdown(levt
);
1008 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
1009 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
1011 /* Check, if the jiffies result is consistent */
1012 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
1013 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
1015 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
1019 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
1020 pr_warning("APIC timer disabled due to verification failure\n");
1028 * Setup the boot APIC
1030 * Calibrate and verify the result.
1032 void __init
setup_boot_APIC_clock(void)
1035 * The local apic timer can be disabled via the kernel
1036 * commandline or from the CPU detection code. Register the lapic
1037 * timer as a dummy clock event source on SMP systems, so the
1038 * broadcast mechanism is used. On UP systems simply ignore it.
1040 if (disable_apic_timer
) {
1041 pr_info("Disabling APIC timer\n");
1042 /* No broadcast on UP ! */
1043 if (num_possible_cpus() > 1) {
1044 lapic_clockevent
.mult
= 1;
1050 if (calibrate_APIC_clock()) {
1051 /* No broadcast on UP ! */
1052 if (num_possible_cpus() > 1)
1058 * If nmi_watchdog is set to IO_APIC, we need the
1059 * PIT/HPET going. Otherwise register lapic as a dummy
1062 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
1064 /* Setup the lapic or request the broadcast */
1066 amd_e400_c1e_apic_setup();
1069 void setup_secondary_APIC_clock(void)
1072 amd_e400_c1e_apic_setup();
1076 * The guts of the apic timer interrupt
1078 static void local_apic_timer_interrupt(void)
1080 struct clock_event_device
*evt
= this_cpu_ptr(&lapic_events
);
1083 * Normally we should not be here till LAPIC has been initialized but
1084 * in some cases like kdump, its possible that there is a pending LAPIC
1085 * timer interrupt from previous kernel's context and is delivered in
1086 * new kernel the moment interrupts are enabled.
1088 * Interrupts are enabled early and LAPIC is setup much later, hence
1089 * its possible that when we get here evt->event_handler is NULL.
1090 * Check for event_handler being NULL and discard the interrupt as
1093 if (!evt
->event_handler
) {
1094 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1095 smp_processor_id());
1097 lapic_timer_shutdown(evt
);
1102 * the NMI deadlock-detector uses this.
1104 inc_irq_stat(apic_timer_irqs
);
1106 evt
->event_handler(evt
);
1110 * Local APIC timer interrupt. This is the most natural way for doing
1111 * local interrupts, but local timer interrupts can be emulated by
1112 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1114 * [ if a single-CPU system runs an SMP kernel then we call the local
1115 * interrupt as well. Thus we cannot inline the local irq ... ]
1117 __visible
void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
1119 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1122 * NOTE! We'd better ACK the irq immediately,
1123 * because timer handling can be slow.
1125 * update_process_times() expects us to have done irq_enter().
1126 * Besides, if we don't timer interrupts ignore the global
1127 * interrupt lock, which is the WrongThing (tm) to do.
1130 trace_local_timer_entry(LOCAL_TIMER_VECTOR
);
1131 local_apic_timer_interrupt();
1132 trace_local_timer_exit(LOCAL_TIMER_VECTOR
);
1135 set_irq_regs(old_regs
);
1138 int setup_profiling_timer(unsigned int multiplier
)
1144 * Local APIC start and shutdown
1148 * clear_local_APIC - shutdown the local APIC
1150 * This is called, when a CPU is disabled and before rebooting, so the state of
1151 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1152 * leftovers during boot.
1154 void clear_local_APIC(void)
1159 /* APIC hasn't been mapped yet */
1160 if (!x2apic_mode
&& !apic_phys
)
1163 maxlvt
= lapic_get_maxlvt();
1165 * Masking an LVT entry can trigger a local APIC error
1166 * if the vector is zero. Mask LVTERR first to prevent this.
1169 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
1170 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
1173 * Careful: we have to set masks only first to deassert
1174 * any level-triggered sources.
1176 v
= apic_read(APIC_LVTT
);
1177 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1178 v
= apic_read(APIC_LVT0
);
1179 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1180 v
= apic_read(APIC_LVT1
);
1181 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
1183 v
= apic_read(APIC_LVTPC
);
1184 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
1187 /* lets not touch this if we didn't frob it */
1188 #ifdef CONFIG_X86_THERMAL_VECTOR
1190 v
= apic_read(APIC_LVTTHMR
);
1191 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
1194 #ifdef CONFIG_X86_MCE_INTEL
1196 v
= apic_read(APIC_LVTCMCI
);
1197 if (!(v
& APIC_LVT_MASKED
))
1198 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
1203 * Clean APIC state for other OSs:
1205 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
1206 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1207 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
1209 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
1211 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
1213 /* Integrated APIC (!82489DX) ? */
1214 if (lapic_is_integrated()) {
1216 /* Clear ESR due to Pentium errata 3AP and 11AP */
1217 apic_write(APIC_ESR
, 0);
1218 apic_read(APIC_ESR
);
1223 * disable_local_APIC - clear and disable the local APIC
1225 void disable_local_APIC(void)
1229 /* APIC hasn't been mapped yet */
1230 if (!x2apic_mode
&& !apic_phys
)
1236 * Disable APIC (implies clearing of registers
1239 value
= apic_read(APIC_SPIV
);
1240 value
&= ~APIC_SPIV_APIC_ENABLED
;
1241 apic_write(APIC_SPIV
, value
);
1243 #ifdef CONFIG_X86_32
1245 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1246 * restore the disabled state.
1248 if (enabled_via_apicbase
) {
1251 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1252 l
&= ~MSR_IA32_APICBASE_ENABLE
;
1253 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1259 * If Linux enabled the LAPIC against the BIOS default disable it down before
1260 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1261 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1262 * for the case where Linux didn't enable the LAPIC.
1264 void lapic_shutdown(void)
1266 unsigned long flags
;
1268 if (!boot_cpu_has(X86_FEATURE_APIC
) && !apic_from_smp_config())
1271 local_irq_save(flags
);
1273 #ifdef CONFIG_X86_32
1274 if (!enabled_via_apicbase
)
1278 disable_local_APIC();
1281 local_irq_restore(flags
);
1285 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1287 void __init
sync_Arb_IDs(void)
1290 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1293 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1299 apic_wait_icr_idle();
1301 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1302 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1303 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1306 enum apic_intr_mode_id apic_intr_mode
;
1308 static int __init
apic_intr_mode_select(void)
1310 /* Check kernel option */
1312 pr_info("APIC disabled via kernel command line\n");
1317 #ifdef CONFIG_X86_64
1318 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1319 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
1321 pr_info("APIC disabled by BIOS\n");
1325 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1327 /* Neither 82489DX nor integrated APIC ? */
1328 if (!boot_cpu_has(X86_FEATURE_APIC
) && !smp_found_config
) {
1333 /* If the BIOS pretends there is an integrated APIC ? */
1334 if (!boot_cpu_has(X86_FEATURE_APIC
) &&
1335 APIC_INTEGRATED(boot_cpu_apic_version
)) {
1337 pr_err(FW_BUG
"Local APIC %d not detected, force emulation\n",
1338 boot_cpu_physical_apicid
);
1343 /* Check MP table or ACPI MADT configuration */
1344 if (!smp_found_config
) {
1345 disable_ioapic_support();
1347 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1348 return APIC_VIRTUAL_WIRE_NO_CONFIG
;
1350 return APIC_VIRTUAL_WIRE
;
1354 /* If SMP should be disabled, then really disable it! */
1355 if (!setup_max_cpus
) {
1356 pr_info("APIC: SMP mode deactivated\n");
1357 return APIC_SYMMETRIC_IO_NO_ROUTING
;
1360 if (read_apic_id() != boot_cpu_physical_apicid
) {
1361 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1362 read_apic_id(), boot_cpu_physical_apicid
);
1363 /* Or can we switch back to PIC here? */
1367 return APIC_SYMMETRIC_IO
;
1371 * An initial setup of the virtual wire mode.
1373 void __init
init_bsp_APIC(void)
1378 * Don't do the setup now if we have a SMP BIOS as the
1379 * through-I/O-APIC virtual wire mode might be active.
1381 if (smp_found_config
|| !boot_cpu_has(X86_FEATURE_APIC
))
1385 * Do not trust the local APIC being empty at bootup.
1392 value
= apic_read(APIC_SPIV
);
1393 value
&= ~APIC_VECTOR_MASK
;
1394 value
|= APIC_SPIV_APIC_ENABLED
;
1396 #ifdef CONFIG_X86_32
1397 /* This bit is reserved on P4/Xeon and should be cleared */
1398 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1399 (boot_cpu_data
.x86
== 15))
1400 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1403 value
|= APIC_SPIV_FOCUS_DISABLED
;
1404 value
|= SPURIOUS_APIC_VECTOR
;
1405 apic_write(APIC_SPIV
, value
);
1408 * Set up the virtual wire mode.
1410 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1411 value
= APIC_DM_NMI
;
1412 if (!lapic_is_integrated()) /* 82489DX */
1413 value
|= APIC_LVT_LEVEL_TRIGGER
;
1414 if (apic_extnmi
== APIC_EXTNMI_NONE
)
1415 value
|= APIC_LVT_MASKED
;
1416 apic_write(APIC_LVT1
, value
);
1419 static void __init
apic_bsp_setup(bool upmode
);
1421 /* Init the interrupt delivery mode for the BSP */
1422 void __init
apic_intr_mode_init(void)
1424 bool upmode
= IS_ENABLED(CONFIG_UP_LATE_INIT
);
1426 apic_intr_mode
= apic_intr_mode_select();
1428 switch (apic_intr_mode
) {
1430 pr_info("APIC: Keep in PIC mode(8259)\n");
1432 case APIC_VIRTUAL_WIRE
:
1433 pr_info("APIC: Switch to virtual wire mode setup\n");
1434 default_setup_apic_routing();
1436 case APIC_VIRTUAL_WIRE_NO_CONFIG
:
1437 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1439 default_setup_apic_routing();
1441 case APIC_SYMMETRIC_IO
:
1442 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1443 default_setup_apic_routing();
1445 case APIC_SYMMETRIC_IO_NO_ROUTING
:
1446 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1450 apic_bsp_setup(upmode
);
1453 static void lapic_setup_esr(void)
1455 unsigned int oldvalue
, value
, maxlvt
;
1457 if (!lapic_is_integrated()) {
1458 pr_info("No ESR for 82489DX.\n");
1462 if (apic
->disable_esr
) {
1464 * Something untraceable is creating bad interrupts on
1465 * secondary quads ... for the moment, just leave the
1466 * ESR disabled - we can't do anything useful with the
1467 * errors anyway - mbligh
1469 pr_info("Leaving ESR disabled.\n");
1473 maxlvt
= lapic_get_maxlvt();
1474 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1475 apic_write(APIC_ESR
, 0);
1476 oldvalue
= apic_read(APIC_ESR
);
1478 /* enables sending errors */
1479 value
= ERROR_APIC_VECTOR
;
1480 apic_write(APIC_LVTERR
, value
);
1483 * spec says clear errors after enabling vector.
1486 apic_write(APIC_ESR
, 0);
1487 value
= apic_read(APIC_ESR
);
1488 if (value
!= oldvalue
)
1489 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1490 "vector: 0x%08x after: 0x%08x\n",
1494 static void apic_pending_intr_clear(void)
1496 long long max_loops
= cpu_khz
? cpu_khz
: 1000000;
1497 unsigned long long tsc
= 0, ntsc
;
1498 unsigned int queued
;
1499 unsigned long value
;
1500 int i
, j
, acked
= 0;
1502 if (boot_cpu_has(X86_FEATURE_TSC
))
1505 * After a crash, we no longer service the interrupts and a pending
1506 * interrupt from previous kernel might still have ISR bit set.
1508 * Most probably by now CPU has serviced that pending interrupt and
1509 * it might not have done the ack_APIC_irq() because it thought,
1510 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1511 * does not clear the ISR bit and cpu thinks it has already serivced
1512 * the interrupt. Hence a vector might get locked. It was noticed
1513 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1517 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1518 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1520 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1521 value
= apic_read(APIC_ISR
+ i
*0x10);
1522 for_each_set_bit(j
, &value
, 32) {
1528 pr_err("LAPIC pending interrupts after %d EOI\n", acked
);
1532 if (boot_cpu_has(X86_FEATURE_TSC
) && cpu_khz
) {
1534 max_loops
= (long long)cpu_khz
<< 10;
1535 max_loops
-= ntsc
- tsc
;
1540 } while (queued
&& max_loops
> 0);
1541 WARN_ON(max_loops
<= 0);
1545 * setup_local_APIC - setup the local APIC
1547 * Used to setup local APIC while initializing BSP or bringing up APs.
1548 * Always called with preemption disabled.
1550 static void setup_local_APIC(void)
1552 int cpu
= smp_processor_id();
1554 #ifdef CONFIG_X86_32
1555 int logical_apicid
, ldr_apicid
;
1560 disable_ioapic_support();
1564 #ifdef CONFIG_X86_32
1565 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1566 if (lapic_is_integrated() && apic
->disable_esr
) {
1567 apic_write(APIC_ESR
, 0);
1568 apic_write(APIC_ESR
, 0);
1569 apic_write(APIC_ESR
, 0);
1570 apic_write(APIC_ESR
, 0);
1573 perf_events_lapic_init();
1576 * Double-check whether this APIC is really registered.
1577 * This is meaningless in clustered apic mode, so we skip it.
1579 BUG_ON(!apic
->apic_id_registered());
1582 * Intel recommends to set DFR, LDR and TPR before enabling
1583 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1584 * document number 292116). So here it goes...
1586 apic
->init_apic_ldr();
1588 #ifdef CONFIG_X86_32
1590 * APIC LDR is initialized. If logical_apicid mapping was
1591 * initialized during get_smp_config(), make sure it matches the
1594 logical_apicid
= early_per_cpu(x86_cpu_to_logical_apicid
, cpu
);
1595 ldr_apicid
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
1596 WARN_ON(logical_apicid
!= BAD_APICID
&& logical_apicid
!= ldr_apicid
);
1597 /* always use the value from LDR */
1598 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) = ldr_apicid
;
1602 * Set Task Priority to 'accept all'. We never change this
1605 value
= apic_read(APIC_TASKPRI
);
1606 value
&= ~APIC_TPRI_MASK
;
1607 apic_write(APIC_TASKPRI
, value
);
1609 apic_pending_intr_clear();
1612 * Now that we are all set up, enable the APIC
1614 value
= apic_read(APIC_SPIV
);
1615 value
&= ~APIC_VECTOR_MASK
;
1619 value
|= APIC_SPIV_APIC_ENABLED
;
1621 #ifdef CONFIG_X86_32
1623 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1624 * certain networking cards. If high frequency interrupts are
1625 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1626 * entry is masked/unmasked at a high rate as well then sooner or
1627 * later IOAPIC line gets 'stuck', no more interrupts are received
1628 * from the device. If focus CPU is disabled then the hang goes
1631 * [ This bug can be reproduced easily with a level-triggered
1632 * PCI Ne2000 networking cards and PII/PIII processors, dual
1636 * Actually disabling the focus CPU check just makes the hang less
1637 * frequent as it makes the interrupt distributon model be more
1638 * like LRU than MRU (the short-term load is more even across CPUs).
1642 * - enable focus processor (bit==0)
1643 * - 64bit mode always use processor focus
1644 * so no need to set it
1646 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1650 * Set spurious IRQ vector
1652 value
|= SPURIOUS_APIC_VECTOR
;
1653 apic_write(APIC_SPIV
, value
);
1656 * Set up LVT0, LVT1:
1658 * set up through-local-APIC on the boot CPU's LINT0. This is not
1659 * strictly necessary in pure symmetric-IO mode, but sometimes
1660 * we delegate interrupts to the 8259A.
1663 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1665 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1666 if (!cpu
&& (pic_mode
|| !value
|| skip_ioapic_setup
)) {
1667 value
= APIC_DM_EXTINT
;
1668 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", cpu
);
1670 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1671 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", cpu
);
1673 apic_write(APIC_LVT0
, value
);
1676 * Only the BSP sees the LINT1 NMI signal by default. This can be
1677 * modified by apic_extnmi= boot option.
1679 if ((!cpu
&& apic_extnmi
!= APIC_EXTNMI_NONE
) ||
1680 apic_extnmi
== APIC_EXTNMI_ALL
)
1681 value
= APIC_DM_NMI
;
1683 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1686 if (!lapic_is_integrated())
1687 value
|= APIC_LVT_LEVEL_TRIGGER
;
1688 apic_write(APIC_LVT1
, value
);
1690 #ifdef CONFIG_X86_MCE_INTEL
1691 /* Recheck CMCI information after local APIC is up on CPU #0 */
1697 static void end_local_APIC_setup(void)
1701 #ifdef CONFIG_X86_32
1704 /* Disable the local apic timer */
1705 value
= apic_read(APIC_LVTT
);
1706 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1707 apic_write(APIC_LVTT
, value
);
1715 * APIC setup function for application processors. Called from smpboot.c
1717 void apic_ap_setup(void)
1720 end_local_APIC_setup();
1723 #ifdef CONFIG_X86_X2APIC
1731 static int x2apic_state
;
1733 static void __x2apic_disable(void)
1737 if (!boot_cpu_has(X86_FEATURE_APIC
))
1740 rdmsrl(MSR_IA32_APICBASE
, msr
);
1741 if (!(msr
& X2APIC_ENABLE
))
1743 /* Disable xapic and x2apic first and then reenable xapic mode */
1744 wrmsrl(MSR_IA32_APICBASE
, msr
& ~(X2APIC_ENABLE
| XAPIC_ENABLE
));
1745 wrmsrl(MSR_IA32_APICBASE
, msr
& ~X2APIC_ENABLE
);
1746 printk_once(KERN_INFO
"x2apic disabled\n");
1749 static void __x2apic_enable(void)
1753 rdmsrl(MSR_IA32_APICBASE
, msr
);
1754 if (msr
& X2APIC_ENABLE
)
1756 wrmsrl(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
);
1757 printk_once(KERN_INFO
"x2apic enabled\n");
1760 static int __init
setup_nox2apic(char *str
)
1762 if (x2apic_enabled()) {
1763 int apicid
= native_apic_msr_read(APIC_ID
);
1765 if (apicid
>= 255) {
1766 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1770 pr_warning("x2apic already enabled.\n");
1773 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
1774 x2apic_state
= X2APIC_DISABLED
;
1778 early_param("nox2apic", setup_nox2apic
);
1780 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1781 void x2apic_setup(void)
1784 * If x2apic is not in ON state, disable it if already enabled
1787 if (x2apic_state
!= X2APIC_ON
) {
1794 static __init
void x2apic_disable(void)
1796 u32 x2apic_id
, state
= x2apic_state
;
1799 x2apic_state
= X2APIC_DISABLED
;
1801 if (state
!= X2APIC_ON
)
1804 x2apic_id
= read_apic_id();
1805 if (x2apic_id
>= 255)
1806 panic("Cannot disable x2apic, id: %08x\n", x2apic_id
);
1809 register_lapic_address(mp_lapic_addr
);
1812 static __init
void x2apic_enable(void)
1814 if (x2apic_state
!= X2APIC_OFF
)
1818 x2apic_state
= X2APIC_ON
;
1822 static __init
void try_to_enable_x2apic(int remap_mode
)
1824 if (x2apic_state
== X2APIC_DISABLED
)
1827 if (remap_mode
!= IRQ_REMAP_X2APIC_MODE
) {
1828 /* IR is required if there is APIC ID > 255 even when running
1831 if (max_physical_apicid
> 255 ||
1832 !x86_init
.hyper
.x2apic_available()) {
1833 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1839 * without IR all CPUs can be addressed by IOAPIC/MSI
1840 * only in physical mode
1847 void __init
check_x2apic(void)
1849 if (x2apic_enabled()) {
1850 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1852 x2apic_state
= X2APIC_ON
;
1853 } else if (!boot_cpu_has(X86_FEATURE_X2APIC
)) {
1854 x2apic_state
= X2APIC_DISABLED
;
1857 #else /* CONFIG_X86_X2APIC */
1858 static int __init
validate_x2apic(void)
1860 if (!apic_is_x2apic_enabled())
1863 * Checkme: Can we simply turn off x2apic here instead of panic?
1865 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1867 early_initcall(validate_x2apic
);
1869 static inline void try_to_enable_x2apic(int remap_mode
) { }
1870 static inline void __x2apic_enable(void) { }
1871 #endif /* !CONFIG_X86_X2APIC */
1873 void __init
enable_IR_x2apic(void)
1875 unsigned long flags
;
1878 if (skip_ioapic_setup
) {
1879 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1883 ir_stat
= irq_remapping_prepare();
1884 if (ir_stat
< 0 && !x2apic_supported())
1887 ret
= save_ioapic_entries();
1889 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1893 local_irq_save(flags
);
1894 legacy_pic
->mask_all();
1895 mask_ioapic_entries();
1897 /* If irq_remapping_prepare() succeeded, try to enable it */
1899 ir_stat
= irq_remapping_enable();
1900 /* ir_stat contains the remap mode or an error code */
1901 try_to_enable_x2apic(ir_stat
);
1904 restore_ioapic_entries();
1905 legacy_pic
->restore_mask();
1906 local_irq_restore(flags
);
1909 #ifdef CONFIG_X86_64
1911 * Detect and enable local APICs on non-SMP boards.
1912 * Original code written by Keir Fraser.
1913 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1914 * not correctly set up (usually the APIC timer won't work etc.)
1916 static int __init
detect_init_APIC(void)
1918 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
1919 pr_info("No local APIC present\n");
1923 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1928 static int __init
apic_verify(void)
1933 * The APIC feature bit should now be enabled
1936 features
= cpuid_edx(1);
1937 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1938 pr_warning("Could not enable APIC!\n");
1941 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1942 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1944 /* The BIOS may have set up the APIC at some other address */
1945 if (boot_cpu_data
.x86
>= 6) {
1946 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1947 if (l
& MSR_IA32_APICBASE_ENABLE
)
1948 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1951 pr_info("Found and enabled local APIC!\n");
1955 int __init
apic_force_enable(unsigned long addr
)
1963 * Some BIOSes disable the local APIC in the APIC_BASE
1964 * MSR. This can only be done in software for Intel P6 or later
1965 * and AMD K7 (Model > 1) or later.
1967 if (boot_cpu_data
.x86
>= 6) {
1968 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1969 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1970 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1971 l
&= ~MSR_IA32_APICBASE_BASE
;
1972 l
|= MSR_IA32_APICBASE_ENABLE
| addr
;
1973 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1974 enabled_via_apicbase
= 1;
1977 return apic_verify();
1981 * Detect and initialize APIC
1983 static int __init
detect_init_APIC(void)
1985 /* Disabled by kernel option? */
1989 switch (boot_cpu_data
.x86_vendor
) {
1990 case X86_VENDOR_AMD
:
1991 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1992 (boot_cpu_data
.x86
>= 15))
1995 case X86_VENDOR_HYGON
:
1997 case X86_VENDOR_INTEL
:
1998 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1999 (boot_cpu_data
.x86
== 5 && boot_cpu_has(X86_FEATURE_APIC
)))
2006 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
2008 * Over-ride BIOS and try to enable the local APIC only if
2009 * "lapic" specified.
2011 if (!force_enable_local_apic
) {
2012 pr_info("Local APIC disabled by BIOS -- "
2013 "you can enable it with \"lapic\"\n");
2016 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE
))
2028 pr_info("No local APIC present or hardware disabled\n");
2034 * init_apic_mappings - initialize APIC mappings
2036 void __init
init_apic_mappings(void)
2038 unsigned int new_apicid
;
2040 apic_check_deadline_errata();
2043 boot_cpu_physical_apicid
= read_apic_id();
2047 /* If no local APIC can be found return early */
2048 if (!smp_found_config
&& detect_init_APIC()) {
2049 /* lets NOP'ify apic operations */
2050 pr_info("APIC: disable apic facility\n");
2053 apic_phys
= mp_lapic_addr
;
2056 * If the system has ACPI MADT tables or MP info, the LAPIC
2057 * address is already registered.
2059 if (!acpi_lapic
&& !smp_found_config
)
2060 register_lapic_address(apic_phys
);
2064 * Fetch the APIC ID of the BSP in case we have a
2065 * default configuration (or the MP table is broken).
2067 new_apicid
= read_apic_id();
2068 if (boot_cpu_physical_apicid
!= new_apicid
) {
2069 boot_cpu_physical_apicid
= new_apicid
;
2071 * yeah -- we lie about apic_version
2072 * in case if apic was disabled via boot option
2073 * but it's not a problem for SMP compiled kernel
2074 * since apic_intr_mode_select is prepared for such
2075 * a case and disable smp mode
2077 boot_cpu_apic_version
= GET_APIC_VERSION(apic_read(APIC_LVR
));
2081 void __init
register_lapic_address(unsigned long address
)
2083 mp_lapic_addr
= address
;
2086 set_fixmap_nocache(FIX_APIC_BASE
, address
);
2087 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
2088 APIC_BASE
, address
);
2090 if (boot_cpu_physical_apicid
== -1U) {
2091 boot_cpu_physical_apicid
= read_apic_id();
2092 boot_cpu_apic_version
= GET_APIC_VERSION(apic_read(APIC_LVR
));
2097 * Local APIC interrupts
2101 * This interrupt should _never_ happen with our APIC/SMP architecture
2103 __visible
void __irq_entry
smp_spurious_interrupt(struct pt_regs
*regs
)
2105 u8 vector
= ~regs
->orig_ax
;
2109 trace_spurious_apic_entry(vector
);
2111 inc_irq_stat(irq_spurious_count
);
2114 * If this is a spurious interrupt then do not acknowledge
2116 if (vector
== SPURIOUS_APIC_VECTOR
) {
2118 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2119 smp_processor_id());
2124 * If it is a vectored one, verify it's set in the ISR. If set,
2127 v
= apic_read(APIC_ISR
+ ((vector
& ~0x1f) >> 1));
2128 if (v
& (1 << (vector
& 0x1f))) {
2129 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2130 vector
, smp_processor_id());
2133 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2134 vector
, smp_processor_id());
2137 trace_spurious_apic_exit(vector
);
2142 * This interrupt should never happen with our APIC/SMP architecture
2144 __visible
void __irq_entry
smp_error_interrupt(struct pt_regs
*regs
)
2146 static const char * const error_interrupt_reason
[] = {
2147 "Send CS error", /* APIC Error Bit 0 */
2148 "Receive CS error", /* APIC Error Bit 1 */
2149 "Send accept error", /* APIC Error Bit 2 */
2150 "Receive accept error", /* APIC Error Bit 3 */
2151 "Redirectable IPI", /* APIC Error Bit 4 */
2152 "Send illegal vector", /* APIC Error Bit 5 */
2153 "Received illegal vector", /* APIC Error Bit 6 */
2154 "Illegal register address", /* APIC Error Bit 7 */
2159 trace_error_apic_entry(ERROR_APIC_VECTOR
);
2161 /* First tickle the hardware, only then report what went on. -- REW */
2162 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2163 apic_write(APIC_ESR
, 0);
2164 v
= apic_read(APIC_ESR
);
2166 atomic_inc(&irq_err_count
);
2168 apic_printk(APIC_DEBUG
, KERN_DEBUG
"APIC error on CPU%d: %02x",
2169 smp_processor_id(), v
);
2174 apic_printk(APIC_DEBUG
, KERN_CONT
" : %s", error_interrupt_reason
[i
]);
2179 apic_printk(APIC_DEBUG
, KERN_CONT
"\n");
2181 trace_error_apic_exit(ERROR_APIC_VECTOR
);
2186 * connect_bsp_APIC - attach the APIC to the interrupt system
2188 static void __init
connect_bsp_APIC(void)
2190 #ifdef CONFIG_X86_32
2193 * Do not trust the local APIC being empty at bootup.
2197 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2198 * local APIC to INT and NMI lines.
2200 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
2201 "enabling APIC mode.\n");
2208 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2209 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2211 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2214 void disconnect_bsp_APIC(int virt_wire_setup
)
2218 #ifdef CONFIG_X86_32
2221 * Put the board back into PIC mode (has an effect only on
2222 * certain older boards). Note that APIC interrupts, including
2223 * IPIs, won't work beyond this point! The only exception are
2226 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
2227 "entering PIC mode.\n");
2233 /* Go back to Virtual Wire compatibility mode */
2235 /* For the spurious interrupt use vector F, and enable it */
2236 value
= apic_read(APIC_SPIV
);
2237 value
&= ~APIC_VECTOR_MASK
;
2238 value
|= APIC_SPIV_APIC_ENABLED
;
2240 apic_write(APIC_SPIV
, value
);
2242 if (!virt_wire_setup
) {
2244 * For LVT0 make it edge triggered, active high,
2245 * external and enabled
2247 value
= apic_read(APIC_LVT0
);
2248 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2249 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2250 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2251 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2252 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
2253 apic_write(APIC_LVT0
, value
);
2256 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
2260 * For LVT1 make it edge triggered, active high,
2263 value
= apic_read(APIC_LVT1
);
2264 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2265 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2266 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2267 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2268 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
2269 apic_write(APIC_LVT1
, value
);
2273 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2274 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2275 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2276 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2278 * NOTE: Reserve 0 for BSP.
2280 static int nr_logical_cpuids
= 1;
2283 * Used to store mapping between logical CPU IDs and APIC IDs.
2285 static int cpuid_to_apicid
[] = {
2286 [0 ... NR_CPUS
- 1] = -1,
2291 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2292 * @id: APIC ID to check
2294 bool apic_id_is_primary_thread(unsigned int apicid
)
2298 if (smp_num_siblings
== 1)
2300 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2301 mask
= (1U << (fls(smp_num_siblings
) - 1)) - 1;
2302 return !(apicid
& mask
);
2307 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2308 * and cpuid_to_apicid[] synchronized.
2310 static int allocate_logical_cpuid(int apicid
)
2315 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2316 * check if the kernel has allocated a cpuid for it.
2318 for (i
= 0; i
< nr_logical_cpuids
; i
++) {
2319 if (cpuid_to_apicid
[i
] == apicid
)
2323 /* Allocate a new cpuid. */
2324 if (nr_logical_cpuids
>= nr_cpu_ids
) {
2325 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2326 "Processor %d/0x%x and the rest are ignored.\n",
2327 nr_cpu_ids
, nr_logical_cpuids
, apicid
);
2331 cpuid_to_apicid
[nr_logical_cpuids
] = apicid
;
2332 return nr_logical_cpuids
++;
2335 int generic_processor_info(int apicid
, int version
)
2337 int cpu
, max
= nr_cpu_ids
;
2338 bool boot_cpu_detected
= physid_isset(boot_cpu_physical_apicid
,
2339 phys_cpu_present_map
);
2342 * boot_cpu_physical_apicid is designed to have the apicid
2343 * returned by read_apic_id(), i.e, the apicid of the
2344 * currently booting-up processor. However, on some platforms,
2345 * it is temporarily modified by the apicid reported as BSP
2346 * through MP table. Concretely:
2348 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2349 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2351 * This function is executed with the modified
2352 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2353 * parameter doesn't work to disable APs on kdump 2nd kernel.
2355 * Since fixing handling of boot_cpu_physical_apicid requires
2356 * another discussion and tests on each platform, we leave it
2357 * for now and here we use read_apic_id() directly in this
2358 * function, generic_processor_info().
2360 if (disabled_cpu_apicid
!= BAD_APICID
&&
2361 disabled_cpu_apicid
!= read_apic_id() &&
2362 disabled_cpu_apicid
== apicid
) {
2363 int thiscpu
= num_processors
+ disabled_cpus
;
2365 pr_warning("APIC: Disabling requested cpu."
2366 " Processor %d/0x%x ignored.\n",
2374 * If boot cpu has not been detected yet, then only allow upto
2375 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2377 if (!boot_cpu_detected
&& num_processors
>= nr_cpu_ids
- 1 &&
2378 apicid
!= boot_cpu_physical_apicid
) {
2379 int thiscpu
= max
+ disabled_cpus
- 1;
2382 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2383 " reached. Keeping one slot for boot cpu."
2384 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2390 if (num_processors
>= nr_cpu_ids
) {
2391 int thiscpu
= max
+ disabled_cpus
;
2393 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2394 "reached. Processor %d/0x%x ignored.\n",
2395 max
, thiscpu
, apicid
);
2401 if (apicid
== boot_cpu_physical_apicid
) {
2403 * x86_bios_cpu_apicid is required to have processors listed
2404 * in same order as logical cpu numbers. Hence the first
2405 * entry is BSP, and so on.
2406 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2411 /* Logical cpuid 0 is reserved for BSP. */
2412 cpuid_to_apicid
[0] = apicid
;
2414 cpu
= allocate_logical_cpuid(apicid
);
2424 if (version
== 0x0) {
2425 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2430 if (version
!= boot_cpu_apic_version
) {
2431 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2432 boot_cpu_apic_version
, cpu
, version
);
2435 if (apicid
> max_physical_apicid
)
2436 max_physical_apicid
= apicid
;
2438 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2439 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
2440 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
2442 #ifdef CONFIG_X86_32
2443 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
2444 apic
->x86_32_early_logical_apicid(cpu
);
2446 set_cpu_possible(cpu
, true);
2447 physid_set(apicid
, phys_cpu_present_map
);
2448 set_cpu_present(cpu
, true);
2454 int hard_smp_processor_id(void)
2456 return read_apic_id();
2460 * Override the generic EOI implementation with an optimized version.
2461 * Only called during early boot when only one CPU is active and with
2462 * interrupts disabled, so we know this does not race with actual APIC driver
2465 void __init
apic_set_eoi_write(void (*eoi_write
)(u32 reg
, u32 v
))
2469 for (drv
= __apicdrivers
; drv
< __apicdrivers_end
; drv
++) {
2470 /* Should happen once for each apic */
2471 WARN_ON((*drv
)->eoi_write
== eoi_write
);
2472 (*drv
)->native_eoi_write
= (*drv
)->eoi_write
;
2473 (*drv
)->eoi_write
= eoi_write
;
2477 static void __init
apic_bsp_up_setup(void)
2479 #ifdef CONFIG_X86_64
2480 apic_write(APIC_ID
, apic
->set_apic_id(boot_cpu_physical_apicid
));
2483 * Hack: In case of kdump, after a crash, kernel might be booting
2484 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2485 * might be zero if read from MP tables. Get it from LAPIC.
2487 # ifdef CONFIG_CRASH_DUMP
2488 boot_cpu_physical_apicid
= read_apic_id();
2491 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
2495 * apic_bsp_setup - Setup function for local apic and io-apic
2496 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2498 static void __init
apic_bsp_setup(bool upmode
)
2502 apic_bsp_up_setup();
2506 end_local_APIC_setup();
2507 irq_remap_enable_fault_handling();
2511 #ifdef CONFIG_UP_LATE_INIT
2512 void __init
up_late_init(void)
2514 if (apic_intr_mode
== APIC_PIC
)
2517 /* Setup local timer */
2518 x86_init
.timers
.setup_percpu_clockev();
2529 * 'active' is true if the local APIC was enabled by us and
2530 * not the BIOS; this signifies that we are also responsible
2531 * for disabling it before entering apm/acpi suspend
2534 /* r/w apic fields */
2535 unsigned int apic_id
;
2536 unsigned int apic_taskpri
;
2537 unsigned int apic_ldr
;
2538 unsigned int apic_dfr
;
2539 unsigned int apic_spiv
;
2540 unsigned int apic_lvtt
;
2541 unsigned int apic_lvtpc
;
2542 unsigned int apic_lvt0
;
2543 unsigned int apic_lvt1
;
2544 unsigned int apic_lvterr
;
2545 unsigned int apic_tmict
;
2546 unsigned int apic_tdcr
;
2547 unsigned int apic_thmr
;
2548 unsigned int apic_cmci
;
2551 static int lapic_suspend(void)
2553 unsigned long flags
;
2556 if (!apic_pm_state
.active
)
2559 maxlvt
= lapic_get_maxlvt();
2561 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2562 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2563 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2564 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2565 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2566 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2568 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2569 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2570 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2571 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2572 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2573 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2574 #ifdef CONFIG_X86_THERMAL_VECTOR
2576 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2578 #ifdef CONFIG_X86_MCE_INTEL
2580 apic_pm_state
.apic_cmci
= apic_read(APIC_LVTCMCI
);
2583 local_irq_save(flags
);
2584 disable_local_APIC();
2586 irq_remapping_disable();
2588 local_irq_restore(flags
);
2592 static void lapic_resume(void)
2595 unsigned long flags
;
2598 if (!apic_pm_state
.active
)
2601 local_irq_save(flags
);
2604 * IO-APIC and PIC have their own resume routines.
2605 * We just mask them here to make sure the interrupt
2606 * subsystem is completely quiet while we enable x2apic
2607 * and interrupt-remapping.
2609 mask_ioapic_entries();
2610 legacy_pic
->mask_all();
2616 * Make sure the APICBASE points to the right address
2618 * FIXME! This will be wrong if we ever support suspend on
2619 * SMP! We'll need to do this as part of the CPU restore!
2621 if (boot_cpu_data
.x86
>= 6) {
2622 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2623 l
&= ~MSR_IA32_APICBASE_BASE
;
2624 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2625 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2629 maxlvt
= lapic_get_maxlvt();
2630 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2631 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2632 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2633 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2634 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2635 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2636 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2637 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2638 #ifdef CONFIG_X86_THERMAL_VECTOR
2640 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2642 #ifdef CONFIG_X86_MCE_INTEL
2644 apic_write(APIC_LVTCMCI
, apic_pm_state
.apic_cmci
);
2647 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2648 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2649 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2650 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2651 apic_write(APIC_ESR
, 0);
2652 apic_read(APIC_ESR
);
2653 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2654 apic_write(APIC_ESR
, 0);
2655 apic_read(APIC_ESR
);
2657 irq_remapping_reenable(x2apic_mode
);
2659 local_irq_restore(flags
);
2663 * This device has no shutdown method - fully functioning local APICs
2664 * are needed on every CPU up until machine_halt/restart/poweroff.
2667 static struct syscore_ops lapic_syscore_ops
= {
2668 .resume
= lapic_resume
,
2669 .suspend
= lapic_suspend
,
2672 static void apic_pm_activate(void)
2674 apic_pm_state
.active
= 1;
2677 static int __init
init_lapic_sysfs(void)
2679 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2680 if (boot_cpu_has(X86_FEATURE_APIC
))
2681 register_syscore_ops(&lapic_syscore_ops
);
2686 /* local apic needs to resume before other devices access its registers. */
2687 core_initcall(init_lapic_sysfs
);
2689 #else /* CONFIG_PM */
2691 static void apic_pm_activate(void) { }
2693 #endif /* CONFIG_PM */
2695 #ifdef CONFIG_X86_64
2697 static int multi_checked
;
2700 static int set_multi(const struct dmi_system_id
*d
)
2704 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2709 static const struct dmi_system_id multi_dmi_table
[] = {
2711 .callback
= set_multi
,
2712 .ident
= "IBM System Summit2",
2714 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2715 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2721 static void dmi_check_multi(void)
2726 dmi_check_system(multi_dmi_table
);
2731 * apic_is_clustered_box() -- Check if we can expect good TSC
2733 * Thus far, the major user of this is IBM's Summit2 series:
2734 * Clustered boxes may have unsynced TSC problems if they are
2736 * Use DMI to check them
2738 int apic_is_clustered_box(void)
2746 * APIC command line parameters
2748 static int __init
setup_disableapic(char *arg
)
2751 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2754 early_param("disableapic", setup_disableapic
);
2756 /* same as disableapic, for compatibility */
2757 static int __init
setup_nolapic(char *arg
)
2759 return setup_disableapic(arg
);
2761 early_param("nolapic", setup_nolapic
);
2763 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2765 local_apic_timer_c2_ok
= 1;
2768 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2770 static int __init
parse_disable_apic_timer(char *arg
)
2772 disable_apic_timer
= 1;
2775 early_param("noapictimer", parse_disable_apic_timer
);
2777 static int __init
parse_nolapic_timer(char *arg
)
2779 disable_apic_timer
= 1;
2782 early_param("nolapic_timer", parse_nolapic_timer
);
2784 static int __init
apic_set_verbosity(char *arg
)
2787 #ifdef CONFIG_X86_64
2788 skip_ioapic_setup
= 0;
2794 if (strcmp("debug", arg
) == 0)
2795 apic_verbosity
= APIC_DEBUG
;
2796 else if (strcmp("verbose", arg
) == 0)
2797 apic_verbosity
= APIC_VERBOSE
;
2798 #ifdef CONFIG_X86_64
2800 pr_warning("APIC Verbosity level %s not recognised"
2801 " use apic=verbose or apic=debug\n", arg
);
2808 early_param("apic", apic_set_verbosity
);
2810 static int __init
lapic_insert_resource(void)
2815 /* Put local APIC into the resource map. */
2816 lapic_resource
.start
= apic_phys
;
2817 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2818 insert_resource(&iomem_resource
, &lapic_resource
);
2824 * need call insert after e820__reserve_resources()
2825 * that is using request_resource
2827 late_initcall(lapic_insert_resource
);
2829 static int __init
apic_set_disabled_cpu_apicid(char *arg
)
2831 if (!arg
|| !get_option(&arg
, &disabled_cpu_apicid
))
2836 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid
);
2838 static int __init
apic_set_extnmi(char *arg
)
2843 if (!strncmp("all", arg
, 3))
2844 apic_extnmi
= APIC_EXTNMI_ALL
;
2845 else if (!strncmp("none", arg
, 4))
2846 apic_extnmi
= APIC_EXTNMI_NONE
;
2847 else if (!strncmp("bsp", arg
, 3))
2848 apic_extnmi
= APIC_EXTNMI_BSP
;
2850 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg
);
2856 early_param("apic_extnmi", apic_set_extnmi
);