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1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/nmi.h>
35 #include <linux/smp.h>
36 #include <linux/mm.h>
37
38 #include <asm/perf_event.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <asm/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8253.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
46 #include <asm/apic.h>
47 #include <asm/desc.h>
48 #include <asm/hpet.h>
49 #include <asm/idle.h>
50 #include <asm/mtrr.h>
51 #include <asm/smp.h>
52 #include <asm/mce.h>
53 #include <asm/kvm_para.h>
54 #include <asm/tsc.h>
55
56 unsigned int num_processors;
57
58 unsigned disabled_cpus __cpuinitdata;
59
60 /* Processor that is doing the boot up */
61 unsigned int boot_cpu_physical_apicid = -1U;
62
63 /*
64 * The highest APIC ID seen during enumeration.
65 */
66 unsigned int max_physical_apicid;
67
68 /*
69 * Bitmask of physically existing CPUs:
70 */
71 physid_mask_t phys_cpu_present_map;
72
73 /*
74 * Map cpu index to physical APIC ID
75 */
76 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
77 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
80
81 #ifdef CONFIG_X86_32
82 /*
83 * Knob to control our willingness to enable the local APIC.
84 *
85 * +1=force-enable
86 */
87 static int force_enable_local_apic;
88 /*
89 * APIC command line parameters
90 */
91 static int __init parse_lapic(char *arg)
92 {
93 force_enable_local_apic = 1;
94 return 0;
95 }
96 early_param("lapic", parse_lapic);
97 /* Local APIC was disabled by the BIOS and enabled by the kernel */
98 static int enabled_via_apicbase;
99
100 /*
101 * Handle interrupt mode configuration register (IMCR).
102 * This register controls whether the interrupt signals
103 * that reach the BSP come from the master PIC or from the
104 * local APIC. Before entering Symmetric I/O Mode, either
105 * the BIOS or the operating system must switch out of
106 * PIC Mode by changing the IMCR.
107 */
108 static inline void imcr_pic_to_apic(void)
109 {
110 /* select IMCR register */
111 outb(0x70, 0x22);
112 /* NMI and 8259 INTR go through APIC */
113 outb(0x01, 0x23);
114 }
115
116 static inline void imcr_apic_to_pic(void)
117 {
118 /* select IMCR register */
119 outb(0x70, 0x22);
120 /* NMI and 8259 INTR go directly to BSP */
121 outb(0x00, 0x23);
122 }
123 #endif
124
125 #ifdef CONFIG_X86_64
126 static int apic_calibrate_pmtmr __initdata;
127 static __init int setup_apicpmtimer(char *s)
128 {
129 apic_calibrate_pmtmr = 1;
130 notsc_setup(NULL);
131 return 0;
132 }
133 __setup("apicpmtimer", setup_apicpmtimer);
134 #endif
135
136 int x2apic_mode;
137 #ifdef CONFIG_X86_X2APIC
138 /* x2apic enabled before OS handover */
139 static int x2apic_preenabled;
140 static __init int setup_nox2apic(char *str)
141 {
142 if (x2apic_enabled()) {
143 pr_warning("Bios already enabled x2apic, "
144 "can't enforce nox2apic");
145 return 0;
146 }
147
148 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
149 return 0;
150 }
151 early_param("nox2apic", setup_nox2apic);
152 #endif
153
154 unsigned long mp_lapic_addr;
155 int disable_apic;
156 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
157 static int disable_apic_timer __cpuinitdata;
158 /* Local APIC timer works in C2 */
159 int local_apic_timer_c2_ok;
160 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
161
162 int first_system_vector = 0xfe;
163
164 /*
165 * Debug level, exported for io_apic.c
166 */
167 unsigned int apic_verbosity;
168
169 int pic_mode;
170
171 /* Have we found an MP table */
172 int smp_found_config;
173
174 static struct resource lapic_resource = {
175 .name = "Local APIC",
176 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
177 };
178
179 static unsigned int calibration_result;
180
181 static int lapic_next_event(unsigned long delta,
182 struct clock_event_device *evt);
183 static void lapic_timer_setup(enum clock_event_mode mode,
184 struct clock_event_device *evt);
185 static void lapic_timer_broadcast(const struct cpumask *mask);
186 static void apic_pm_activate(void);
187
188 /*
189 * The local apic timer can be used for any function which is CPU local.
190 */
191 static struct clock_event_device lapic_clockevent = {
192 .name = "lapic",
193 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
194 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
195 .shift = 32,
196 .set_mode = lapic_timer_setup,
197 .set_next_event = lapic_next_event,
198 .broadcast = lapic_timer_broadcast,
199 .rating = 100,
200 .irq = -1,
201 };
202 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
203
204 static unsigned long apic_phys;
205
206 /*
207 * Get the LAPIC version
208 */
209 static inline int lapic_get_version(void)
210 {
211 return GET_APIC_VERSION(apic_read(APIC_LVR));
212 }
213
214 /*
215 * Check, if the APIC is integrated or a separate chip
216 */
217 static inline int lapic_is_integrated(void)
218 {
219 #ifdef CONFIG_X86_64
220 return 1;
221 #else
222 return APIC_INTEGRATED(lapic_get_version());
223 #endif
224 }
225
226 /*
227 * Check, whether this is a modern or a first generation APIC
228 */
229 static int modern_apic(void)
230 {
231 /* AMD systems use old APIC versions, so check the CPU */
232 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
233 boot_cpu_data.x86 >= 0xf)
234 return 1;
235 return lapic_get_version() >= 0x14;
236 }
237
238 /*
239 * right after this call apic become NOOP driven
240 * so apic->write/read doesn't do anything
241 */
242 void apic_disable(void)
243 {
244 pr_info("APIC: switched to apic NOOP\n");
245 apic = &apic_noop;
246 }
247
248 void native_apic_wait_icr_idle(void)
249 {
250 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
251 cpu_relax();
252 }
253
254 u32 native_safe_apic_wait_icr_idle(void)
255 {
256 u32 send_status;
257 int timeout;
258
259 timeout = 0;
260 do {
261 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
262 if (!send_status)
263 break;
264 udelay(100);
265 } while (timeout++ < 1000);
266
267 return send_status;
268 }
269
270 void native_apic_icr_write(u32 low, u32 id)
271 {
272 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
273 apic_write(APIC_ICR, low);
274 }
275
276 u64 native_apic_icr_read(void)
277 {
278 u32 icr1, icr2;
279
280 icr2 = apic_read(APIC_ICR2);
281 icr1 = apic_read(APIC_ICR);
282
283 return icr1 | ((u64)icr2 << 32);
284 }
285
286 /**
287 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
288 */
289 void __cpuinit enable_NMI_through_LVT0(void)
290 {
291 unsigned int v;
292
293 /* unmask and set to NMI */
294 v = APIC_DM_NMI;
295
296 /* Level triggered for 82489DX (32bit mode) */
297 if (!lapic_is_integrated())
298 v |= APIC_LVT_LEVEL_TRIGGER;
299
300 apic_write(APIC_LVT0, v);
301 }
302
303 #ifdef CONFIG_X86_32
304 /**
305 * get_physical_broadcast - Get number of physical broadcast IDs
306 */
307 int get_physical_broadcast(void)
308 {
309 return modern_apic() ? 0xff : 0xf;
310 }
311 #endif
312
313 /**
314 * lapic_get_maxlvt - get the maximum number of local vector table entries
315 */
316 int lapic_get_maxlvt(void)
317 {
318 unsigned int v;
319
320 v = apic_read(APIC_LVR);
321 /*
322 * - we always have APIC integrated on 64bit mode
323 * - 82489DXs do not report # of LVT entries
324 */
325 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
326 }
327
328 /*
329 * Local APIC timer
330 */
331
332 /* Clock divisor */
333 #define APIC_DIVISOR 16
334
335 /*
336 * This function sets up the local APIC timer, with a timeout of
337 * 'clocks' APIC bus clock. During calibration we actually call
338 * this function twice on the boot CPU, once with a bogus timeout
339 * value, second time for real. The other (noncalibrating) CPUs
340 * call this function only once, with the real, calibrated value.
341 *
342 * We do reads before writes even if unnecessary, to get around the
343 * P5 APIC double write bug.
344 */
345 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
346 {
347 unsigned int lvtt_value, tmp_value;
348
349 lvtt_value = LOCAL_TIMER_VECTOR;
350 if (!oneshot)
351 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
352 if (!lapic_is_integrated())
353 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
354
355 if (!irqen)
356 lvtt_value |= APIC_LVT_MASKED;
357
358 apic_write(APIC_LVTT, lvtt_value);
359
360 /*
361 * Divide PICLK by 16
362 */
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
366 APIC_TDR_DIV_16);
367
368 if (!oneshot)
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
370 }
371
372 /*
373 * Setup extended LVT, AMD specific
374 *
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
379 * available.
380 *
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
385 *
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
390 */
391
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395 {
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
399 }
400
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402 {
403 unsigned int rsvd; /* 0: uninitialized */
404
405 if (offset >= APIC_EILVT_NR_MAX)
406 return ~0;
407
408 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
409 do {
410 if (rsvd &&
411 !eilvt_entry_is_changeable(rsvd, new))
412 /* may not change if vectors are different */
413 return rsvd;
414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 } while (rsvd != new);
416
417 return new;
418 }
419
420 /*
421 * If mask=1, the LVT entry does not generate interrupts while mask=0
422 * enables the vector. See also the BKDGs.
423 */
424
425 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
426 {
427 unsigned long reg = APIC_EILVTn(offset);
428 unsigned int new, old, reserved;
429
430 new = (mask << 16) | (msg_type << 8) | vector;
431 old = apic_read(reg);
432 reserved = reserve_eilvt_offset(offset, new);
433
434 if (reserved != new) {
435 pr_err(FW_BUG "cpu %d, try to setup vector 0x%x, but "
436 "vector 0x%x was already reserved by another core, "
437 "APIC%lX=0x%x\n",
438 smp_processor_id(), new, reserved, reg, old);
439 return -EINVAL;
440 }
441
442 if (!eilvt_entry_is_changeable(old, new)) {
443 pr_err(FW_BUG "cpu %d, try to setup vector 0x%x but "
444 "register already in use, APIC%lX=0x%x\n",
445 smp_processor_id(), new, reg, old);
446 return -EBUSY;
447 }
448
449 apic_write(reg, new);
450
451 return 0;
452 }
453 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
454
455 /*
456 * Program the next event, relative to now
457 */
458 static int lapic_next_event(unsigned long delta,
459 struct clock_event_device *evt)
460 {
461 apic_write(APIC_TMICT, delta);
462 return 0;
463 }
464
465 /*
466 * Setup the lapic timer in periodic or oneshot mode
467 */
468 static void lapic_timer_setup(enum clock_event_mode mode,
469 struct clock_event_device *evt)
470 {
471 unsigned long flags;
472 unsigned int v;
473
474 /* Lapic used as dummy for broadcast ? */
475 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
476 return;
477
478 local_irq_save(flags);
479
480 switch (mode) {
481 case CLOCK_EVT_MODE_PERIODIC:
482 case CLOCK_EVT_MODE_ONESHOT:
483 __setup_APIC_LVTT(calibration_result,
484 mode != CLOCK_EVT_MODE_PERIODIC, 1);
485 break;
486 case CLOCK_EVT_MODE_UNUSED:
487 case CLOCK_EVT_MODE_SHUTDOWN:
488 v = apic_read(APIC_LVTT);
489 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
490 apic_write(APIC_LVTT, v);
491 apic_write(APIC_TMICT, 0);
492 break;
493 case CLOCK_EVT_MODE_RESUME:
494 /* Nothing to do here */
495 break;
496 }
497
498 local_irq_restore(flags);
499 }
500
501 /*
502 * Local APIC timer broadcast function
503 */
504 static void lapic_timer_broadcast(const struct cpumask *mask)
505 {
506 #ifdef CONFIG_SMP
507 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
508 #endif
509 }
510
511 /*
512 * Setup the local APIC timer for this CPU. Copy the initialized values
513 * of the boot CPU and register the clock event in the framework.
514 */
515 static void __cpuinit setup_APIC_timer(void)
516 {
517 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
518
519 if (cpu_has(&current_cpu_data, X86_FEATURE_ARAT)) {
520 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
521 /* Make LAPIC timer preferrable over percpu HPET */
522 lapic_clockevent.rating = 150;
523 }
524
525 memcpy(levt, &lapic_clockevent, sizeof(*levt));
526 levt->cpumask = cpumask_of(smp_processor_id());
527
528 clockevents_register_device(levt);
529 }
530
531 /*
532 * In this functions we calibrate APIC bus clocks to the external timer.
533 *
534 * We want to do the calibration only once since we want to have local timer
535 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
536 * frequency.
537 *
538 * This was previously done by reading the PIT/HPET and waiting for a wrap
539 * around to find out, that a tick has elapsed. I have a box, where the PIT
540 * readout is broken, so it never gets out of the wait loop again. This was
541 * also reported by others.
542 *
543 * Monitoring the jiffies value is inaccurate and the clockevents
544 * infrastructure allows us to do a simple substitution of the interrupt
545 * handler.
546 *
547 * The calibration routine also uses the pm_timer when possible, as the PIT
548 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
549 * back to normal later in the boot process).
550 */
551
552 #define LAPIC_CAL_LOOPS (HZ/10)
553
554 static __initdata int lapic_cal_loops = -1;
555 static __initdata long lapic_cal_t1, lapic_cal_t2;
556 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
557 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
558 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
559
560 /*
561 * Temporary interrupt handler.
562 */
563 static void __init lapic_cal_handler(struct clock_event_device *dev)
564 {
565 unsigned long long tsc = 0;
566 long tapic = apic_read(APIC_TMCCT);
567 unsigned long pm = acpi_pm_read_early();
568
569 if (cpu_has_tsc)
570 rdtscll(tsc);
571
572 switch (lapic_cal_loops++) {
573 case 0:
574 lapic_cal_t1 = tapic;
575 lapic_cal_tsc1 = tsc;
576 lapic_cal_pm1 = pm;
577 lapic_cal_j1 = jiffies;
578 break;
579
580 case LAPIC_CAL_LOOPS:
581 lapic_cal_t2 = tapic;
582 lapic_cal_tsc2 = tsc;
583 if (pm < lapic_cal_pm1)
584 pm += ACPI_PM_OVRRUN;
585 lapic_cal_pm2 = pm;
586 lapic_cal_j2 = jiffies;
587 break;
588 }
589 }
590
591 static int __init
592 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
593 {
594 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
595 const long pm_thresh = pm_100ms / 100;
596 unsigned long mult;
597 u64 res;
598
599 #ifndef CONFIG_X86_PM_TIMER
600 return -1;
601 #endif
602
603 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
604
605 /* Check, if the PM timer is available */
606 if (!deltapm)
607 return -1;
608
609 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
610
611 if (deltapm > (pm_100ms - pm_thresh) &&
612 deltapm < (pm_100ms + pm_thresh)) {
613 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
614 return 0;
615 }
616
617 res = (((u64)deltapm) * mult) >> 22;
618 do_div(res, 1000000);
619 pr_warning("APIC calibration not consistent "
620 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
621
622 /* Correct the lapic counter value */
623 res = (((u64)(*delta)) * pm_100ms);
624 do_div(res, deltapm);
625 pr_info("APIC delta adjusted to PM-Timer: "
626 "%lu (%ld)\n", (unsigned long)res, *delta);
627 *delta = (long)res;
628
629 /* Correct the tsc counter value */
630 if (cpu_has_tsc) {
631 res = (((u64)(*deltatsc)) * pm_100ms);
632 do_div(res, deltapm);
633 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
634 "PM-Timer: %lu (%ld)\n",
635 (unsigned long)res, *deltatsc);
636 *deltatsc = (long)res;
637 }
638
639 return 0;
640 }
641
642 static int __init calibrate_APIC_clock(void)
643 {
644 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
645 void (*real_handler)(struct clock_event_device *dev);
646 unsigned long deltaj;
647 long delta, deltatsc;
648 int pm_referenced = 0;
649
650 local_irq_disable();
651
652 /* Replace the global interrupt handler */
653 real_handler = global_clock_event->event_handler;
654 global_clock_event->event_handler = lapic_cal_handler;
655
656 /*
657 * Setup the APIC counter to maximum. There is no way the lapic
658 * can underflow in the 100ms detection time frame
659 */
660 __setup_APIC_LVTT(0xffffffff, 0, 0);
661
662 /* Let the interrupts run */
663 local_irq_enable();
664
665 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
666 cpu_relax();
667
668 local_irq_disable();
669
670 /* Restore the real event handler */
671 global_clock_event->event_handler = real_handler;
672
673 /* Build delta t1-t2 as apic timer counts down */
674 delta = lapic_cal_t1 - lapic_cal_t2;
675 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
676
677 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
678
679 /* we trust the PM based calibration if possible */
680 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
681 &delta, &deltatsc);
682
683 /* Calculate the scaled math multiplication factor */
684 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
685 lapic_clockevent.shift);
686 lapic_clockevent.max_delta_ns =
687 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
688 lapic_clockevent.min_delta_ns =
689 clockevent_delta2ns(0xF, &lapic_clockevent);
690
691 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
692
693 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
694 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
695 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
696 calibration_result);
697
698 if (cpu_has_tsc) {
699 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
700 "%ld.%04ld MHz.\n",
701 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
702 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
703 }
704
705 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
706 "%u.%04u MHz.\n",
707 calibration_result / (1000000 / HZ),
708 calibration_result % (1000000 / HZ));
709
710 /*
711 * Do a sanity check on the APIC calibration result
712 */
713 if (calibration_result < (1000000 / HZ)) {
714 local_irq_enable();
715 pr_warning("APIC frequency too slow, disabling apic timer\n");
716 return -1;
717 }
718
719 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
720
721 /*
722 * PM timer calibration failed or not turned on
723 * so lets try APIC timer based calibration
724 */
725 if (!pm_referenced) {
726 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
727
728 /*
729 * Setup the apic timer manually
730 */
731 levt->event_handler = lapic_cal_handler;
732 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
733 lapic_cal_loops = -1;
734
735 /* Let the interrupts run */
736 local_irq_enable();
737
738 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
739 cpu_relax();
740
741 /* Stop the lapic timer */
742 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
743
744 /* Jiffies delta */
745 deltaj = lapic_cal_j2 - lapic_cal_j1;
746 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
747
748 /* Check, if the jiffies result is consistent */
749 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
750 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
751 else
752 levt->features |= CLOCK_EVT_FEAT_DUMMY;
753 } else
754 local_irq_enable();
755
756 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
757 pr_warning("APIC timer disabled due to verification failure\n");
758 return -1;
759 }
760
761 return 0;
762 }
763
764 /*
765 * Setup the boot APIC
766 *
767 * Calibrate and verify the result.
768 */
769 void __init setup_boot_APIC_clock(void)
770 {
771 /*
772 * The local apic timer can be disabled via the kernel
773 * commandline or from the CPU detection code. Register the lapic
774 * timer as a dummy clock event source on SMP systems, so the
775 * broadcast mechanism is used. On UP systems simply ignore it.
776 */
777 if (disable_apic_timer) {
778 pr_info("Disabling APIC timer\n");
779 /* No broadcast on UP ! */
780 if (num_possible_cpus() > 1) {
781 lapic_clockevent.mult = 1;
782 setup_APIC_timer();
783 }
784 return;
785 }
786
787 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
788 "calibrating APIC timer ...\n");
789
790 if (calibrate_APIC_clock()) {
791 /* No broadcast on UP ! */
792 if (num_possible_cpus() > 1)
793 setup_APIC_timer();
794 return;
795 }
796
797 /*
798 * If nmi_watchdog is set to IO_APIC, we need the
799 * PIT/HPET going. Otherwise register lapic as a dummy
800 * device.
801 */
802 if (nmi_watchdog != NMI_IO_APIC)
803 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
804 else
805 pr_warning("APIC timer registered as dummy,"
806 " due to nmi_watchdog=%d!\n", nmi_watchdog);
807
808 /* Setup the lapic or request the broadcast */
809 setup_APIC_timer();
810 }
811
812 void __cpuinit setup_secondary_APIC_clock(void)
813 {
814 setup_APIC_timer();
815 }
816
817 /*
818 * The guts of the apic timer interrupt
819 */
820 static void local_apic_timer_interrupt(void)
821 {
822 int cpu = smp_processor_id();
823 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
824
825 /*
826 * Normally we should not be here till LAPIC has been initialized but
827 * in some cases like kdump, its possible that there is a pending LAPIC
828 * timer interrupt from previous kernel's context and is delivered in
829 * new kernel the moment interrupts are enabled.
830 *
831 * Interrupts are enabled early and LAPIC is setup much later, hence
832 * its possible that when we get here evt->event_handler is NULL.
833 * Check for event_handler being NULL and discard the interrupt as
834 * spurious.
835 */
836 if (!evt->event_handler) {
837 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
838 /* Switch it off */
839 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
840 return;
841 }
842
843 /*
844 * the NMI deadlock-detector uses this.
845 */
846 inc_irq_stat(apic_timer_irqs);
847
848 evt->event_handler(evt);
849 }
850
851 /*
852 * Local APIC timer interrupt. This is the most natural way for doing
853 * local interrupts, but local timer interrupts can be emulated by
854 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
855 *
856 * [ if a single-CPU system runs an SMP kernel then we call the local
857 * interrupt as well. Thus we cannot inline the local irq ... ]
858 */
859 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
860 {
861 struct pt_regs *old_regs = set_irq_regs(regs);
862
863 /*
864 * NOTE! We'd better ACK the irq immediately,
865 * because timer handling can be slow.
866 */
867 ack_APIC_irq();
868 /*
869 * update_process_times() expects us to have done irq_enter().
870 * Besides, if we don't timer interrupts ignore the global
871 * interrupt lock, which is the WrongThing (tm) to do.
872 */
873 exit_idle();
874 irq_enter();
875 local_apic_timer_interrupt();
876 irq_exit();
877
878 set_irq_regs(old_regs);
879 }
880
881 int setup_profiling_timer(unsigned int multiplier)
882 {
883 return -EINVAL;
884 }
885
886 /*
887 * Local APIC start and shutdown
888 */
889
890 /**
891 * clear_local_APIC - shutdown the local APIC
892 *
893 * This is called, when a CPU is disabled and before rebooting, so the state of
894 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
895 * leftovers during boot.
896 */
897 void clear_local_APIC(void)
898 {
899 int maxlvt;
900 u32 v;
901
902 /* APIC hasn't been mapped yet */
903 if (!x2apic_mode && !apic_phys)
904 return;
905
906 maxlvt = lapic_get_maxlvt();
907 /*
908 * Masking an LVT entry can trigger a local APIC error
909 * if the vector is zero. Mask LVTERR first to prevent this.
910 */
911 if (maxlvt >= 3) {
912 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
913 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
914 }
915 /*
916 * Careful: we have to set masks only first to deassert
917 * any level-triggered sources.
918 */
919 v = apic_read(APIC_LVTT);
920 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
921 v = apic_read(APIC_LVT0);
922 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
923 v = apic_read(APIC_LVT1);
924 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
925 if (maxlvt >= 4) {
926 v = apic_read(APIC_LVTPC);
927 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
928 }
929
930 /* lets not touch this if we didn't frob it */
931 #ifdef CONFIG_X86_THERMAL_VECTOR
932 if (maxlvt >= 5) {
933 v = apic_read(APIC_LVTTHMR);
934 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
935 }
936 #endif
937 #ifdef CONFIG_X86_MCE_INTEL
938 if (maxlvt >= 6) {
939 v = apic_read(APIC_LVTCMCI);
940 if (!(v & APIC_LVT_MASKED))
941 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
942 }
943 #endif
944
945 /*
946 * Clean APIC state for other OSs:
947 */
948 apic_write(APIC_LVTT, APIC_LVT_MASKED);
949 apic_write(APIC_LVT0, APIC_LVT_MASKED);
950 apic_write(APIC_LVT1, APIC_LVT_MASKED);
951 if (maxlvt >= 3)
952 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
953 if (maxlvt >= 4)
954 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
955
956 /* Integrated APIC (!82489DX) ? */
957 if (lapic_is_integrated()) {
958 if (maxlvt > 3)
959 /* Clear ESR due to Pentium errata 3AP and 11AP */
960 apic_write(APIC_ESR, 0);
961 apic_read(APIC_ESR);
962 }
963 }
964
965 /**
966 * disable_local_APIC - clear and disable the local APIC
967 */
968 void disable_local_APIC(void)
969 {
970 unsigned int value;
971
972 /* APIC hasn't been mapped yet */
973 if (!x2apic_mode && !apic_phys)
974 return;
975
976 clear_local_APIC();
977
978 /*
979 * Disable APIC (implies clearing of registers
980 * for 82489DX!).
981 */
982 value = apic_read(APIC_SPIV);
983 value &= ~APIC_SPIV_APIC_ENABLED;
984 apic_write(APIC_SPIV, value);
985
986 #ifdef CONFIG_X86_32
987 /*
988 * When LAPIC was disabled by the BIOS and enabled by the kernel,
989 * restore the disabled state.
990 */
991 if (enabled_via_apicbase) {
992 unsigned int l, h;
993
994 rdmsr(MSR_IA32_APICBASE, l, h);
995 l &= ~MSR_IA32_APICBASE_ENABLE;
996 wrmsr(MSR_IA32_APICBASE, l, h);
997 }
998 #endif
999 }
1000
1001 /*
1002 * If Linux enabled the LAPIC against the BIOS default disable it down before
1003 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1004 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1005 * for the case where Linux didn't enable the LAPIC.
1006 */
1007 void lapic_shutdown(void)
1008 {
1009 unsigned long flags;
1010
1011 if (!cpu_has_apic && !apic_from_smp_config())
1012 return;
1013
1014 local_irq_save(flags);
1015
1016 #ifdef CONFIG_X86_32
1017 if (!enabled_via_apicbase)
1018 clear_local_APIC();
1019 else
1020 #endif
1021 disable_local_APIC();
1022
1023
1024 local_irq_restore(flags);
1025 }
1026
1027 /*
1028 * This is to verify that we're looking at a real local APIC.
1029 * Check these against your board if the CPUs aren't getting
1030 * started for no apparent reason.
1031 */
1032 int __init verify_local_APIC(void)
1033 {
1034 unsigned int reg0, reg1;
1035
1036 /*
1037 * The version register is read-only in a real APIC.
1038 */
1039 reg0 = apic_read(APIC_LVR);
1040 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1041 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1042 reg1 = apic_read(APIC_LVR);
1043 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1044
1045 /*
1046 * The two version reads above should print the same
1047 * numbers. If the second one is different, then we
1048 * poke at a non-APIC.
1049 */
1050 if (reg1 != reg0)
1051 return 0;
1052
1053 /*
1054 * Check if the version looks reasonably.
1055 */
1056 reg1 = GET_APIC_VERSION(reg0);
1057 if (reg1 == 0x00 || reg1 == 0xff)
1058 return 0;
1059 reg1 = lapic_get_maxlvt();
1060 if (reg1 < 0x02 || reg1 == 0xff)
1061 return 0;
1062
1063 /*
1064 * The ID register is read/write in a real APIC.
1065 */
1066 reg0 = apic_read(APIC_ID);
1067 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1068 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1069 reg1 = apic_read(APIC_ID);
1070 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1071 apic_write(APIC_ID, reg0);
1072 if (reg1 != (reg0 ^ apic->apic_id_mask))
1073 return 0;
1074
1075 /*
1076 * The next two are just to see if we have sane values.
1077 * They're only really relevant if we're in Virtual Wire
1078 * compatibility mode, but most boxes are anymore.
1079 */
1080 reg0 = apic_read(APIC_LVT0);
1081 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1082 reg1 = apic_read(APIC_LVT1);
1083 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1084
1085 return 1;
1086 }
1087
1088 /**
1089 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1090 */
1091 void __init sync_Arb_IDs(void)
1092 {
1093 /*
1094 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1095 * needed on AMD.
1096 */
1097 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1098 return;
1099
1100 /*
1101 * Wait for idle.
1102 */
1103 apic_wait_icr_idle();
1104
1105 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1106 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1107 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1108 }
1109
1110 /*
1111 * An initial setup of the virtual wire mode.
1112 */
1113 void __init init_bsp_APIC(void)
1114 {
1115 unsigned int value;
1116
1117 /*
1118 * Don't do the setup now if we have a SMP BIOS as the
1119 * through-I/O-APIC virtual wire mode might be active.
1120 */
1121 if (smp_found_config || !cpu_has_apic)
1122 return;
1123
1124 /*
1125 * Do not trust the local APIC being empty at bootup.
1126 */
1127 clear_local_APIC();
1128
1129 /*
1130 * Enable APIC.
1131 */
1132 value = apic_read(APIC_SPIV);
1133 value &= ~APIC_VECTOR_MASK;
1134 value |= APIC_SPIV_APIC_ENABLED;
1135
1136 #ifdef CONFIG_X86_32
1137 /* This bit is reserved on P4/Xeon and should be cleared */
1138 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1139 (boot_cpu_data.x86 == 15))
1140 value &= ~APIC_SPIV_FOCUS_DISABLED;
1141 else
1142 #endif
1143 value |= APIC_SPIV_FOCUS_DISABLED;
1144 value |= SPURIOUS_APIC_VECTOR;
1145 apic_write(APIC_SPIV, value);
1146
1147 /*
1148 * Set up the virtual wire mode.
1149 */
1150 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1151 value = APIC_DM_NMI;
1152 if (!lapic_is_integrated()) /* 82489DX */
1153 value |= APIC_LVT_LEVEL_TRIGGER;
1154 apic_write(APIC_LVT1, value);
1155 }
1156
1157 static void __cpuinit lapic_setup_esr(void)
1158 {
1159 unsigned int oldvalue, value, maxlvt;
1160
1161 if (!lapic_is_integrated()) {
1162 pr_info("No ESR for 82489DX.\n");
1163 return;
1164 }
1165
1166 if (apic->disable_esr) {
1167 /*
1168 * Something untraceable is creating bad interrupts on
1169 * secondary quads ... for the moment, just leave the
1170 * ESR disabled - we can't do anything useful with the
1171 * errors anyway - mbligh
1172 */
1173 pr_info("Leaving ESR disabled.\n");
1174 return;
1175 }
1176
1177 maxlvt = lapic_get_maxlvt();
1178 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1179 apic_write(APIC_ESR, 0);
1180 oldvalue = apic_read(APIC_ESR);
1181
1182 /* enables sending errors */
1183 value = ERROR_APIC_VECTOR;
1184 apic_write(APIC_LVTERR, value);
1185
1186 /*
1187 * spec says clear errors after enabling vector.
1188 */
1189 if (maxlvt > 3)
1190 apic_write(APIC_ESR, 0);
1191 value = apic_read(APIC_ESR);
1192 if (value != oldvalue)
1193 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1194 "vector: 0x%08x after: 0x%08x\n",
1195 oldvalue, value);
1196 }
1197
1198
1199 /**
1200 * setup_local_APIC - setup the local APIC
1201 */
1202 void __cpuinit setup_local_APIC(void)
1203 {
1204 unsigned int value, queued;
1205 int i, j, acked = 0;
1206 unsigned long long tsc = 0, ntsc;
1207 long long max_loops = cpu_khz;
1208
1209 if (cpu_has_tsc)
1210 rdtscll(tsc);
1211
1212 if (disable_apic) {
1213 arch_disable_smp_support();
1214 return;
1215 }
1216
1217 #ifdef CONFIG_X86_32
1218 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1219 if (lapic_is_integrated() && apic->disable_esr) {
1220 apic_write(APIC_ESR, 0);
1221 apic_write(APIC_ESR, 0);
1222 apic_write(APIC_ESR, 0);
1223 apic_write(APIC_ESR, 0);
1224 }
1225 #endif
1226 perf_events_lapic_init();
1227
1228 preempt_disable();
1229
1230 /*
1231 * Double-check whether this APIC is really registered.
1232 * This is meaningless in clustered apic mode, so we skip it.
1233 */
1234 BUG_ON(!apic->apic_id_registered());
1235
1236 /*
1237 * Intel recommends to set DFR, LDR and TPR before enabling
1238 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1239 * document number 292116). So here it goes...
1240 */
1241 apic->init_apic_ldr();
1242
1243 /*
1244 * Set Task Priority to 'accept all'. We never change this
1245 * later on.
1246 */
1247 value = apic_read(APIC_TASKPRI);
1248 value &= ~APIC_TPRI_MASK;
1249 apic_write(APIC_TASKPRI, value);
1250
1251 /*
1252 * After a crash, we no longer service the interrupts and a pending
1253 * interrupt from previous kernel might still have ISR bit set.
1254 *
1255 * Most probably by now CPU has serviced that pending interrupt and
1256 * it might not have done the ack_APIC_irq() because it thought,
1257 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1258 * does not clear the ISR bit and cpu thinks it has already serivced
1259 * the interrupt. Hence a vector might get locked. It was noticed
1260 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1261 */
1262 do {
1263 queued = 0;
1264 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1265 queued |= apic_read(APIC_IRR + i*0x10);
1266
1267 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1268 value = apic_read(APIC_ISR + i*0x10);
1269 for (j = 31; j >= 0; j--) {
1270 if (value & (1<<j)) {
1271 ack_APIC_irq();
1272 acked++;
1273 }
1274 }
1275 }
1276 if (acked > 256) {
1277 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1278 acked);
1279 break;
1280 }
1281 if (cpu_has_tsc) {
1282 rdtscll(ntsc);
1283 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1284 } else
1285 max_loops--;
1286 } while (queued && max_loops > 0);
1287 WARN_ON(max_loops <= 0);
1288
1289 /*
1290 * Now that we are all set up, enable the APIC
1291 */
1292 value = apic_read(APIC_SPIV);
1293 value &= ~APIC_VECTOR_MASK;
1294 /*
1295 * Enable APIC
1296 */
1297 value |= APIC_SPIV_APIC_ENABLED;
1298
1299 #ifdef CONFIG_X86_32
1300 /*
1301 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1302 * certain networking cards. If high frequency interrupts are
1303 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1304 * entry is masked/unmasked at a high rate as well then sooner or
1305 * later IOAPIC line gets 'stuck', no more interrupts are received
1306 * from the device. If focus CPU is disabled then the hang goes
1307 * away, oh well :-(
1308 *
1309 * [ This bug can be reproduced easily with a level-triggered
1310 * PCI Ne2000 networking cards and PII/PIII processors, dual
1311 * BX chipset. ]
1312 */
1313 /*
1314 * Actually disabling the focus CPU check just makes the hang less
1315 * frequent as it makes the interrupt distributon model be more
1316 * like LRU than MRU (the short-term load is more even across CPUs).
1317 * See also the comment in end_level_ioapic_irq(). --macro
1318 */
1319
1320 /*
1321 * - enable focus processor (bit==0)
1322 * - 64bit mode always use processor focus
1323 * so no need to set it
1324 */
1325 value &= ~APIC_SPIV_FOCUS_DISABLED;
1326 #endif
1327
1328 /*
1329 * Set spurious IRQ vector
1330 */
1331 value |= SPURIOUS_APIC_VECTOR;
1332 apic_write(APIC_SPIV, value);
1333
1334 /*
1335 * Set up LVT0, LVT1:
1336 *
1337 * set up through-local-APIC on the BP's LINT0. This is not
1338 * strictly necessary in pure symmetric-IO mode, but sometimes
1339 * we delegate interrupts to the 8259A.
1340 */
1341 /*
1342 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1343 */
1344 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1345 if (!smp_processor_id() && (pic_mode || !value)) {
1346 value = APIC_DM_EXTINT;
1347 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1348 smp_processor_id());
1349 } else {
1350 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1351 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1352 smp_processor_id());
1353 }
1354 apic_write(APIC_LVT0, value);
1355
1356 /*
1357 * only the BP should see the LINT1 NMI signal, obviously.
1358 */
1359 if (!smp_processor_id())
1360 value = APIC_DM_NMI;
1361 else
1362 value = APIC_DM_NMI | APIC_LVT_MASKED;
1363 if (!lapic_is_integrated()) /* 82489DX */
1364 value |= APIC_LVT_LEVEL_TRIGGER;
1365 apic_write(APIC_LVT1, value);
1366
1367 preempt_enable();
1368
1369 #ifdef CONFIG_X86_MCE_INTEL
1370 /* Recheck CMCI information after local APIC is up on CPU #0 */
1371 if (smp_processor_id() == 0)
1372 cmci_recheck();
1373 #endif
1374 }
1375
1376 void __cpuinit end_local_APIC_setup(void)
1377 {
1378 lapic_setup_esr();
1379
1380 #ifdef CONFIG_X86_32
1381 {
1382 unsigned int value;
1383 /* Disable the local apic timer */
1384 value = apic_read(APIC_LVTT);
1385 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1386 apic_write(APIC_LVTT, value);
1387 }
1388 #endif
1389
1390 setup_apic_nmi_watchdog(NULL);
1391 apic_pm_activate();
1392
1393 /*
1394 * Now that local APIC setup is completed for BP, configure the fault
1395 * handling for interrupt remapping.
1396 */
1397 if (!smp_processor_id() && intr_remapping_enabled)
1398 enable_drhd_fault_handling();
1399
1400 }
1401
1402 #ifdef CONFIG_X86_X2APIC
1403 void check_x2apic(void)
1404 {
1405 if (x2apic_enabled()) {
1406 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1407 x2apic_preenabled = x2apic_mode = 1;
1408 }
1409 }
1410
1411 void enable_x2apic(void)
1412 {
1413 int msr, msr2;
1414
1415 if (!x2apic_mode)
1416 return;
1417
1418 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1419 if (!(msr & X2APIC_ENABLE)) {
1420 printk_once(KERN_INFO "Enabling x2apic\n");
1421 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1422 }
1423 }
1424 #endif /* CONFIG_X86_X2APIC */
1425
1426 int __init enable_IR(void)
1427 {
1428 #ifdef CONFIG_INTR_REMAP
1429 if (!intr_remapping_supported()) {
1430 pr_debug("intr-remapping not supported\n");
1431 return 0;
1432 }
1433
1434 if (!x2apic_preenabled && skip_ioapic_setup) {
1435 pr_info("Skipped enabling intr-remap because of skipping "
1436 "io-apic setup\n");
1437 return 0;
1438 }
1439
1440 if (enable_intr_remapping(x2apic_supported()))
1441 return 0;
1442
1443 pr_info("Enabled Interrupt-remapping\n");
1444
1445 return 1;
1446
1447 #endif
1448 return 0;
1449 }
1450
1451 void __init enable_IR_x2apic(void)
1452 {
1453 unsigned long flags;
1454 struct IO_APIC_route_entry **ioapic_entries = NULL;
1455 int ret, x2apic_enabled = 0;
1456 int dmar_table_init_ret;
1457
1458 dmar_table_init_ret = dmar_table_init();
1459 if (dmar_table_init_ret && !x2apic_supported())
1460 return;
1461
1462 ioapic_entries = alloc_ioapic_entries();
1463 if (!ioapic_entries) {
1464 pr_err("Allocate ioapic_entries failed\n");
1465 goto out;
1466 }
1467
1468 ret = save_IO_APIC_setup(ioapic_entries);
1469 if (ret) {
1470 pr_info("Saving IO-APIC state failed: %d\n", ret);
1471 goto out;
1472 }
1473
1474 local_irq_save(flags);
1475 legacy_pic->mask_all();
1476 mask_IO_APIC_setup(ioapic_entries);
1477
1478 if (dmar_table_init_ret)
1479 ret = 0;
1480 else
1481 ret = enable_IR();
1482
1483 if (!ret) {
1484 /* IR is required if there is APIC ID > 255 even when running
1485 * under KVM
1486 */
1487 if (max_physical_apicid > 255 || !kvm_para_available())
1488 goto nox2apic;
1489 /*
1490 * without IR all CPUs can be addressed by IOAPIC/MSI
1491 * only in physical mode
1492 */
1493 x2apic_force_phys();
1494 }
1495
1496 x2apic_enabled = 1;
1497
1498 if (x2apic_supported() && !x2apic_mode) {
1499 x2apic_mode = 1;
1500 enable_x2apic();
1501 pr_info("Enabled x2apic\n");
1502 }
1503
1504 nox2apic:
1505 if (!ret) /* IR enabling failed */
1506 restore_IO_APIC_setup(ioapic_entries);
1507 legacy_pic->restore_mask();
1508 local_irq_restore(flags);
1509
1510 out:
1511 if (ioapic_entries)
1512 free_ioapic_entries(ioapic_entries);
1513
1514 if (x2apic_enabled)
1515 return;
1516
1517 if (x2apic_preenabled)
1518 panic("x2apic: enabled by BIOS but kernel init failed.");
1519 else if (cpu_has_x2apic)
1520 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1521 }
1522
1523 #ifdef CONFIG_X86_64
1524 /*
1525 * Detect and enable local APICs on non-SMP boards.
1526 * Original code written by Keir Fraser.
1527 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1528 * not correctly set up (usually the APIC timer won't work etc.)
1529 */
1530 static int __init detect_init_APIC(void)
1531 {
1532 if (!cpu_has_apic) {
1533 pr_info("No local APIC present\n");
1534 return -1;
1535 }
1536
1537 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1538 return 0;
1539 }
1540 #else
1541
1542 static int apic_verify(void)
1543 {
1544 u32 features, h, l;
1545
1546 /*
1547 * The APIC feature bit should now be enabled
1548 * in `cpuid'
1549 */
1550 features = cpuid_edx(1);
1551 if (!(features & (1 << X86_FEATURE_APIC))) {
1552 pr_warning("Could not enable APIC!\n");
1553 return -1;
1554 }
1555 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1556 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1557
1558 /* The BIOS may have set up the APIC at some other address */
1559 rdmsr(MSR_IA32_APICBASE, l, h);
1560 if (l & MSR_IA32_APICBASE_ENABLE)
1561 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1562
1563 pr_info("Found and enabled local APIC!\n");
1564 return 0;
1565 }
1566
1567 int apic_force_enable(void)
1568 {
1569 u32 h, l;
1570
1571 if (disable_apic)
1572 return -1;
1573
1574 /*
1575 * Some BIOSes disable the local APIC in the APIC_BASE
1576 * MSR. This can only be done in software for Intel P6 or later
1577 * and AMD K7 (Model > 1) or later.
1578 */
1579 rdmsr(MSR_IA32_APICBASE, l, h);
1580 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1581 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1582 l &= ~MSR_IA32_APICBASE_BASE;
1583 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1584 wrmsr(MSR_IA32_APICBASE, l, h);
1585 enabled_via_apicbase = 1;
1586 }
1587 return apic_verify();
1588 }
1589
1590 /*
1591 * Detect and initialize APIC
1592 */
1593 static int __init detect_init_APIC(void)
1594 {
1595 /* Disabled by kernel option? */
1596 if (disable_apic)
1597 return -1;
1598
1599 switch (boot_cpu_data.x86_vendor) {
1600 case X86_VENDOR_AMD:
1601 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1602 (boot_cpu_data.x86 >= 15))
1603 break;
1604 goto no_apic;
1605 case X86_VENDOR_INTEL:
1606 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1607 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1608 break;
1609 goto no_apic;
1610 default:
1611 goto no_apic;
1612 }
1613
1614 if (!cpu_has_apic) {
1615 /*
1616 * Over-ride BIOS and try to enable the local APIC only if
1617 * "lapic" specified.
1618 */
1619 if (!force_enable_local_apic) {
1620 pr_info("Local APIC disabled by BIOS -- "
1621 "you can enable it with \"lapic\"\n");
1622 return -1;
1623 }
1624 if (apic_force_enable())
1625 return -1;
1626 } else {
1627 if (apic_verify())
1628 return -1;
1629 }
1630
1631 apic_pm_activate();
1632
1633 return 0;
1634
1635 no_apic:
1636 pr_info("No local APIC present or hardware disabled\n");
1637 return -1;
1638 }
1639 #endif
1640
1641 #ifdef CONFIG_X86_64
1642 void __init early_init_lapic_mapping(void)
1643 {
1644 /*
1645 * If no local APIC can be found then go out
1646 * : it means there is no mpatable and MADT
1647 */
1648 if (!smp_found_config)
1649 return;
1650
1651 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
1652 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1653 APIC_BASE, mp_lapic_addr);
1654
1655 /*
1656 * Fetch the APIC ID of the BSP in case we have a
1657 * default configuration (or the MP table is broken).
1658 */
1659 boot_cpu_physical_apicid = read_apic_id();
1660 }
1661 #endif
1662
1663 /**
1664 * init_apic_mappings - initialize APIC mappings
1665 */
1666 void __init init_apic_mappings(void)
1667 {
1668 unsigned int new_apicid;
1669
1670 if (x2apic_mode) {
1671 boot_cpu_physical_apicid = read_apic_id();
1672 return;
1673 }
1674
1675 /* If no local APIC can be found return early */
1676 if (!smp_found_config && detect_init_APIC()) {
1677 /* lets NOP'ify apic operations */
1678 pr_info("APIC: disable apic facility\n");
1679 apic_disable();
1680 } else {
1681 apic_phys = mp_lapic_addr;
1682
1683 /*
1684 * acpi lapic path already maps that address in
1685 * acpi_register_lapic_address()
1686 */
1687 if (!acpi_lapic && !smp_found_config)
1688 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1689
1690 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1691 APIC_BASE, apic_phys);
1692 }
1693
1694 /*
1695 * Fetch the APIC ID of the BSP in case we have a
1696 * default configuration (or the MP table is broken).
1697 */
1698 new_apicid = read_apic_id();
1699 if (boot_cpu_physical_apicid != new_apicid) {
1700 boot_cpu_physical_apicid = new_apicid;
1701 /*
1702 * yeah -- we lie about apic_version
1703 * in case if apic was disabled via boot option
1704 * but it's not a problem for SMP compiled kernel
1705 * since smp_sanity_check is prepared for such a case
1706 * and disable smp mode
1707 */
1708 apic_version[new_apicid] =
1709 GET_APIC_VERSION(apic_read(APIC_LVR));
1710 }
1711 }
1712
1713 /*
1714 * This initializes the IO-APIC and APIC hardware if this is
1715 * a UP kernel.
1716 */
1717 int apic_version[MAX_LOCAL_APIC];
1718
1719 int __init APIC_init_uniprocessor(void)
1720 {
1721 if (disable_apic) {
1722 pr_info("Apic disabled\n");
1723 return -1;
1724 }
1725 #ifdef CONFIG_X86_64
1726 if (!cpu_has_apic) {
1727 disable_apic = 1;
1728 pr_info("Apic disabled by BIOS\n");
1729 return -1;
1730 }
1731 #else
1732 if (!smp_found_config && !cpu_has_apic)
1733 return -1;
1734
1735 /*
1736 * Complain if the BIOS pretends there is one.
1737 */
1738 if (!cpu_has_apic &&
1739 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1740 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1741 boot_cpu_physical_apicid);
1742 return -1;
1743 }
1744 #endif
1745
1746 default_setup_apic_routing();
1747
1748 verify_local_APIC();
1749 connect_bsp_APIC();
1750
1751 #ifdef CONFIG_X86_64
1752 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1753 #else
1754 /*
1755 * Hack: In case of kdump, after a crash, kernel might be booting
1756 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1757 * might be zero if read from MP tables. Get it from LAPIC.
1758 */
1759 # ifdef CONFIG_CRASH_DUMP
1760 boot_cpu_physical_apicid = read_apic_id();
1761 # endif
1762 #endif
1763 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1764 setup_local_APIC();
1765
1766 #ifdef CONFIG_X86_IO_APIC
1767 /*
1768 * Now enable IO-APICs, actually call clear_IO_APIC
1769 * We need clear_IO_APIC before enabling error vector
1770 */
1771 if (!skip_ioapic_setup && nr_ioapics)
1772 enable_IO_APIC();
1773 #endif
1774
1775 end_local_APIC_setup();
1776
1777 #ifdef CONFIG_X86_IO_APIC
1778 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1779 setup_IO_APIC();
1780 else {
1781 nr_ioapics = 0;
1782 localise_nmi_watchdog();
1783 }
1784 #else
1785 localise_nmi_watchdog();
1786 #endif
1787
1788 x86_init.timers.setup_percpu_clockev();
1789 #ifdef CONFIG_X86_64
1790 check_nmi_watchdog();
1791 #endif
1792
1793 return 0;
1794 }
1795
1796 /*
1797 * Local APIC interrupts
1798 */
1799
1800 /*
1801 * This interrupt should _never_ happen with our APIC/SMP architecture
1802 */
1803 void smp_spurious_interrupt(struct pt_regs *regs)
1804 {
1805 u32 v;
1806
1807 exit_idle();
1808 irq_enter();
1809 /*
1810 * Check if this really is a spurious interrupt and ACK it
1811 * if it is a vectored one. Just in case...
1812 * Spurious interrupts should not be ACKed.
1813 */
1814 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1815 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1816 ack_APIC_irq();
1817
1818 inc_irq_stat(irq_spurious_count);
1819
1820 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1821 pr_info("spurious APIC interrupt on CPU#%d, "
1822 "should never happen.\n", smp_processor_id());
1823 irq_exit();
1824 }
1825
1826 /*
1827 * This interrupt should never happen with our APIC/SMP architecture
1828 */
1829 void smp_error_interrupt(struct pt_regs *regs)
1830 {
1831 u32 v, v1;
1832
1833 exit_idle();
1834 irq_enter();
1835 /* First tickle the hardware, only then report what went on. -- REW */
1836 v = apic_read(APIC_ESR);
1837 apic_write(APIC_ESR, 0);
1838 v1 = apic_read(APIC_ESR);
1839 ack_APIC_irq();
1840 atomic_inc(&irq_err_count);
1841
1842 /*
1843 * Here is what the APIC error bits mean:
1844 * 0: Send CS error
1845 * 1: Receive CS error
1846 * 2: Send accept error
1847 * 3: Receive accept error
1848 * 4: Reserved
1849 * 5: Send illegal vector
1850 * 6: Received illegal vector
1851 * 7: Illegal register address
1852 */
1853 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1854 smp_processor_id(), v , v1);
1855 irq_exit();
1856 }
1857
1858 /**
1859 * connect_bsp_APIC - attach the APIC to the interrupt system
1860 */
1861 void __init connect_bsp_APIC(void)
1862 {
1863 #ifdef CONFIG_X86_32
1864 if (pic_mode) {
1865 /*
1866 * Do not trust the local APIC being empty at bootup.
1867 */
1868 clear_local_APIC();
1869 /*
1870 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1871 * local APIC to INT and NMI lines.
1872 */
1873 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1874 "enabling APIC mode.\n");
1875 imcr_pic_to_apic();
1876 }
1877 #endif
1878 if (apic->enable_apic_mode)
1879 apic->enable_apic_mode();
1880 }
1881
1882 /**
1883 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1884 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1885 *
1886 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1887 * APIC is disabled.
1888 */
1889 void disconnect_bsp_APIC(int virt_wire_setup)
1890 {
1891 unsigned int value;
1892
1893 #ifdef CONFIG_X86_32
1894 if (pic_mode) {
1895 /*
1896 * Put the board back into PIC mode (has an effect only on
1897 * certain older boards). Note that APIC interrupts, including
1898 * IPIs, won't work beyond this point! The only exception are
1899 * INIT IPIs.
1900 */
1901 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1902 "entering PIC mode.\n");
1903 imcr_apic_to_pic();
1904 return;
1905 }
1906 #endif
1907
1908 /* Go back to Virtual Wire compatibility mode */
1909
1910 /* For the spurious interrupt use vector F, and enable it */
1911 value = apic_read(APIC_SPIV);
1912 value &= ~APIC_VECTOR_MASK;
1913 value |= APIC_SPIV_APIC_ENABLED;
1914 value |= 0xf;
1915 apic_write(APIC_SPIV, value);
1916
1917 if (!virt_wire_setup) {
1918 /*
1919 * For LVT0 make it edge triggered, active high,
1920 * external and enabled
1921 */
1922 value = apic_read(APIC_LVT0);
1923 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1924 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1925 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1926 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1927 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1928 apic_write(APIC_LVT0, value);
1929 } else {
1930 /* Disable LVT0 */
1931 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1932 }
1933
1934 /*
1935 * For LVT1 make it edge triggered, active high,
1936 * nmi and enabled
1937 */
1938 value = apic_read(APIC_LVT1);
1939 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1940 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1941 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1942 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1943 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1944 apic_write(APIC_LVT1, value);
1945 }
1946
1947 void __cpuinit generic_processor_info(int apicid, int version)
1948 {
1949 int cpu;
1950
1951 /*
1952 * Validate version
1953 */
1954 if (version == 0x0) {
1955 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1956 "fixing up to 0x10. (tell your hw vendor)\n",
1957 version);
1958 version = 0x10;
1959 }
1960 apic_version[apicid] = version;
1961
1962 if (num_processors >= nr_cpu_ids) {
1963 int max = nr_cpu_ids;
1964 int thiscpu = max + disabled_cpus;
1965
1966 pr_warning(
1967 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1968 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1969
1970 disabled_cpus++;
1971 return;
1972 }
1973
1974 num_processors++;
1975 cpu = cpumask_next_zero(-1, cpu_present_mask);
1976
1977 if (version != apic_version[boot_cpu_physical_apicid])
1978 WARN_ONCE(1,
1979 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1980 apic_version[boot_cpu_physical_apicid], cpu, version);
1981
1982 physid_set(apicid, phys_cpu_present_map);
1983 if (apicid == boot_cpu_physical_apicid) {
1984 /*
1985 * x86_bios_cpu_apicid is required to have processors listed
1986 * in same order as logical cpu numbers. Hence the first
1987 * entry is BSP, and so on.
1988 */
1989 cpu = 0;
1990 }
1991 if (apicid > max_physical_apicid)
1992 max_physical_apicid = apicid;
1993
1994 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1995 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1996 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1997 #endif
1998
1999 set_cpu_possible(cpu, true);
2000 set_cpu_present(cpu, true);
2001 }
2002
2003 int hard_smp_processor_id(void)
2004 {
2005 return read_apic_id();
2006 }
2007
2008 void default_init_apic_ldr(void)
2009 {
2010 unsigned long val;
2011
2012 apic_write(APIC_DFR, APIC_DFR_VALUE);
2013 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2014 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2015 apic_write(APIC_LDR, val);
2016 }
2017
2018 #ifdef CONFIG_X86_32
2019 int default_apicid_to_node(int logical_apicid)
2020 {
2021 #ifdef CONFIG_SMP
2022 return apicid_2_node[hard_smp_processor_id()];
2023 #else
2024 return 0;
2025 #endif
2026 }
2027 #endif
2028
2029 /*
2030 * Power management
2031 */
2032 #ifdef CONFIG_PM
2033
2034 static struct {
2035 /*
2036 * 'active' is true if the local APIC was enabled by us and
2037 * not the BIOS; this signifies that we are also responsible
2038 * for disabling it before entering apm/acpi suspend
2039 */
2040 int active;
2041 /* r/w apic fields */
2042 unsigned int apic_id;
2043 unsigned int apic_taskpri;
2044 unsigned int apic_ldr;
2045 unsigned int apic_dfr;
2046 unsigned int apic_spiv;
2047 unsigned int apic_lvtt;
2048 unsigned int apic_lvtpc;
2049 unsigned int apic_lvt0;
2050 unsigned int apic_lvt1;
2051 unsigned int apic_lvterr;
2052 unsigned int apic_tmict;
2053 unsigned int apic_tdcr;
2054 unsigned int apic_thmr;
2055 } apic_pm_state;
2056
2057 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
2058 {
2059 unsigned long flags;
2060 int maxlvt;
2061
2062 if (!apic_pm_state.active)
2063 return 0;
2064
2065 maxlvt = lapic_get_maxlvt();
2066
2067 apic_pm_state.apic_id = apic_read(APIC_ID);
2068 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2069 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2070 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2071 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2072 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2073 if (maxlvt >= 4)
2074 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2075 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2076 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2077 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2078 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2079 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2080 #ifdef CONFIG_X86_THERMAL_VECTOR
2081 if (maxlvt >= 5)
2082 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2083 #endif
2084
2085 local_irq_save(flags);
2086 disable_local_APIC();
2087
2088 if (intr_remapping_enabled)
2089 disable_intr_remapping();
2090
2091 local_irq_restore(flags);
2092 return 0;
2093 }
2094
2095 static int lapic_resume(struct sys_device *dev)
2096 {
2097 unsigned int l, h;
2098 unsigned long flags;
2099 int maxlvt;
2100 int ret = 0;
2101 struct IO_APIC_route_entry **ioapic_entries = NULL;
2102
2103 if (!apic_pm_state.active)
2104 return 0;
2105
2106 local_irq_save(flags);
2107 if (intr_remapping_enabled) {
2108 ioapic_entries = alloc_ioapic_entries();
2109 if (!ioapic_entries) {
2110 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2111 ret = -ENOMEM;
2112 goto restore;
2113 }
2114
2115 ret = save_IO_APIC_setup(ioapic_entries);
2116 if (ret) {
2117 WARN(1, "Saving IO-APIC state failed: %d\n", ret);
2118 free_ioapic_entries(ioapic_entries);
2119 goto restore;
2120 }
2121
2122 mask_IO_APIC_setup(ioapic_entries);
2123 legacy_pic->mask_all();
2124 }
2125
2126 if (x2apic_mode)
2127 enable_x2apic();
2128 else {
2129 /*
2130 * Make sure the APICBASE points to the right address
2131 *
2132 * FIXME! This will be wrong if we ever support suspend on
2133 * SMP! We'll need to do this as part of the CPU restore!
2134 */
2135 rdmsr(MSR_IA32_APICBASE, l, h);
2136 l &= ~MSR_IA32_APICBASE_BASE;
2137 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2138 wrmsr(MSR_IA32_APICBASE, l, h);
2139 }
2140
2141 maxlvt = lapic_get_maxlvt();
2142 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2143 apic_write(APIC_ID, apic_pm_state.apic_id);
2144 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2145 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2146 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2147 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2148 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2149 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2150 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2151 if (maxlvt >= 5)
2152 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2153 #endif
2154 if (maxlvt >= 4)
2155 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2156 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2157 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2158 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2159 apic_write(APIC_ESR, 0);
2160 apic_read(APIC_ESR);
2161 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2162 apic_write(APIC_ESR, 0);
2163 apic_read(APIC_ESR);
2164
2165 if (intr_remapping_enabled) {
2166 reenable_intr_remapping(x2apic_mode);
2167 legacy_pic->restore_mask();
2168 restore_IO_APIC_setup(ioapic_entries);
2169 free_ioapic_entries(ioapic_entries);
2170 }
2171 restore:
2172 local_irq_restore(flags);
2173
2174 return ret;
2175 }
2176
2177 /*
2178 * This device has no shutdown method - fully functioning local APICs
2179 * are needed on every CPU up until machine_halt/restart/poweroff.
2180 */
2181
2182 static struct sysdev_class lapic_sysclass = {
2183 .name = "lapic",
2184 .resume = lapic_resume,
2185 .suspend = lapic_suspend,
2186 };
2187
2188 static struct sys_device device_lapic = {
2189 .id = 0,
2190 .cls = &lapic_sysclass,
2191 };
2192
2193 static void __cpuinit apic_pm_activate(void)
2194 {
2195 apic_pm_state.active = 1;
2196 }
2197
2198 static int __init init_lapic_sysfs(void)
2199 {
2200 int error;
2201
2202 if (!cpu_has_apic)
2203 return 0;
2204 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2205
2206 error = sysdev_class_register(&lapic_sysclass);
2207 if (!error)
2208 error = sysdev_register(&device_lapic);
2209 return error;
2210 }
2211
2212 /* local apic needs to resume before other devices access its registers. */
2213 core_initcall(init_lapic_sysfs);
2214
2215 #else /* CONFIG_PM */
2216
2217 static void apic_pm_activate(void) { }
2218
2219 #endif /* CONFIG_PM */
2220
2221 #ifdef CONFIG_X86_64
2222
2223 static int __cpuinit apic_cluster_num(void)
2224 {
2225 int i, clusters, zeros;
2226 unsigned id;
2227 u16 *bios_cpu_apicid;
2228 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2229
2230 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2231 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2232
2233 for (i = 0; i < nr_cpu_ids; i++) {
2234 /* are we being called early in kernel startup? */
2235 if (bios_cpu_apicid) {
2236 id = bios_cpu_apicid[i];
2237 } else if (i < nr_cpu_ids) {
2238 if (cpu_present(i))
2239 id = per_cpu(x86_bios_cpu_apicid, i);
2240 else
2241 continue;
2242 } else
2243 break;
2244
2245 if (id != BAD_APICID)
2246 __set_bit(APIC_CLUSTERID(id), clustermap);
2247 }
2248
2249 /* Problem: Partially populated chassis may not have CPUs in some of
2250 * the APIC clusters they have been allocated. Only present CPUs have
2251 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2252 * Since clusters are allocated sequentially, count zeros only if
2253 * they are bounded by ones.
2254 */
2255 clusters = 0;
2256 zeros = 0;
2257 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2258 if (test_bit(i, clustermap)) {
2259 clusters += 1 + zeros;
2260 zeros = 0;
2261 } else
2262 ++zeros;
2263 }
2264
2265 return clusters;
2266 }
2267
2268 static int __cpuinitdata multi_checked;
2269 static int __cpuinitdata multi;
2270
2271 static int __cpuinit set_multi(const struct dmi_system_id *d)
2272 {
2273 if (multi)
2274 return 0;
2275 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2276 multi = 1;
2277 return 0;
2278 }
2279
2280 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2281 {
2282 .callback = set_multi,
2283 .ident = "IBM System Summit2",
2284 .matches = {
2285 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2286 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2287 },
2288 },
2289 {}
2290 };
2291
2292 static void __cpuinit dmi_check_multi(void)
2293 {
2294 if (multi_checked)
2295 return;
2296
2297 dmi_check_system(multi_dmi_table);
2298 multi_checked = 1;
2299 }
2300
2301 /*
2302 * apic_is_clustered_box() -- Check if we can expect good TSC
2303 *
2304 * Thus far, the major user of this is IBM's Summit2 series:
2305 * Clustered boxes may have unsynced TSC problems if they are
2306 * multi-chassis.
2307 * Use DMI to check them
2308 */
2309 __cpuinit int apic_is_clustered_box(void)
2310 {
2311 dmi_check_multi();
2312 if (multi)
2313 return 1;
2314
2315 if (!is_vsmp_box())
2316 return 0;
2317
2318 /*
2319 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2320 * not guaranteed to be synced between boards
2321 */
2322 if (apic_cluster_num() > 1)
2323 return 1;
2324
2325 return 0;
2326 }
2327 #endif
2328
2329 /*
2330 * APIC command line parameters
2331 */
2332 static int __init setup_disableapic(char *arg)
2333 {
2334 disable_apic = 1;
2335 setup_clear_cpu_cap(X86_FEATURE_APIC);
2336 return 0;
2337 }
2338 early_param("disableapic", setup_disableapic);
2339
2340 /* same as disableapic, for compatibility */
2341 static int __init setup_nolapic(char *arg)
2342 {
2343 return setup_disableapic(arg);
2344 }
2345 early_param("nolapic", setup_nolapic);
2346
2347 static int __init parse_lapic_timer_c2_ok(char *arg)
2348 {
2349 local_apic_timer_c2_ok = 1;
2350 return 0;
2351 }
2352 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2353
2354 static int __init parse_disable_apic_timer(char *arg)
2355 {
2356 disable_apic_timer = 1;
2357 return 0;
2358 }
2359 early_param("noapictimer", parse_disable_apic_timer);
2360
2361 static int __init parse_nolapic_timer(char *arg)
2362 {
2363 disable_apic_timer = 1;
2364 return 0;
2365 }
2366 early_param("nolapic_timer", parse_nolapic_timer);
2367
2368 static int __init apic_set_verbosity(char *arg)
2369 {
2370 if (!arg) {
2371 #ifdef CONFIG_X86_64
2372 skip_ioapic_setup = 0;
2373 return 0;
2374 #endif
2375 return -EINVAL;
2376 }
2377
2378 if (strcmp("debug", arg) == 0)
2379 apic_verbosity = APIC_DEBUG;
2380 else if (strcmp("verbose", arg) == 0)
2381 apic_verbosity = APIC_VERBOSE;
2382 else {
2383 pr_warning("APIC Verbosity level %s not recognised"
2384 " use apic=verbose or apic=debug\n", arg);
2385 return -EINVAL;
2386 }
2387
2388 return 0;
2389 }
2390 early_param("apic", apic_set_verbosity);
2391
2392 static int __init lapic_insert_resource(void)
2393 {
2394 if (!apic_phys)
2395 return -1;
2396
2397 /* Put local APIC into the resource map. */
2398 lapic_resource.start = apic_phys;
2399 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2400 insert_resource(&iomem_resource, &lapic_resource);
2401
2402 return 0;
2403 }
2404
2405 /*
2406 * need call insert after e820_reserve_resources()
2407 * that is using request_resource
2408 */
2409 late_initcall(lapic_insert_resource);