2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_counter.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/nmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_counter.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <asm/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8253.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
53 #include <asm/kvm_para.h>
55 unsigned int num_processors
;
57 unsigned disabled_cpus __cpuinitdata
;
59 /* Processor that is doing the boot up */
60 unsigned int boot_cpu_physical_apicid
= -1U;
63 * The highest APIC ID seen during enumeration.
65 * This determines the messaging protocol we can use: if all APIC IDs
66 * are in the 0 ... 7 range, then we can use logical addressing which
67 * has some performance advantages (better broadcasting).
69 * If there's an APIC ID above 8, we use physical addressing.
71 unsigned int max_physical_apicid
;
74 * Bitmask of physically existing CPUs:
76 physid_mask_t phys_cpu_present_map
;
79 * Map cpu index to physical APIC ID
81 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
82 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
83 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
84 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
88 * Knob to control our willingness to enable the local APIC.
92 static int force_enable_local_apic
;
94 * APIC command line parameters
96 static int __init
parse_lapic(char *arg
)
98 force_enable_local_apic
= 1;
101 early_param("lapic", parse_lapic
);
102 /* Local APIC was disabled by the BIOS and enabled by the kernel */
103 static int enabled_via_apicbase
;
106 * Handle interrupt mode configuration register (IMCR).
107 * This register controls whether the interrupt signals
108 * that reach the BSP come from the master PIC or from the
109 * local APIC. Before entering Symmetric I/O Mode, either
110 * the BIOS or the operating system must switch out of
111 * PIC Mode by changing the IMCR.
113 static inline void imcr_pic_to_apic(void)
115 /* select IMCR register */
117 /* NMI and 8259 INTR go through APIC */
121 static inline void imcr_apic_to_pic(void)
123 /* select IMCR register */
125 /* NMI and 8259 INTR go directly to BSP */
131 static int apic_calibrate_pmtmr __initdata
;
132 static __init
int setup_apicpmtimer(char *s
)
134 apic_calibrate_pmtmr
= 1;
138 __setup("apicpmtimer", setup_apicpmtimer
);
142 #ifdef CONFIG_X86_X2APIC
143 /* x2apic enabled before OS handover */
144 static int x2apic_preenabled
;
145 static __init
int setup_nox2apic(char *str
)
147 if (x2apic_enabled()) {
148 pr_warning("Bios already enabled x2apic, "
149 "can't enforce nox2apic");
153 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
156 early_param("nox2apic", setup_nox2apic
);
159 unsigned long mp_lapic_addr
;
161 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
162 static int disable_apic_timer __cpuinitdata
;
163 /* Local APIC timer works in C2 */
164 int local_apic_timer_c2_ok
;
165 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
167 int first_system_vector
= 0xfe;
170 * Debug level, exported for io_apic.c
172 unsigned int apic_verbosity
;
176 /* Have we found an MP table */
177 int smp_found_config
;
179 static struct resource lapic_resource
= {
180 .name
= "Local APIC",
181 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
184 static unsigned int calibration_result
;
186 static int lapic_next_event(unsigned long delta
,
187 struct clock_event_device
*evt
);
188 static void lapic_timer_setup(enum clock_event_mode mode
,
189 struct clock_event_device
*evt
);
190 static void lapic_timer_broadcast(const struct cpumask
*mask
);
191 static void apic_pm_activate(void);
194 * The local apic timer can be used for any function which is CPU local.
196 static struct clock_event_device lapic_clockevent
= {
198 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
199 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
201 .set_mode
= lapic_timer_setup
,
202 .set_next_event
= lapic_next_event
,
203 .broadcast
= lapic_timer_broadcast
,
207 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
209 static unsigned long apic_phys
;
212 * Get the LAPIC version
214 static inline int lapic_get_version(void)
216 return GET_APIC_VERSION(apic_read(APIC_LVR
));
220 * Check, if the APIC is integrated or a separate chip
222 static inline int lapic_is_integrated(void)
227 return APIC_INTEGRATED(lapic_get_version());
232 * Check, whether this is a modern or a first generation APIC
234 static int modern_apic(void)
236 /* AMD systems use old APIC versions, so check the CPU */
237 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
238 boot_cpu_data
.x86
>= 0xf)
240 return lapic_get_version() >= 0x14;
244 * bare function to substitute write operation
245 * and it's _that_ fast :)
247 static void native_apic_write_dummy(u32 reg
, u32 v
)
249 WARN_ON_ONCE((cpu_has_apic
|| !disable_apic
));
252 static u32
native_apic_read_dummy(u32 reg
)
254 WARN_ON_ONCE((cpu_has_apic
&& !disable_apic
));
259 * right after this call apic->write/read doesn't do anything
260 * note that there is no restore operation it works one way
262 void apic_disable(void)
264 apic
->read
= native_apic_read_dummy
;
265 apic
->write
= native_apic_write_dummy
;
268 void native_apic_wait_icr_idle(void)
270 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
274 u32
native_safe_apic_wait_icr_idle(void)
281 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
285 } while (timeout
++ < 1000);
290 void native_apic_icr_write(u32 low
, u32 id
)
292 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
293 apic_write(APIC_ICR
, low
);
296 u64
native_apic_icr_read(void)
300 icr2
= apic_read(APIC_ICR2
);
301 icr1
= apic_read(APIC_ICR
);
303 return icr1
| ((u64
)icr2
<< 32);
307 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
309 void __cpuinit
enable_NMI_through_LVT0(void)
313 /* unmask and set to NMI */
316 /* Level triggered for 82489DX (32bit mode) */
317 if (!lapic_is_integrated())
318 v
|= APIC_LVT_LEVEL_TRIGGER
;
320 apic_write(APIC_LVT0
, v
);
325 * get_physical_broadcast - Get number of physical broadcast IDs
327 int get_physical_broadcast(void)
329 return modern_apic() ? 0xff : 0xf;
334 * lapic_get_maxlvt - get the maximum number of local vector table entries
336 int lapic_get_maxlvt(void)
340 v
= apic_read(APIC_LVR
);
342 * - we always have APIC integrated on 64bit mode
343 * - 82489DXs do not report # of LVT entries
345 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
353 #define APIC_DIVISOR 16
356 * This function sets up the local APIC timer, with a timeout of
357 * 'clocks' APIC bus clock. During calibration we actually call
358 * this function twice on the boot CPU, once with a bogus timeout
359 * value, second time for real. The other (noncalibrating) CPUs
360 * call this function only once, with the real, calibrated value.
362 * We do reads before writes even if unnecessary, to get around the
363 * P5 APIC double write bug.
365 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
367 unsigned int lvtt_value
, tmp_value
;
369 lvtt_value
= LOCAL_TIMER_VECTOR
;
371 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
372 if (!lapic_is_integrated())
373 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
376 lvtt_value
|= APIC_LVT_MASKED
;
378 apic_write(APIC_LVTT
, lvtt_value
);
383 tmp_value
= apic_read(APIC_TDCR
);
384 apic_write(APIC_TDCR
,
385 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
389 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
393 * Setup extended LVT, AMD specific (K8, family 10h)
395 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
396 * MCE interrupts are supported. Thus MCE offset must be set to 0.
398 * If mask=1, the LVT entry does not generate interrupts while mask=0
399 * enables the vector. See also the BKDGs.
402 #define APIC_EILVT_LVTOFF_MCE 0
403 #define APIC_EILVT_LVTOFF_IBS 1
405 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
407 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVTn(0);
408 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
413 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
415 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
416 return APIC_EILVT_LVTOFF_MCE
;
419 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
421 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
422 return APIC_EILVT_LVTOFF_IBS
;
424 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
427 * Program the next event, relative to now
429 static int lapic_next_event(unsigned long delta
,
430 struct clock_event_device
*evt
)
432 apic_write(APIC_TMICT
, delta
);
437 * Setup the lapic timer in periodic or oneshot mode
439 static void lapic_timer_setup(enum clock_event_mode mode
,
440 struct clock_event_device
*evt
)
445 /* Lapic used as dummy for broadcast ? */
446 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
449 local_irq_save(flags
);
452 case CLOCK_EVT_MODE_PERIODIC
:
453 case CLOCK_EVT_MODE_ONESHOT
:
454 __setup_APIC_LVTT(calibration_result
,
455 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
457 case CLOCK_EVT_MODE_UNUSED
:
458 case CLOCK_EVT_MODE_SHUTDOWN
:
459 v
= apic_read(APIC_LVTT
);
460 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
461 apic_write(APIC_LVTT
, v
);
462 apic_write(APIC_TMICT
, 0xffffffff);
464 case CLOCK_EVT_MODE_RESUME
:
465 /* Nothing to do here */
469 local_irq_restore(flags
);
473 * Local APIC timer broadcast function
475 static void lapic_timer_broadcast(const struct cpumask
*mask
)
478 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
483 * Setup the local APIC timer for this CPU. Copy the initilized values
484 * of the boot CPU and register the clock event in the framework.
486 static void __cpuinit
setup_APIC_timer(void)
488 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
490 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
491 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
492 /* Make LAPIC timer preferrable over percpu HPET */
493 lapic_clockevent
.rating
= 150;
496 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
497 levt
->cpumask
= cpumask_of(smp_processor_id());
499 clockevents_register_device(levt
);
503 * In this functions we calibrate APIC bus clocks to the external timer.
505 * We want to do the calibration only once since we want to have local timer
506 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
509 * This was previously done by reading the PIT/HPET and waiting for a wrap
510 * around to find out, that a tick has elapsed. I have a box, where the PIT
511 * readout is broken, so it never gets out of the wait loop again. This was
512 * also reported by others.
514 * Monitoring the jiffies value is inaccurate and the clockevents
515 * infrastructure allows us to do a simple substitution of the interrupt
518 * The calibration routine also uses the pm_timer when possible, as the PIT
519 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
520 * back to normal later in the boot process).
523 #define LAPIC_CAL_LOOPS (HZ/10)
525 static __initdata
int lapic_cal_loops
= -1;
526 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
527 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
528 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
529 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
532 * Temporary interrupt handler.
534 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
536 unsigned long long tsc
= 0;
537 long tapic
= apic_read(APIC_TMCCT
);
538 unsigned long pm
= acpi_pm_read_early();
543 switch (lapic_cal_loops
++) {
545 lapic_cal_t1
= tapic
;
546 lapic_cal_tsc1
= tsc
;
548 lapic_cal_j1
= jiffies
;
551 case LAPIC_CAL_LOOPS
:
552 lapic_cal_t2
= tapic
;
553 lapic_cal_tsc2
= tsc
;
554 if (pm
< lapic_cal_pm1
)
555 pm
+= ACPI_PM_OVRRUN
;
557 lapic_cal_j2
= jiffies
;
563 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
565 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
566 const long pm_thresh
= pm_100ms
/ 100;
570 #ifndef CONFIG_X86_PM_TIMER
574 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
576 /* Check, if the PM timer is available */
580 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
582 if (deltapm
> (pm_100ms
- pm_thresh
) &&
583 deltapm
< (pm_100ms
+ pm_thresh
)) {
584 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
588 res
= (((u64
)deltapm
) * mult
) >> 22;
589 do_div(res
, 1000000);
590 pr_warning("APIC calibration not consistent "
591 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
593 /* Correct the lapic counter value */
594 res
= (((u64
)(*delta
)) * pm_100ms
);
595 do_div(res
, deltapm
);
596 pr_info("APIC delta adjusted to PM-Timer: "
597 "%lu (%ld)\n", (unsigned long)res
, *delta
);
600 /* Correct the tsc counter value */
602 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
603 do_div(res
, deltapm
);
604 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
605 "PM-Timer: %lu (%ld) \n",
606 (unsigned long)res
, *deltatsc
);
607 *deltatsc
= (long)res
;
613 static int __init
calibrate_APIC_clock(void)
615 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
616 void (*real_handler
)(struct clock_event_device
*dev
);
617 unsigned long deltaj
;
618 long delta
, deltatsc
;
619 int pm_referenced
= 0;
623 /* Replace the global interrupt handler */
624 real_handler
= global_clock_event
->event_handler
;
625 global_clock_event
->event_handler
= lapic_cal_handler
;
628 * Setup the APIC counter to maximum. There is no way the lapic
629 * can underflow in the 100ms detection time frame
631 __setup_APIC_LVTT(0xffffffff, 0, 0);
633 /* Let the interrupts run */
636 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
641 /* Restore the real event handler */
642 global_clock_event
->event_handler
= real_handler
;
644 /* Build delta t1-t2 as apic timer counts down */
645 delta
= lapic_cal_t1
- lapic_cal_t2
;
646 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
648 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
650 /* we trust the PM based calibration if possible */
651 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
654 /* Calculate the scaled math multiplication factor */
655 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
656 lapic_clockevent
.shift
);
657 lapic_clockevent
.max_delta_ns
=
658 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
659 lapic_clockevent
.min_delta_ns
=
660 clockevent_delta2ns(0xF, &lapic_clockevent
);
662 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
664 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
665 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
666 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
670 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
672 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
673 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
676 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
678 calibration_result
/ (1000000 / HZ
),
679 calibration_result
% (1000000 / HZ
));
682 * Do a sanity check on the APIC calibration result
684 if (calibration_result
< (1000000 / HZ
)) {
686 pr_warning("APIC frequency too slow, disabling apic timer\n");
690 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
693 * PM timer calibration failed or not turned on
694 * so lets try APIC timer based calibration
696 if (!pm_referenced
) {
697 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
700 * Setup the apic timer manually
702 levt
->event_handler
= lapic_cal_handler
;
703 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
704 lapic_cal_loops
= -1;
706 /* Let the interrupts run */
709 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
712 /* Stop the lapic timer */
713 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
716 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
717 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
719 /* Check, if the jiffies result is consistent */
720 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
721 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
723 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
727 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
728 pr_warning("APIC timer disabled due to verification failure\n");
736 * Setup the boot APIC
738 * Calibrate and verify the result.
740 void __init
setup_boot_APIC_clock(void)
743 * The local apic timer can be disabled via the kernel
744 * commandline or from the CPU detection code. Register the lapic
745 * timer as a dummy clock event source on SMP systems, so the
746 * broadcast mechanism is used. On UP systems simply ignore it.
748 if (disable_apic_timer
) {
749 pr_info("Disabling APIC timer\n");
750 /* No broadcast on UP ! */
751 if (num_possible_cpus() > 1) {
752 lapic_clockevent
.mult
= 1;
758 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
759 "calibrating APIC timer ...\n");
761 if (calibrate_APIC_clock()) {
762 /* No broadcast on UP ! */
763 if (num_possible_cpus() > 1)
769 * If nmi_watchdog is set to IO_APIC, we need the
770 * PIT/HPET going. Otherwise register lapic as a dummy
773 if (nmi_watchdog
!= NMI_IO_APIC
)
774 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
776 pr_warning("APIC timer registered as dummy,"
777 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
779 /* Setup the lapic or request the broadcast */
783 void __cpuinit
setup_secondary_APIC_clock(void)
789 * The guts of the apic timer interrupt
791 static void local_apic_timer_interrupt(void)
793 int cpu
= smp_processor_id();
794 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
797 * Normally we should not be here till LAPIC has been initialized but
798 * in some cases like kdump, its possible that there is a pending LAPIC
799 * timer interrupt from previous kernel's context and is delivered in
800 * new kernel the moment interrupts are enabled.
802 * Interrupts are enabled early and LAPIC is setup much later, hence
803 * its possible that when we get here evt->event_handler is NULL.
804 * Check for event_handler being NULL and discard the interrupt as
807 if (!evt
->event_handler
) {
808 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
810 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
815 * the NMI deadlock-detector uses this.
817 inc_irq_stat(apic_timer_irqs
);
819 evt
->event_handler(evt
);
823 * Local APIC timer interrupt. This is the most natural way for doing
824 * local interrupts, but local timer interrupts can be emulated by
825 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
827 * [ if a single-CPU system runs an SMP kernel then we call the local
828 * interrupt as well. Thus we cannot inline the local irq ... ]
830 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
832 struct pt_regs
*old_regs
= set_irq_regs(regs
);
835 * NOTE! We'd better ACK the irq immediately,
836 * because timer handling can be slow.
840 * update_process_times() expects us to have done irq_enter().
841 * Besides, if we don't timer interrupts ignore the global
842 * interrupt lock, which is the WrongThing (tm) to do.
846 local_apic_timer_interrupt();
849 set_irq_regs(old_regs
);
852 int setup_profiling_timer(unsigned int multiplier
)
858 * Local APIC start and shutdown
862 * clear_local_APIC - shutdown the local APIC
864 * This is called, when a CPU is disabled and before rebooting, so the state of
865 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
866 * leftovers during boot.
868 void clear_local_APIC(void)
873 /* APIC hasn't been mapped yet */
874 if (!x2apic_mode
&& !apic_phys
)
877 maxlvt
= lapic_get_maxlvt();
879 * Masking an LVT entry can trigger a local APIC error
880 * if the vector is zero. Mask LVTERR first to prevent this.
883 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
884 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
887 * Careful: we have to set masks only first to deassert
888 * any level-triggered sources.
890 v
= apic_read(APIC_LVTT
);
891 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
892 v
= apic_read(APIC_LVT0
);
893 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
894 v
= apic_read(APIC_LVT1
);
895 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
897 v
= apic_read(APIC_LVTPC
);
898 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
901 /* lets not touch this if we didn't frob it */
902 #ifdef CONFIG_X86_THERMAL_VECTOR
904 v
= apic_read(APIC_LVTTHMR
);
905 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
908 #ifdef CONFIG_X86_MCE_INTEL
910 v
= apic_read(APIC_LVTCMCI
);
911 if (!(v
& APIC_LVT_MASKED
))
912 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
917 * Clean APIC state for other OSs:
919 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
920 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
921 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
923 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
925 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
927 /* Integrated APIC (!82489DX) ? */
928 if (lapic_is_integrated()) {
930 /* Clear ESR due to Pentium errata 3AP and 11AP */
931 apic_write(APIC_ESR
, 0);
937 * disable_local_APIC - clear and disable the local APIC
939 void disable_local_APIC(void)
943 /* APIC hasn't been mapped yet */
950 * Disable APIC (implies clearing of registers
953 value
= apic_read(APIC_SPIV
);
954 value
&= ~APIC_SPIV_APIC_ENABLED
;
955 apic_write(APIC_SPIV
, value
);
959 * When LAPIC was disabled by the BIOS and enabled by the kernel,
960 * restore the disabled state.
962 if (enabled_via_apicbase
) {
965 rdmsr(MSR_IA32_APICBASE
, l
, h
);
966 l
&= ~MSR_IA32_APICBASE_ENABLE
;
967 wrmsr(MSR_IA32_APICBASE
, l
, h
);
973 * If Linux enabled the LAPIC against the BIOS default disable it down before
974 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
975 * not power-off. Additionally clear all LVT entries before disable_local_APIC
976 * for the case where Linux didn't enable the LAPIC.
978 void lapic_shutdown(void)
985 local_irq_save(flags
);
988 if (!enabled_via_apicbase
)
992 disable_local_APIC();
995 local_irq_restore(flags
);
999 * This is to verify that we're looking at a real local APIC.
1000 * Check these against your board if the CPUs aren't getting
1001 * started for no apparent reason.
1003 int __init
verify_local_APIC(void)
1005 unsigned int reg0
, reg1
;
1008 * The version register is read-only in a real APIC.
1010 reg0
= apic_read(APIC_LVR
);
1011 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1012 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1013 reg1
= apic_read(APIC_LVR
);
1014 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1017 * The two version reads above should print the same
1018 * numbers. If the second one is different, then we
1019 * poke at a non-APIC.
1025 * Check if the version looks reasonably.
1027 reg1
= GET_APIC_VERSION(reg0
);
1028 if (reg1
== 0x00 || reg1
== 0xff)
1030 reg1
= lapic_get_maxlvt();
1031 if (reg1
< 0x02 || reg1
== 0xff)
1035 * The ID register is read/write in a real APIC.
1037 reg0
= apic_read(APIC_ID
);
1038 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1039 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1040 reg1
= apic_read(APIC_ID
);
1041 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1042 apic_write(APIC_ID
, reg0
);
1043 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1047 * The next two are just to see if we have sane values.
1048 * They're only really relevant if we're in Virtual Wire
1049 * compatibility mode, but most boxes are anymore.
1051 reg0
= apic_read(APIC_LVT0
);
1052 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1053 reg1
= apic_read(APIC_LVT1
);
1054 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1060 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1062 void __init
sync_Arb_IDs(void)
1065 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1068 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1074 apic_wait_icr_idle();
1076 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1077 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1078 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1082 * An initial setup of the virtual wire mode.
1084 void __init
init_bsp_APIC(void)
1089 * Don't do the setup now if we have a SMP BIOS as the
1090 * through-I/O-APIC virtual wire mode might be active.
1092 if (smp_found_config
|| !cpu_has_apic
)
1096 * Do not trust the local APIC being empty at bootup.
1103 value
= apic_read(APIC_SPIV
);
1104 value
&= ~APIC_VECTOR_MASK
;
1105 value
|= APIC_SPIV_APIC_ENABLED
;
1107 #ifdef CONFIG_X86_32
1108 /* This bit is reserved on P4/Xeon and should be cleared */
1109 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1110 (boot_cpu_data
.x86
== 15))
1111 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1114 value
|= APIC_SPIV_FOCUS_DISABLED
;
1115 value
|= SPURIOUS_APIC_VECTOR
;
1116 apic_write(APIC_SPIV
, value
);
1119 * Set up the virtual wire mode.
1121 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1122 value
= APIC_DM_NMI
;
1123 if (!lapic_is_integrated()) /* 82489DX */
1124 value
|= APIC_LVT_LEVEL_TRIGGER
;
1125 apic_write(APIC_LVT1
, value
);
1128 static void __cpuinit
lapic_setup_esr(void)
1130 unsigned int oldvalue
, value
, maxlvt
;
1132 if (!lapic_is_integrated()) {
1133 pr_info("No ESR for 82489DX.\n");
1137 if (apic
->disable_esr
) {
1139 * Something untraceable is creating bad interrupts on
1140 * secondary quads ... for the moment, just leave the
1141 * ESR disabled - we can't do anything useful with the
1142 * errors anyway - mbligh
1144 pr_info("Leaving ESR disabled.\n");
1148 maxlvt
= lapic_get_maxlvt();
1149 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1150 apic_write(APIC_ESR
, 0);
1151 oldvalue
= apic_read(APIC_ESR
);
1153 /* enables sending errors */
1154 value
= ERROR_APIC_VECTOR
;
1155 apic_write(APIC_LVTERR
, value
);
1158 * spec says clear errors after enabling vector.
1161 apic_write(APIC_ESR
, 0);
1162 value
= apic_read(APIC_ESR
);
1163 if (value
!= oldvalue
)
1164 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1165 "vector: 0x%08x after: 0x%08x\n",
1171 * setup_local_APIC - setup the local APIC
1173 void __cpuinit
setup_local_APIC(void)
1179 arch_disable_smp_support();
1183 #ifdef CONFIG_X86_32
1184 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1185 if (lapic_is_integrated() && apic
->disable_esr
) {
1186 apic_write(APIC_ESR
, 0);
1187 apic_write(APIC_ESR
, 0);
1188 apic_write(APIC_ESR
, 0);
1189 apic_write(APIC_ESR
, 0);
1192 perf_counters_lapic_init();
1197 * Double-check whether this APIC is really registered.
1198 * This is meaningless in clustered apic mode, so we skip it.
1200 if (!apic
->apic_id_registered())
1204 * Intel recommends to set DFR, LDR and TPR before enabling
1205 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1206 * document number 292116). So here it goes...
1208 apic
->init_apic_ldr();
1211 * Set Task Priority to 'accept all'. We never change this
1214 value
= apic_read(APIC_TASKPRI
);
1215 value
&= ~APIC_TPRI_MASK
;
1216 apic_write(APIC_TASKPRI
, value
);
1219 * After a crash, we no longer service the interrupts and a pending
1220 * interrupt from previous kernel might still have ISR bit set.
1222 * Most probably by now CPU has serviced that pending interrupt and
1223 * it might not have done the ack_APIC_irq() because it thought,
1224 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1225 * does not clear the ISR bit and cpu thinks it has already serivced
1226 * the interrupt. Hence a vector might get locked. It was noticed
1227 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1229 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1230 value
= apic_read(APIC_ISR
+ i
*0x10);
1231 for (j
= 31; j
>= 0; j
--) {
1238 * Now that we are all set up, enable the APIC
1240 value
= apic_read(APIC_SPIV
);
1241 value
&= ~APIC_VECTOR_MASK
;
1245 value
|= APIC_SPIV_APIC_ENABLED
;
1247 #ifdef CONFIG_X86_32
1249 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1250 * certain networking cards. If high frequency interrupts are
1251 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1252 * entry is masked/unmasked at a high rate as well then sooner or
1253 * later IOAPIC line gets 'stuck', no more interrupts are received
1254 * from the device. If focus CPU is disabled then the hang goes
1257 * [ This bug can be reproduced easily with a level-triggered
1258 * PCI Ne2000 networking cards and PII/PIII processors, dual
1262 * Actually disabling the focus CPU check just makes the hang less
1263 * frequent as it makes the interrupt distributon model be more
1264 * like LRU than MRU (the short-term load is more even across CPUs).
1265 * See also the comment in end_level_ioapic_irq(). --macro
1269 * - enable focus processor (bit==0)
1270 * - 64bit mode always use processor focus
1271 * so no need to set it
1273 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1277 * Set spurious IRQ vector
1279 value
|= SPURIOUS_APIC_VECTOR
;
1280 apic_write(APIC_SPIV
, value
);
1283 * Set up LVT0, LVT1:
1285 * set up through-local-APIC on the BP's LINT0. This is not
1286 * strictly necessary in pure symmetric-IO mode, but sometimes
1287 * we delegate interrupts to the 8259A.
1290 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1292 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1293 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1294 value
= APIC_DM_EXTINT
;
1295 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1296 smp_processor_id());
1298 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1299 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1300 smp_processor_id());
1302 apic_write(APIC_LVT0
, value
);
1305 * only the BP should see the LINT1 NMI signal, obviously.
1307 if (!smp_processor_id())
1308 value
= APIC_DM_NMI
;
1310 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1311 if (!lapic_is_integrated()) /* 82489DX */
1312 value
|= APIC_LVT_LEVEL_TRIGGER
;
1313 apic_write(APIC_LVT1
, value
);
1317 #ifdef CONFIG_X86_MCE_INTEL
1318 /* Recheck CMCI information after local APIC is up on CPU #0 */
1319 if (smp_processor_id() == 0)
1324 void __cpuinit
end_local_APIC_setup(void)
1328 #ifdef CONFIG_X86_32
1331 /* Disable the local apic timer */
1332 value
= apic_read(APIC_LVTT
);
1333 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1334 apic_write(APIC_LVTT
, value
);
1338 setup_apic_nmi_watchdog(NULL
);
1342 #ifdef CONFIG_X86_X2APIC
1343 void check_x2apic(void)
1345 if (x2apic_enabled()) {
1346 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1347 x2apic_preenabled
= x2apic_mode
= 1;
1351 void enable_x2apic(void)
1358 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1359 if (!(msr
& X2APIC_ENABLE
)) {
1360 pr_info("Enabling x2apic\n");
1361 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1364 #endif /* CONFIG_X86_X2APIC */
1366 int __init
enable_IR(void)
1368 #ifdef CONFIG_INTR_REMAP
1369 if (!intr_remapping_supported()) {
1370 pr_debug("intr-remapping not supported\n");
1374 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1375 pr_info("Skipped enabling intr-remap because of skipping "
1380 if (enable_intr_remapping(x2apic_supported()))
1383 pr_info("Enabled Interrupt-remapping\n");
1391 void __init
enable_IR_x2apic(void)
1393 unsigned long flags
;
1394 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1395 int ret
, x2apic_enabled
= 0;
1396 int dmar_table_init_ret
= 0;
1398 #ifdef CONFIG_INTR_REMAP
1399 dmar_table_init_ret
= dmar_table_init();
1400 if (dmar_table_init_ret
)
1401 pr_debug("dmar_table_init() failed with %d:\n",
1402 dmar_table_init_ret
);
1405 ioapic_entries
= alloc_ioapic_entries();
1406 if (!ioapic_entries
) {
1407 pr_err("Allocate ioapic_entries failed\n");
1411 ret
= save_IO_APIC_setup(ioapic_entries
);
1413 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1417 local_irq_save(flags
);
1419 mask_IO_APIC_setup(ioapic_entries
);
1421 if (dmar_table_init_ret
)
1427 /* IR is required if there is APIC ID > 255 even when running
1430 if (max_physical_apicid
> 255 || !kvm_para_available())
1433 * without IR all CPUs can be addressed by IOAPIC/MSI
1434 * only in physical mode
1436 x2apic_force_phys();
1441 if (x2apic_supported() && !x2apic_mode
) {
1444 pr_info("Enabled x2apic\n");
1448 if (!ret
) /* IR enabling failed */
1449 restore_IO_APIC_setup(ioapic_entries
);
1451 local_irq_restore(flags
);
1455 free_ioapic_entries(ioapic_entries
);
1460 if (x2apic_preenabled
)
1461 panic("x2apic: enabled by BIOS but kernel init failed.");
1462 else if (cpu_has_x2apic
)
1463 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1466 #ifdef CONFIG_X86_64
1468 * Detect and enable local APICs on non-SMP boards.
1469 * Original code written by Keir Fraser.
1470 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1471 * not correctly set up (usually the APIC timer won't work etc.)
1473 static int __init
detect_init_APIC(void)
1475 if (!cpu_has_apic
) {
1476 pr_info("No local APIC present\n");
1480 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1485 * Detect and initialize APIC
1487 static int __init
detect_init_APIC(void)
1491 /* Disabled by kernel option? */
1495 switch (boot_cpu_data
.x86_vendor
) {
1496 case X86_VENDOR_AMD
:
1497 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1498 (boot_cpu_data
.x86
>= 15))
1501 case X86_VENDOR_INTEL
:
1502 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1503 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1510 if (!cpu_has_apic
) {
1512 * Over-ride BIOS and try to enable the local APIC only if
1513 * "lapic" specified.
1515 if (!force_enable_local_apic
) {
1516 pr_info("Local APIC disabled by BIOS -- "
1517 "you can enable it with \"lapic\"\n");
1521 * Some BIOSes disable the local APIC in the APIC_BASE
1522 * MSR. This can only be done in software for Intel P6 or later
1523 * and AMD K7 (Model > 1) or later.
1525 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1526 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1527 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1528 l
&= ~MSR_IA32_APICBASE_BASE
;
1529 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1530 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1531 enabled_via_apicbase
= 1;
1535 * The APIC feature bit should now be enabled
1538 features
= cpuid_edx(1);
1539 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1540 pr_warning("Could not enable APIC!\n");
1543 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1544 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1546 /* The BIOS may have set up the APIC at some other address */
1547 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1548 if (l
& MSR_IA32_APICBASE_ENABLE
)
1549 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1551 pr_info("Found and enabled local APIC!\n");
1558 pr_info("No local APIC present or hardware disabled\n");
1563 #ifdef CONFIG_X86_64
1564 void __init
early_init_lapic_mapping(void)
1567 * If no local APIC can be found then go out
1568 * : it means there is no mpatable and MADT
1570 if (!smp_found_config
)
1573 set_fixmap_nocache(FIX_APIC_BASE
, mp_lapic_addr
);
1574 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1575 APIC_BASE
, mp_lapic_addr
);
1578 * Fetch the APIC ID of the BSP in case we have a
1579 * default configuration (or the MP table is broken).
1581 boot_cpu_physical_apicid
= read_apic_id();
1586 * init_apic_mappings - initialize APIC mappings
1588 void __init
init_apic_mappings(void)
1590 unsigned int new_apicid
;
1593 boot_cpu_physical_apicid
= read_apic_id();
1597 /* If no local APIC can be found return early */
1598 if (!smp_found_config
&& detect_init_APIC()) {
1599 /* lets NOP'ify apic operations */
1600 pr_info("APIC: disable apic facility\n");
1603 apic_phys
= mp_lapic_addr
;
1606 * acpi lapic path already maps that address in
1607 * acpi_register_lapic_address()
1610 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1612 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1613 APIC_BASE
, apic_phys
);
1617 * Fetch the APIC ID of the BSP in case we have a
1618 * default configuration (or the MP table is broken).
1620 new_apicid
= read_apic_id();
1621 if (boot_cpu_physical_apicid
!= new_apicid
) {
1622 boot_cpu_physical_apicid
= new_apicid
;
1624 * yeah -- we lie about apic_version
1625 * in case if apic was disabled via boot option
1626 * but it's not a problem for SMP compiled kernel
1627 * since smp_sanity_check is prepared for such a case
1628 * and disable smp mode
1630 apic_version
[new_apicid
] =
1631 GET_APIC_VERSION(apic_read(APIC_LVR
));
1636 * This initializes the IO-APIC and APIC hardware if this is
1639 int apic_version
[MAX_APICS
];
1641 int __init
APIC_init_uniprocessor(void)
1644 pr_info("Apic disabled\n");
1647 #ifdef CONFIG_X86_64
1648 if (!cpu_has_apic
) {
1650 pr_info("Apic disabled by BIOS\n");
1654 if (!smp_found_config
&& !cpu_has_apic
)
1658 * Complain if the BIOS pretends there is one.
1660 if (!cpu_has_apic
&&
1661 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1662 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1663 boot_cpu_physical_apicid
);
1669 #ifdef CONFIG_X86_64
1670 default_setup_apic_routing();
1673 verify_local_APIC();
1676 #ifdef CONFIG_X86_64
1677 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1680 * Hack: In case of kdump, after a crash, kernel might be booting
1681 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1682 * might be zero if read from MP tables. Get it from LAPIC.
1684 # ifdef CONFIG_CRASH_DUMP
1685 boot_cpu_physical_apicid
= read_apic_id();
1688 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1691 #ifdef CONFIG_X86_IO_APIC
1693 * Now enable IO-APICs, actually call clear_IO_APIC
1694 * We need clear_IO_APIC before enabling error vector
1696 if (!skip_ioapic_setup
&& nr_ioapics
)
1700 end_local_APIC_setup();
1702 #ifdef CONFIG_X86_IO_APIC
1703 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1707 localise_nmi_watchdog();
1710 localise_nmi_watchdog();
1713 x86_init
.timers
.setup_percpu_clockev();
1714 #ifdef CONFIG_X86_64
1715 check_nmi_watchdog();
1722 * Local APIC interrupts
1726 * This interrupt should _never_ happen with our APIC/SMP architecture
1728 void smp_spurious_interrupt(struct pt_regs
*regs
)
1735 * Check if this really is a spurious interrupt and ACK it
1736 * if it is a vectored one. Just in case...
1737 * Spurious interrupts should not be ACKed.
1739 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1740 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1743 inc_irq_stat(irq_spurious_count
);
1745 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1746 pr_info("spurious APIC interrupt on CPU#%d, "
1747 "should never happen.\n", smp_processor_id());
1752 * This interrupt should never happen with our APIC/SMP architecture
1754 void smp_error_interrupt(struct pt_regs
*regs
)
1760 /* First tickle the hardware, only then report what went on. -- REW */
1761 v
= apic_read(APIC_ESR
);
1762 apic_write(APIC_ESR
, 0);
1763 v1
= apic_read(APIC_ESR
);
1765 atomic_inc(&irq_err_count
);
1768 * Here is what the APIC error bits mean:
1770 * 1: Receive CS error
1771 * 2: Send accept error
1772 * 3: Receive accept error
1774 * 5: Send illegal vector
1775 * 6: Received illegal vector
1776 * 7: Illegal register address
1778 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1779 smp_processor_id(), v
, v1
);
1784 * connect_bsp_APIC - attach the APIC to the interrupt system
1786 void __init
connect_bsp_APIC(void)
1788 #ifdef CONFIG_X86_32
1791 * Do not trust the local APIC being empty at bootup.
1795 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1796 * local APIC to INT and NMI lines.
1798 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1799 "enabling APIC mode.\n");
1803 if (apic
->enable_apic_mode
)
1804 apic
->enable_apic_mode();
1808 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1809 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1811 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1814 void disconnect_bsp_APIC(int virt_wire_setup
)
1818 #ifdef CONFIG_X86_32
1821 * Put the board back into PIC mode (has an effect only on
1822 * certain older boards). Note that APIC interrupts, including
1823 * IPIs, won't work beyond this point! The only exception are
1826 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1827 "entering PIC mode.\n");
1833 /* Go back to Virtual Wire compatibility mode */
1835 /* For the spurious interrupt use vector F, and enable it */
1836 value
= apic_read(APIC_SPIV
);
1837 value
&= ~APIC_VECTOR_MASK
;
1838 value
|= APIC_SPIV_APIC_ENABLED
;
1840 apic_write(APIC_SPIV
, value
);
1842 if (!virt_wire_setup
) {
1844 * For LVT0 make it edge triggered, active high,
1845 * external and enabled
1847 value
= apic_read(APIC_LVT0
);
1848 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1849 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1850 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1851 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1852 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1853 apic_write(APIC_LVT0
, value
);
1856 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1860 * For LVT1 make it edge triggered, active high,
1863 value
= apic_read(APIC_LVT1
);
1864 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1865 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1866 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1867 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1868 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1869 apic_write(APIC_LVT1
, value
);
1872 void __cpuinit
generic_processor_info(int apicid
, int version
)
1879 if (version
== 0x0) {
1880 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1881 "fixing up to 0x10. (tell your hw vendor)\n",
1885 apic_version
[apicid
] = version
;
1887 if (num_processors
>= nr_cpu_ids
) {
1888 int max
= nr_cpu_ids
;
1889 int thiscpu
= max
+ disabled_cpus
;
1892 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1893 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1900 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1902 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1904 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1905 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1907 physid_set(apicid
, phys_cpu_present_map
);
1908 if (apicid
== boot_cpu_physical_apicid
) {
1910 * x86_bios_cpu_apicid is required to have processors listed
1911 * in same order as logical cpu numbers. Hence the first
1912 * entry is BSP, and so on.
1916 if (apicid
> max_physical_apicid
)
1917 max_physical_apicid
= apicid
;
1919 #ifdef CONFIG_X86_32
1921 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1922 * but we need to work other dependencies like SMP_SUSPEND etc
1923 * before this can be done without some confusion.
1924 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1925 * - Ashok Raj <ashok.raj@intel.com>
1927 if (max_physical_apicid
>= 8) {
1928 switch (boot_cpu_data
.x86_vendor
) {
1929 case X86_VENDOR_INTEL
:
1930 if (!APIC_XAPIC(version
)) {
1934 /* If P4 and above fall through */
1935 case X86_VENDOR_AMD
:
1941 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1942 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1943 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1946 set_cpu_possible(cpu
, true);
1947 set_cpu_present(cpu
, true);
1950 int hard_smp_processor_id(void)
1952 return read_apic_id();
1955 void default_init_apic_ldr(void)
1959 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1960 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1961 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1962 apic_write(APIC_LDR
, val
);
1965 #ifdef CONFIG_X86_32
1966 int default_apicid_to_node(int logical_apicid
)
1969 return apicid_2_node
[hard_smp_processor_id()];
1983 * 'active' is true if the local APIC was enabled by us and
1984 * not the BIOS; this signifies that we are also responsible
1985 * for disabling it before entering apm/acpi suspend
1988 /* r/w apic fields */
1989 unsigned int apic_id
;
1990 unsigned int apic_taskpri
;
1991 unsigned int apic_ldr
;
1992 unsigned int apic_dfr
;
1993 unsigned int apic_spiv
;
1994 unsigned int apic_lvtt
;
1995 unsigned int apic_lvtpc
;
1996 unsigned int apic_lvt0
;
1997 unsigned int apic_lvt1
;
1998 unsigned int apic_lvterr
;
1999 unsigned int apic_tmict
;
2000 unsigned int apic_tdcr
;
2001 unsigned int apic_thmr
;
2004 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2006 unsigned long flags
;
2009 if (!apic_pm_state
.active
)
2012 maxlvt
= lapic_get_maxlvt();
2014 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2015 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2016 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2017 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2018 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2019 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2021 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2022 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2023 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2024 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2025 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2026 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2027 #ifdef CONFIG_X86_THERMAL_VECTOR
2029 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2032 local_irq_save(flags
);
2033 disable_local_APIC();
2035 if (intr_remapping_enabled
)
2036 disable_intr_remapping();
2038 local_irq_restore(flags
);
2042 static int lapic_resume(struct sys_device
*dev
)
2045 unsigned long flags
;
2048 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2050 if (!apic_pm_state
.active
)
2053 local_irq_save(flags
);
2054 if (intr_remapping_enabled
) {
2055 ioapic_entries
= alloc_ioapic_entries();
2056 if (!ioapic_entries
) {
2057 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2062 ret
= save_IO_APIC_setup(ioapic_entries
);
2064 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2065 free_ioapic_entries(ioapic_entries
);
2069 mask_IO_APIC_setup(ioapic_entries
);
2077 * Make sure the APICBASE points to the right address
2079 * FIXME! This will be wrong if we ever support suspend on
2080 * SMP! We'll need to do this as part of the CPU restore!
2082 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2083 l
&= ~MSR_IA32_APICBASE_BASE
;
2084 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2085 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2088 maxlvt
= lapic_get_maxlvt();
2089 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2090 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2091 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2092 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2093 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2094 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2095 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2096 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2097 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2099 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2102 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2103 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2104 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2105 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2106 apic_write(APIC_ESR
, 0);
2107 apic_read(APIC_ESR
);
2108 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2109 apic_write(APIC_ESR
, 0);
2110 apic_read(APIC_ESR
);
2112 if (intr_remapping_enabled
) {
2113 reenable_intr_remapping(x2apic_mode
);
2115 restore_IO_APIC_setup(ioapic_entries
);
2116 free_ioapic_entries(ioapic_entries
);
2119 local_irq_restore(flags
);
2125 * This device has no shutdown method - fully functioning local APICs
2126 * are needed on every CPU up until machine_halt/restart/poweroff.
2129 static struct sysdev_class lapic_sysclass
= {
2131 .resume
= lapic_resume
,
2132 .suspend
= lapic_suspend
,
2135 static struct sys_device device_lapic
= {
2137 .cls
= &lapic_sysclass
,
2140 static void __cpuinit
apic_pm_activate(void)
2142 apic_pm_state
.active
= 1;
2145 static int __init
init_lapic_sysfs(void)
2151 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2153 error
= sysdev_class_register(&lapic_sysclass
);
2155 error
= sysdev_register(&device_lapic
);
2159 /* local apic needs to resume before other devices access its registers. */
2160 core_initcall(init_lapic_sysfs
);
2162 #else /* CONFIG_PM */
2164 static void apic_pm_activate(void) { }
2166 #endif /* CONFIG_PM */
2168 #ifdef CONFIG_X86_64
2170 static int __cpuinit
apic_cluster_num(void)
2172 int i
, clusters
, zeros
;
2174 u16
*bios_cpu_apicid
;
2175 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2177 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2178 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2180 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2181 /* are we being called early in kernel startup? */
2182 if (bios_cpu_apicid
) {
2183 id
= bios_cpu_apicid
[i
];
2184 } else if (i
< nr_cpu_ids
) {
2186 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2192 if (id
!= BAD_APICID
)
2193 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2196 /* Problem: Partially populated chassis may not have CPUs in some of
2197 * the APIC clusters they have been allocated. Only present CPUs have
2198 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2199 * Since clusters are allocated sequentially, count zeros only if
2200 * they are bounded by ones.
2204 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2205 if (test_bit(i
, clustermap
)) {
2206 clusters
+= 1 + zeros
;
2215 static int __cpuinitdata multi_checked
;
2216 static int __cpuinitdata multi
;
2218 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2222 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2227 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2229 .callback
= set_multi
,
2230 .ident
= "IBM System Summit2",
2232 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2233 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2239 static void __cpuinit
dmi_check_multi(void)
2244 dmi_check_system(multi_dmi_table
);
2249 * apic_is_clustered_box() -- Check if we can expect good TSC
2251 * Thus far, the major user of this is IBM's Summit2 series:
2252 * Clustered boxes may have unsynced TSC problems if they are
2254 * Use DMI to check them
2256 __cpuinit
int apic_is_clustered_box(void)
2266 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2267 * not guaranteed to be synced between boards
2269 if (apic_cluster_num() > 1)
2277 * APIC command line parameters
2279 static int __init
setup_disableapic(char *arg
)
2282 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2285 early_param("disableapic", setup_disableapic
);
2287 /* same as disableapic, for compatibility */
2288 static int __init
setup_nolapic(char *arg
)
2290 return setup_disableapic(arg
);
2292 early_param("nolapic", setup_nolapic
);
2294 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2296 local_apic_timer_c2_ok
= 1;
2299 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2301 static int __init
parse_disable_apic_timer(char *arg
)
2303 disable_apic_timer
= 1;
2306 early_param("noapictimer", parse_disable_apic_timer
);
2308 static int __init
parse_nolapic_timer(char *arg
)
2310 disable_apic_timer
= 1;
2313 early_param("nolapic_timer", parse_nolapic_timer
);
2315 static int __init
apic_set_verbosity(char *arg
)
2318 #ifdef CONFIG_X86_64
2319 skip_ioapic_setup
= 0;
2325 if (strcmp("debug", arg
) == 0)
2326 apic_verbosity
= APIC_DEBUG
;
2327 else if (strcmp("verbose", arg
) == 0)
2328 apic_verbosity
= APIC_VERBOSE
;
2330 pr_warning("APIC Verbosity level %s not recognised"
2331 " use apic=verbose or apic=debug\n", arg
);
2337 early_param("apic", apic_set_verbosity
);
2339 static int __init
lapic_insert_resource(void)
2344 /* Put local APIC into the resource map. */
2345 lapic_resource
.start
= apic_phys
;
2346 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2347 insert_resource(&iomem_resource
, &lapic_resource
);
2353 * need call insert after e820_reserve_resources()
2354 * that is using request_resource
2356 late_initcall(lapic_insert_resource
);