2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug
= -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
78 static DEFINE_RAW_SPINLOCK(vector_lock
);
81 * # of IRQ routing registers
83 int nr_ioapic_registers
[MAX_IO_APICS
];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing
[MAX_IO_APICS
];
92 /* MP IRQ source entries */
93 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
95 /* # of MP IRQ source entries */
99 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
101 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
102 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
105 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
107 int skip_ioapic_setup
;
109 void arch_disable_smp_support(void)
113 noioapicreroute
= -1;
115 skip_ioapic_setup
= 1;
118 static int __init
parse_noapic(char *str
)
120 /* disable IO-APIC */
121 arch_disable_smp_support();
124 early_param("noapic", parse_noapic
);
126 struct irq_pin_list
{
128 struct irq_pin_list
*next
;
131 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
133 struct irq_pin_list
*pin
;
135 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
140 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
141 #ifdef CONFIG_SPARSE_IRQ
142 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
144 static struct irq_cfg irq_cfgx
[NR_IRQS
];
147 int __init
arch_early_irq_init(void)
150 struct irq_desc
*desc
;
155 if (!legacy_pic
->nr_legacy_irqs
) {
161 count
= ARRAY_SIZE(irq_cfgx
);
162 node
= cpu_to_node(boot_cpu_id
);
164 for (i
= 0; i
< count
; i
++) {
165 desc
= irq_to_desc(i
);
166 desc
->chip_data
= &cfg
[i
];
167 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
168 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
170 * For legacy IRQ's, start with assigning irq0 to irq15 to
171 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
173 if (i
< legacy_pic
->nr_legacy_irqs
) {
174 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
175 cpumask_set_cpu(0, cfg
[i
].domain
);
182 #ifdef CONFIG_SPARSE_IRQ
183 struct irq_cfg
*irq_cfg(unsigned int irq
)
185 struct irq_cfg
*cfg
= NULL
;
186 struct irq_desc
*desc
;
188 desc
= irq_to_desc(irq
);
190 cfg
= desc
->chip_data
;
195 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
199 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
201 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
204 } else if (!zalloc_cpumask_var_node(&cfg
->old_domain
,
206 free_cpumask_var(cfg
->domain
);
215 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
219 cfg
= desc
->chip_data
;
221 desc
->chip_data
= get_one_free_irq_cfg(node
);
222 if (!desc
->chip_data
) {
223 printk(KERN_ERR
"can not alloc irq_cfg\n");
231 /* for move_irq_desc */
233 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
235 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
237 cfg
->irq_2_pin
= NULL
;
238 old_entry
= old_cfg
->irq_2_pin
;
242 entry
= get_one_free_irq_2_pin(node
);
246 entry
->apic
= old_entry
->apic
;
247 entry
->pin
= old_entry
->pin
;
250 old_entry
= old_entry
->next
;
252 entry
= get_one_free_irq_2_pin(node
);
260 /* still use the old one */
263 entry
->apic
= old_entry
->apic
;
264 entry
->pin
= old_entry
->pin
;
267 old_entry
= old_entry
->next
;
271 cfg
->irq_2_pin
= head
;
274 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
276 struct irq_pin_list
*entry
, *next
;
278 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
281 entry
= old_cfg
->irq_2_pin
;
288 old_cfg
->irq_2_pin
= NULL
;
291 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
292 struct irq_desc
*desc
, int node
)
295 struct irq_cfg
*old_cfg
;
297 cfg
= get_one_free_irq_cfg(node
);
302 desc
->chip_data
= cfg
;
304 old_cfg
= old_desc
->chip_data
;
306 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
308 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
311 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
316 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
318 struct irq_cfg
*old_cfg
, *cfg
;
320 old_cfg
= old_desc
->chip_data
;
321 cfg
= desc
->chip_data
;
327 free_irq_2_pin(old_cfg
, cfg
);
328 free_irq_cfg(old_cfg
);
329 old_desc
->chip_data
= NULL
;
332 /* end for move_irq_desc */
335 struct irq_cfg
*irq_cfg(unsigned int irq
)
337 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
344 unsigned int unused
[3];
346 unsigned int unused2
[11];
350 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
352 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
353 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
356 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
358 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
359 writel(vector
, &io_apic
->eoi
);
362 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
364 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
365 writel(reg
, &io_apic
->index
);
366 return readl(&io_apic
->data
);
369 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
371 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
372 writel(reg
, &io_apic
->index
);
373 writel(value
, &io_apic
->data
);
377 * Re-write a value: to be used for read-modify-write
378 * cycles where the read already set up the index register.
380 * Older SiS APIC requires we rewrite the index register
382 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
384 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
387 writel(reg
, &io_apic
->index
);
388 writel(value
, &io_apic
->data
);
391 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
393 struct irq_pin_list
*entry
;
396 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
397 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
402 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
403 /* Is the remote IRR bit set? */
404 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
405 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
409 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
415 struct { u32 w1
, w2
; };
416 struct IO_APIC_route_entry entry
;
419 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
421 union entry_union eu
;
423 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
424 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
425 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
426 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
431 * When we write a new IO APIC routing entry, we need to write the high
432 * word first! If the mask bit in the low word is clear, we will enable
433 * the interrupt, and we need to make sure the entry is fully populated
434 * before that happens.
437 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
439 union entry_union eu
= {{0, 0}};
442 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
443 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
446 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
449 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
450 __ioapic_write_entry(apic
, pin
, e
);
451 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
455 * When we mask an IO APIC routing entry, we need to write the low
456 * word first, in order to set the mask bit before we change the
459 static void ioapic_mask_entry(int apic
, int pin
)
462 union entry_union eu
= { .entry
.mask
= 1 };
464 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
465 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
466 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
467 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
471 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
472 * shared ISA-space IRQs, so we have to support them. We are super
473 * fast in the common case, and fast for shared ISA-space IRQs.
476 add_pin_to_irq_node_nopanic(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
478 struct irq_pin_list
**last
, *entry
;
480 /* don't allow duplicates */
481 last
= &cfg
->irq_2_pin
;
482 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
483 if (entry
->apic
== apic
&& entry
->pin
== pin
)
488 entry
= get_one_free_irq_2_pin(node
);
490 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
501 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
503 if (add_pin_to_irq_node_nopanic(cfg
, node
, apic
, pin
))
504 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
508 * Reroute an IRQ to a different pin.
510 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
511 int oldapic
, int oldpin
,
512 int newapic
, int newpin
)
514 struct irq_pin_list
*entry
;
516 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
517 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
518 entry
->apic
= newapic
;
520 /* every one is different, right? */
525 /* old apic/pin didn't exist, so just add new ones */
526 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
529 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
530 int mask_and
, int mask_or
,
531 void (*final
)(struct irq_pin_list
*entry
))
533 unsigned int reg
, pin
;
536 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
539 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
544 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
545 int mask_and
, int mask_or
,
546 void (*final
)(struct irq_pin_list
*entry
))
548 struct irq_pin_list
*entry
;
550 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
551 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
554 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
556 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
557 IO_APIC_REDIR_MASKED
, NULL
);
560 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
562 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
563 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
566 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
568 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
571 static void io_apic_sync(struct irq_pin_list
*entry
)
574 * Synchronize the IO-APIC and the CPU by doing
575 * a dummy read from the IO-APIC
577 struct io_apic __iomem
*io_apic
;
578 io_apic
= io_apic_base(entry
->apic
);
579 readl(&io_apic
->data
);
582 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
584 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
587 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
589 struct irq_cfg
*cfg
= desc
->chip_data
;
594 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
595 __mask_IO_APIC_irq(cfg
);
596 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
599 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
601 struct irq_cfg
*cfg
= desc
->chip_data
;
604 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
605 __unmask_IO_APIC_irq(cfg
);
606 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
609 static void mask_IO_APIC_irq(unsigned int irq
)
611 struct irq_desc
*desc
= irq_to_desc(irq
);
613 mask_IO_APIC_irq_desc(desc
);
615 static void unmask_IO_APIC_irq(unsigned int irq
)
617 struct irq_desc
*desc
= irq_to_desc(irq
);
619 unmask_IO_APIC_irq_desc(desc
);
622 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
624 struct IO_APIC_route_entry entry
;
626 /* Check delivery_mode to be sure we're not clearing an SMI pin */
627 entry
= ioapic_read_entry(apic
, pin
);
628 if (entry
.delivery_mode
== dest_SMI
)
631 * Disable it in the IO-APIC irq-routing table:
633 ioapic_mask_entry(apic
, pin
);
636 static void clear_IO_APIC (void)
640 for (apic
= 0; apic
< nr_ioapics
; apic
++)
641 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
642 clear_IO_APIC_pin(apic
, pin
);
647 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
648 * specific CPU-side IRQs.
652 static int pirq_entries
[MAX_PIRQS
] = {
653 [0 ... MAX_PIRQS
- 1] = -1
656 static int __init
ioapic_pirq_setup(char *str
)
659 int ints
[MAX_PIRQS
+1];
661 get_options(str
, ARRAY_SIZE(ints
), ints
);
663 apic_printk(APIC_VERBOSE
, KERN_INFO
664 "PIRQ redirection, working around broken MP-BIOS.\n");
666 if (ints
[0] < MAX_PIRQS
)
669 for (i
= 0; i
< max
; i
++) {
670 apic_printk(APIC_VERBOSE
, KERN_DEBUG
671 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
673 * PIRQs are mapped upside down, usually.
675 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
680 __setup("pirq=", ioapic_pirq_setup
);
681 #endif /* CONFIG_X86_32 */
683 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
686 struct IO_APIC_route_entry
**ioapic_entries
;
688 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
693 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
694 ioapic_entries
[apic
] =
695 kzalloc(sizeof(struct IO_APIC_route_entry
) *
696 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
697 if (!ioapic_entries
[apic
])
701 return ioapic_entries
;
705 kfree(ioapic_entries
[apic
]);
706 kfree(ioapic_entries
);
712 * Saves all the IO-APIC RTE's
714 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
721 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
722 if (!ioapic_entries
[apic
])
725 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
726 ioapic_entries
[apic
][pin
] =
727 ioapic_read_entry(apic
, pin
);
734 * Mask all IO APIC entries.
736 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
743 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
744 if (!ioapic_entries
[apic
])
747 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
748 struct IO_APIC_route_entry entry
;
750 entry
= ioapic_entries
[apic
][pin
];
753 ioapic_write_entry(apic
, pin
, entry
);
760 * Restore IO APIC entries which was saved in ioapic_entries.
762 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
769 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
770 if (!ioapic_entries
[apic
])
773 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
774 ioapic_write_entry(apic
, pin
,
775 ioapic_entries
[apic
][pin
]);
780 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
784 for (apic
= 0; apic
< nr_ioapics
; apic
++)
785 kfree(ioapic_entries
[apic
]);
787 kfree(ioapic_entries
);
791 * Find the IRQ entry number of a certain pin.
793 static int find_irq_entry(int apic
, int pin
, int type
)
797 for (i
= 0; i
< mp_irq_entries
; i
++)
798 if (mp_irqs
[i
].irqtype
== type
&&
799 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
800 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
801 mp_irqs
[i
].dstirq
== pin
)
808 * Find the pin to which IRQ[irq] (ISA) is connected
810 static int __init
find_isa_irq_pin(int irq
, int type
)
814 for (i
= 0; i
< mp_irq_entries
; i
++) {
815 int lbus
= mp_irqs
[i
].srcbus
;
817 if (test_bit(lbus
, mp_bus_not_pci
) &&
818 (mp_irqs
[i
].irqtype
== type
) &&
819 (mp_irqs
[i
].srcbusirq
== irq
))
821 return mp_irqs
[i
].dstirq
;
826 static int __init
find_isa_irq_apic(int irq
, int type
)
830 for (i
= 0; i
< mp_irq_entries
; i
++) {
831 int lbus
= mp_irqs
[i
].srcbus
;
833 if (test_bit(lbus
, mp_bus_not_pci
) &&
834 (mp_irqs
[i
].irqtype
== type
) &&
835 (mp_irqs
[i
].srcbusirq
== irq
))
838 if (i
< mp_irq_entries
) {
840 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
841 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
849 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
851 * EISA Edge/Level control register, ELCR
853 static int EISA_ELCR(unsigned int irq
)
855 if (irq
< legacy_pic
->nr_legacy_irqs
) {
856 unsigned int port
= 0x4d0 + (irq
>> 3);
857 return (inb(port
) >> (irq
& 7)) & 1;
859 apic_printk(APIC_VERBOSE
, KERN_INFO
860 "Broken MPtable reports ISA irq %d\n", irq
);
866 /* ISA interrupts are always polarity zero edge triggered,
867 * when listed as conforming in the MP table. */
869 #define default_ISA_trigger(idx) (0)
870 #define default_ISA_polarity(idx) (0)
872 /* EISA interrupts are always polarity zero and can be edge or level
873 * trigger depending on the ELCR value. If an interrupt is listed as
874 * EISA conforming in the MP table, that means its trigger type must
875 * be read in from the ELCR */
877 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
878 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
880 /* PCI interrupts are always polarity one level triggered,
881 * when listed as conforming in the MP table. */
883 #define default_PCI_trigger(idx) (1)
884 #define default_PCI_polarity(idx) (1)
886 /* MCA interrupts are always polarity zero level triggered,
887 * when listed as conforming in the MP table. */
889 #define default_MCA_trigger(idx) (1)
890 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
892 static int MPBIOS_polarity(int idx
)
894 int bus
= mp_irqs
[idx
].srcbus
;
898 * Determine IRQ line polarity (high active or low active):
900 switch (mp_irqs
[idx
].irqflag
& 3)
902 case 0: /* conforms, ie. bus-type dependent polarity */
903 if (test_bit(bus
, mp_bus_not_pci
))
904 polarity
= default_ISA_polarity(idx
);
906 polarity
= default_PCI_polarity(idx
);
908 case 1: /* high active */
913 case 2: /* reserved */
915 printk(KERN_WARNING
"broken BIOS!!\n");
919 case 3: /* low active */
924 default: /* invalid */
926 printk(KERN_WARNING
"broken BIOS!!\n");
934 static int MPBIOS_trigger(int idx
)
936 int bus
= mp_irqs
[idx
].srcbus
;
940 * Determine IRQ trigger mode (edge or level sensitive):
942 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
944 case 0: /* conforms, ie. bus-type dependent */
945 if (test_bit(bus
, mp_bus_not_pci
))
946 trigger
= default_ISA_trigger(idx
);
948 trigger
= default_PCI_trigger(idx
);
949 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
950 switch (mp_bus_id_to_type
[bus
]) {
951 case MP_BUS_ISA
: /* ISA pin */
953 /* set before the switch */
956 case MP_BUS_EISA
: /* EISA pin */
958 trigger
= default_EISA_trigger(idx
);
961 case MP_BUS_PCI
: /* PCI pin */
963 /* set before the switch */
966 case MP_BUS_MCA
: /* MCA pin */
968 trigger
= default_MCA_trigger(idx
);
973 printk(KERN_WARNING
"broken BIOS!!\n");
985 case 2: /* reserved */
987 printk(KERN_WARNING
"broken BIOS!!\n");
996 default: /* invalid */
998 printk(KERN_WARNING
"broken BIOS!!\n");
1006 static inline int irq_polarity(int idx
)
1008 return MPBIOS_polarity(idx
);
1011 static inline int irq_trigger(int idx
)
1013 return MPBIOS_trigger(idx
);
1016 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1017 static int pin_2_irq(int idx
, int apic
, int pin
)
1020 int bus
= mp_irqs
[idx
].srcbus
;
1023 * Debugging check, we are in big trouble if this message pops up!
1025 if (mp_irqs
[idx
].dstirq
!= pin
)
1026 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1028 if (test_bit(bus
, mp_bus_not_pci
)) {
1029 irq
= mp_irqs
[idx
].srcbusirq
;
1032 * PCI IRQs are mapped in order
1036 irq
+= nr_ioapic_registers
[i
++];
1039 * For MPS mode, so far only needed by ES7000 platform
1041 if (ioapic_renumber_irq
)
1042 irq
= ioapic_renumber_irq(apic
, irq
);
1045 #ifdef CONFIG_X86_32
1047 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1049 if ((pin
>= 16) && (pin
<= 23)) {
1050 if (pirq_entries
[pin
-16] != -1) {
1051 if (!pirq_entries
[pin
-16]) {
1052 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1053 "disabling PIRQ%d\n", pin
-16);
1055 irq
= pirq_entries
[pin
-16];
1056 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1057 "using PIRQ%d -> IRQ %d\n",
1068 * Find a specific PCI IRQ entry.
1069 * Not an __init, possibly needed by modules
1071 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1072 struct io_apic_irq_attr
*irq_attr
)
1074 int apic
, i
, best_guess
= -1;
1076 apic_printk(APIC_DEBUG
,
1077 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1079 if (test_bit(bus
, mp_bus_not_pci
)) {
1080 apic_printk(APIC_VERBOSE
,
1081 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1084 for (i
= 0; i
< mp_irq_entries
; i
++) {
1085 int lbus
= mp_irqs
[i
].srcbus
;
1087 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1088 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1089 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1092 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1093 !mp_irqs
[i
].irqtype
&&
1095 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1096 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1098 if (!(apic
|| IO_APIC_IRQ(irq
)))
1101 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1102 set_io_apic_irq_attr(irq_attr
, apic
,
1109 * Use the first all-but-pin matching entry as a
1110 * best-guess fuzzy result for broken mptables.
1112 if (best_guess
< 0) {
1113 set_io_apic_irq_attr(irq_attr
, apic
,
1123 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1125 void lock_vector_lock(void)
1127 /* Used to the online set of cpus does not change
1128 * during assign_irq_vector.
1130 raw_spin_lock(&vector_lock
);
1133 void unlock_vector_lock(void)
1135 raw_spin_unlock(&vector_lock
);
1139 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1142 * NOTE! The local APIC isn't very good at handling
1143 * multiple interrupts at the same interrupt level.
1144 * As the interrupt level is determined by taking the
1145 * vector number and shifting that right by 4, we
1146 * want to spread these out a bit so that they don't
1147 * all fall in the same interrupt level.
1149 * Also, we've got to be careful not to trash gate
1150 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1152 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1153 static int current_offset
= VECTOR_OFFSET_START
% 8;
1154 unsigned int old_vector
;
1156 cpumask_var_t tmp_mask
;
1158 if (cfg
->move_in_progress
)
1161 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1164 old_vector
= cfg
->vector
;
1166 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1167 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1168 if (!cpumask_empty(tmp_mask
)) {
1169 free_cpumask_var(tmp_mask
);
1174 /* Only try and allocate irqs on cpus that are present */
1176 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1180 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1182 vector
= current_vector
;
1183 offset
= current_offset
;
1186 if (vector
>= first_system_vector
) {
1187 /* If out of vectors on large boxen, must share them. */
1188 offset
= (offset
+ 1) % 8;
1189 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1191 if (unlikely(current_vector
== vector
))
1194 if (test_bit(vector
, used_vectors
))
1197 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1198 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1201 current_vector
= vector
;
1202 current_offset
= offset
;
1204 cfg
->move_in_progress
= 1;
1205 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1207 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1208 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1209 cfg
->vector
= vector
;
1210 cpumask_copy(cfg
->domain
, tmp_mask
);
1214 free_cpumask_var(tmp_mask
);
1218 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1221 unsigned long flags
;
1223 raw_spin_lock_irqsave(&vector_lock
, flags
);
1224 err
= __assign_irq_vector(irq
, cfg
, mask
);
1225 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1229 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1233 BUG_ON(!cfg
->vector
);
1235 vector
= cfg
->vector
;
1236 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1237 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1240 cpumask_clear(cfg
->domain
);
1242 if (likely(!cfg
->move_in_progress
))
1244 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1245 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1247 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1249 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1253 cfg
->move_in_progress
= 0;
1256 void __setup_vector_irq(int cpu
)
1258 /* Initialize vector_irq on a new cpu */
1260 struct irq_cfg
*cfg
;
1261 struct irq_desc
*desc
;
1264 * vector_lock will make sure that we don't run into irq vector
1265 * assignments that might be happening on another cpu in parallel,
1266 * while we setup our initial vector to irq mappings.
1268 raw_spin_lock(&vector_lock
);
1269 /* Mark the inuse vectors */
1270 for_each_irq_desc(irq
, desc
) {
1271 cfg
= desc
->chip_data
;
1274 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1275 * will be part of the irq_cfg's domain.
1277 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1278 cpumask_set_cpu(cpu
, cfg
->domain
);
1280 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1282 vector
= cfg
->vector
;
1283 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1285 /* Mark the free vectors */
1286 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1287 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1292 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1293 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1295 raw_spin_unlock(&vector_lock
);
1298 static struct irq_chip ioapic_chip
;
1299 static struct irq_chip ir_ioapic_chip
;
1301 #define IOAPIC_AUTO -1
1302 #define IOAPIC_EDGE 0
1303 #define IOAPIC_LEVEL 1
1305 #ifdef CONFIG_X86_32
1306 static inline int IO_APIC_irq_trigger(int irq
)
1310 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1311 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1312 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1313 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1314 return irq_trigger(idx
);
1318 * nonexistent IRQs are edge default
1323 static inline int IO_APIC_irq_trigger(int irq
)
1329 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1332 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1333 trigger
== IOAPIC_LEVEL
)
1334 desc
->status
|= IRQ_LEVEL
;
1336 desc
->status
&= ~IRQ_LEVEL
;
1338 if (irq_remapped(irq
)) {
1339 desc
->status
|= IRQ_MOVE_PCNTXT
;
1341 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1345 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1346 handle_edge_irq
, "edge");
1350 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1351 trigger
== IOAPIC_LEVEL
)
1352 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1356 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1357 handle_edge_irq
, "edge");
1360 int setup_ioapic_entry(int apic_id
, int irq
,
1361 struct IO_APIC_route_entry
*entry
,
1362 unsigned int destination
, int trigger
,
1363 int polarity
, int vector
, int pin
)
1366 * add it to the IO-APIC irq-routing table:
1368 memset(entry
,0,sizeof(*entry
));
1370 if (intr_remapping_enabled
) {
1371 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1373 struct IR_IO_APIC_route_entry
*ir_entry
=
1374 (struct IR_IO_APIC_route_entry
*) entry
;
1378 panic("No mapping iommu for ioapic %d\n", apic_id
);
1380 index
= alloc_irte(iommu
, irq
, 1);
1382 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1384 memset(&irte
, 0, sizeof(irte
));
1387 irte
.dst_mode
= apic
->irq_dest_mode
;
1389 * Trigger mode in the IRTE will always be edge, and the
1390 * actual level or edge trigger will be setup in the IO-APIC
1391 * RTE. This will help simplify level triggered irq migration.
1392 * For more details, see the comments above explainig IO-APIC
1393 * irq migration in the presence of interrupt-remapping.
1395 irte
.trigger_mode
= 0;
1396 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1397 irte
.vector
= vector
;
1398 irte
.dest_id
= IRTE_DEST(destination
);
1400 /* Set source-id of interrupt request */
1401 set_ioapic_sid(&irte
, apic_id
);
1403 modify_irte(irq
, &irte
);
1405 ir_entry
->index2
= (index
>> 15) & 0x1;
1407 ir_entry
->format
= 1;
1408 ir_entry
->index
= (index
& 0x7fff);
1410 * IO-APIC RTE will be configured with virtual vector.
1411 * irq handler will do the explicit EOI to the io-apic.
1413 ir_entry
->vector
= pin
;
1415 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1416 entry
->dest_mode
= apic
->irq_dest_mode
;
1417 entry
->dest
= destination
;
1418 entry
->vector
= vector
;
1421 entry
->mask
= 0; /* enable IRQ */
1422 entry
->trigger
= trigger
;
1423 entry
->polarity
= polarity
;
1425 /* Mask level triggered irqs.
1426 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1433 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1434 int trigger
, int polarity
)
1436 struct irq_cfg
*cfg
;
1437 struct IO_APIC_route_entry entry
;
1440 if (!IO_APIC_IRQ(irq
))
1443 cfg
= desc
->chip_data
;
1446 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1447 * controllers like 8259. Now that IO-APIC can handle this irq, update
1450 if (irq
< legacy_pic
->nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1451 apic
->vector_allocation_domain(0, cfg
->domain
);
1453 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1456 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1458 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1459 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1460 "IRQ %d Mode:%i Active:%i)\n",
1461 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1462 irq
, trigger
, polarity
);
1465 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1466 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1467 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1468 mp_ioapics
[apic_id
].apicid
, pin
);
1469 __clear_irq_vector(irq
, cfg
);
1473 ioapic_register_intr(irq
, desc
, trigger
);
1474 if (irq
< legacy_pic
->nr_legacy_irqs
)
1475 legacy_pic
->chip
->mask(irq
);
1477 ioapic_write_entry(apic_id
, pin
, entry
);
1481 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1482 } mp_ioapic_routing
[MAX_IO_APICS
];
1484 static void __init
setup_IO_APIC_irqs(void)
1486 int apic_id
, pin
, idx
, irq
;
1488 struct irq_desc
*desc
;
1489 struct irq_cfg
*cfg
;
1490 int node
= cpu_to_node(boot_cpu_id
);
1492 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1494 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++)
1495 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1496 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1500 apic_printk(APIC_VERBOSE
,
1501 KERN_DEBUG
" %d-%d",
1502 mp_ioapics
[apic_id
].apicid
, pin
);
1504 apic_printk(APIC_VERBOSE
, " %d-%d",
1505 mp_ioapics
[apic_id
].apicid
, pin
);
1509 apic_printk(APIC_VERBOSE
,
1510 " (apicid-pin) not connected\n");
1514 irq
= pin_2_irq(idx
, apic_id
, pin
);
1516 if ((apic_id
> 0) && (irq
> 16))
1520 * Skip the timer IRQ if there's a quirk handler
1521 * installed and if it returns 1:
1523 if (apic
->multi_timer_check
&&
1524 apic
->multi_timer_check(apic_id
, irq
))
1527 desc
= irq_to_desc_alloc_node(irq
, node
);
1529 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1532 cfg
= desc
->chip_data
;
1533 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1535 * don't mark it in pin_programmed, so later acpi could
1536 * set it correctly when irq < 16
1538 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1539 irq_trigger(idx
), irq_polarity(idx
));
1543 apic_printk(APIC_VERBOSE
,
1544 " (apicid-pin) not connected\n");
1548 * for the gsit that is not in first ioapic
1549 * but could not use acpi_register_gsi()
1550 * like some special sci in IBM x3330
1552 void setup_IO_APIC_irq_extra(u32 gsi
)
1554 int apic_id
= 0, pin
, idx
, irq
;
1555 int node
= cpu_to_node(boot_cpu_id
);
1556 struct irq_desc
*desc
;
1557 struct irq_cfg
*cfg
;
1560 * Convert 'gsi' to 'ioapic.pin'.
1562 apic_id
= mp_find_ioapic(gsi
);
1566 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1567 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1571 irq
= pin_2_irq(idx
, apic_id
, pin
);
1572 #ifdef CONFIG_SPARSE_IRQ
1573 desc
= irq_to_desc(irq
);
1577 desc
= irq_to_desc_alloc_node(irq
, node
);
1579 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1583 cfg
= desc
->chip_data
;
1584 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1586 if (test_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
)) {
1587 pr_debug("Pin %d-%d already programmed\n",
1588 mp_ioapics
[apic_id
].apicid
, pin
);
1591 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1593 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1594 irq_trigger(idx
), irq_polarity(idx
));
1598 * Set up the timer pin, possibly with the 8259A-master behind.
1600 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1603 struct IO_APIC_route_entry entry
;
1605 if (intr_remapping_enabled
)
1608 memset(&entry
, 0, sizeof(entry
));
1611 * We use logical delivery to get the timer IRQ
1614 entry
.dest_mode
= apic
->irq_dest_mode
;
1615 entry
.mask
= 0; /* don't mask IRQ for edge */
1616 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1617 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1620 entry
.vector
= vector
;
1623 * The timer IRQ doesn't have to know that behind the
1624 * scene we may have a 8259A-master in AEOI mode ...
1626 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1629 * Add it to the IO-APIC irq-routing table:
1631 ioapic_write_entry(apic_id
, pin
, entry
);
1635 __apicdebuginit(void) print_IO_APIC(void)
1638 union IO_APIC_reg_00 reg_00
;
1639 union IO_APIC_reg_01 reg_01
;
1640 union IO_APIC_reg_02 reg_02
;
1641 union IO_APIC_reg_03 reg_03
;
1642 unsigned long flags
;
1643 struct irq_cfg
*cfg
;
1644 struct irq_desc
*desc
;
1647 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1648 for (i
= 0; i
< nr_ioapics
; i
++)
1649 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1650 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1653 * We are a bit conservative about what we expect. We have to
1654 * know about every hardware change ASAP.
1656 printk(KERN_INFO
"testing the IO APIC.......................\n");
1658 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1660 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1661 reg_00
.raw
= io_apic_read(apic
, 0);
1662 reg_01
.raw
= io_apic_read(apic
, 1);
1663 if (reg_01
.bits
.version
>= 0x10)
1664 reg_02
.raw
= io_apic_read(apic
, 2);
1665 if (reg_01
.bits
.version
>= 0x20)
1666 reg_03
.raw
= io_apic_read(apic
, 3);
1667 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1670 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1671 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1672 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1673 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1674 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1676 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1677 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1679 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1680 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1683 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1684 * but the value of reg_02 is read as the previous read register
1685 * value, so ignore it if reg_02 == reg_01.
1687 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1688 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1689 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1693 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1694 * or reg_03, but the value of reg_0[23] is read as the previous read
1695 * register value, so ignore it if reg_03 == reg_0[12].
1697 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1698 reg_03
.raw
!= reg_01
.raw
) {
1699 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1700 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1703 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1705 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1706 " Stat Dmod Deli Vect:\n");
1708 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1709 struct IO_APIC_route_entry entry
;
1711 entry
= ioapic_read_entry(apic
, i
);
1713 printk(KERN_DEBUG
" %02x %03X ",
1718 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1723 entry
.delivery_status
,
1725 entry
.delivery_mode
,
1730 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1731 for_each_irq_desc(irq
, desc
) {
1732 struct irq_pin_list
*entry
;
1734 cfg
= desc
->chip_data
;
1735 entry
= cfg
->irq_2_pin
;
1738 printk(KERN_DEBUG
"IRQ%d ", irq
);
1739 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1740 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1744 printk(KERN_INFO
".................................... done.\n");
1749 __apicdebuginit(void) print_APIC_field(int base
)
1755 for (i
= 0; i
< 8; i
++)
1756 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1758 printk(KERN_CONT
"\n");
1761 __apicdebuginit(void) print_local_APIC(void *dummy
)
1763 unsigned int i
, v
, ver
, maxlvt
;
1766 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1767 smp_processor_id(), hard_smp_processor_id());
1768 v
= apic_read(APIC_ID
);
1769 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1770 v
= apic_read(APIC_LVR
);
1771 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1772 ver
= GET_APIC_VERSION(v
);
1773 maxlvt
= lapic_get_maxlvt();
1775 v
= apic_read(APIC_TASKPRI
);
1776 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1778 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1779 if (!APIC_XAPIC(ver
)) {
1780 v
= apic_read(APIC_ARBPRI
);
1781 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1782 v
& APIC_ARBPRI_MASK
);
1784 v
= apic_read(APIC_PROCPRI
);
1785 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1789 * Remote read supported only in the 82489DX and local APIC for
1790 * Pentium processors.
1792 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1793 v
= apic_read(APIC_RRR
);
1794 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1797 v
= apic_read(APIC_LDR
);
1798 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1799 if (!x2apic_enabled()) {
1800 v
= apic_read(APIC_DFR
);
1801 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1803 v
= apic_read(APIC_SPIV
);
1804 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1806 printk(KERN_DEBUG
"... APIC ISR field:\n");
1807 print_APIC_field(APIC_ISR
);
1808 printk(KERN_DEBUG
"... APIC TMR field:\n");
1809 print_APIC_field(APIC_TMR
);
1810 printk(KERN_DEBUG
"... APIC IRR field:\n");
1811 print_APIC_field(APIC_IRR
);
1813 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1814 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1815 apic_write(APIC_ESR
, 0);
1817 v
= apic_read(APIC_ESR
);
1818 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1821 icr
= apic_icr_read();
1822 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1823 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1825 v
= apic_read(APIC_LVTT
);
1826 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1828 if (maxlvt
> 3) { /* PC is LVT#4. */
1829 v
= apic_read(APIC_LVTPC
);
1830 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1832 v
= apic_read(APIC_LVT0
);
1833 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1834 v
= apic_read(APIC_LVT1
);
1835 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1837 if (maxlvt
> 2) { /* ERR is LVT#3. */
1838 v
= apic_read(APIC_LVTERR
);
1839 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1842 v
= apic_read(APIC_TMICT
);
1843 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1844 v
= apic_read(APIC_TMCCT
);
1845 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1846 v
= apic_read(APIC_TDCR
);
1847 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1849 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1850 v
= apic_read(APIC_EFEAT
);
1851 maxlvt
= (v
>> 16) & 0xff;
1852 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1853 v
= apic_read(APIC_ECTRL
);
1854 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1855 for (i
= 0; i
< maxlvt
; i
++) {
1856 v
= apic_read(APIC_EILVTn(i
));
1857 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1863 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1871 for_each_online_cpu(cpu
) {
1874 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1879 __apicdebuginit(void) print_PIC(void)
1882 unsigned long flags
;
1884 if (!legacy_pic
->nr_legacy_irqs
)
1887 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1889 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1891 v
= inb(0xa1) << 8 | inb(0x21);
1892 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1894 v
= inb(0xa0) << 8 | inb(0x20);
1895 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1899 v
= inb(0xa0) << 8 | inb(0x20);
1903 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1905 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1907 v
= inb(0x4d1) << 8 | inb(0x4d0);
1908 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1911 static int __initdata show_lapic
= 1;
1912 static __init
int setup_show_lapic(char *arg
)
1916 if (strcmp(arg
, "all") == 0) {
1917 show_lapic
= CONFIG_NR_CPUS
;
1919 get_option(&arg
, &num
);
1926 __setup("show_lapic=", setup_show_lapic
);
1928 __apicdebuginit(int) print_ICs(void)
1930 if (apic_verbosity
== APIC_QUIET
)
1935 /* don't print out if apic is not there */
1936 if (!cpu_has_apic
&& !apic_from_smp_config())
1939 print_local_APICs(show_lapic
);
1945 fs_initcall(print_ICs
);
1948 /* Where if anywhere is the i8259 connect in external int mode */
1949 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1951 void __init
enable_IO_APIC(void)
1953 union IO_APIC_reg_01 reg_01
;
1954 int i8259_apic
, i8259_pin
;
1956 unsigned long flags
;
1959 * The number of IO-APIC IRQ registers (== #pins):
1961 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1962 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1963 reg_01
.raw
= io_apic_read(apic
, 1);
1964 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1965 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1968 if (!legacy_pic
->nr_legacy_irqs
)
1971 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1973 /* See if any of the pins is in ExtINT mode */
1974 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1975 struct IO_APIC_route_entry entry
;
1976 entry
= ioapic_read_entry(apic
, pin
);
1978 /* If the interrupt line is enabled and in ExtInt mode
1979 * I have found the pin where the i8259 is connected.
1981 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1982 ioapic_i8259
.apic
= apic
;
1983 ioapic_i8259
.pin
= pin
;
1989 /* Look to see what if the MP table has reported the ExtINT */
1990 /* If we could not find the appropriate pin by looking at the ioapic
1991 * the i8259 probably is not connected the ioapic but give the
1992 * mptable a chance anyway.
1994 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1995 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1996 /* Trust the MP table if nothing is setup in the hardware */
1997 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1998 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1999 ioapic_i8259
.pin
= i8259_pin
;
2000 ioapic_i8259
.apic
= i8259_apic
;
2002 /* Complain if the MP table and the hardware disagree */
2003 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2004 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2006 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2010 * Do not trust the IO-APIC being empty at bootup
2016 * Not an __init, needed by the reboot code
2018 void disable_IO_APIC(void)
2021 * Clear the IO-APIC before rebooting:
2025 if (!legacy_pic
->nr_legacy_irqs
)
2029 * If the i8259 is routed through an IOAPIC
2030 * Put that IOAPIC in virtual wire mode
2031 * so legacy interrupts can be delivered.
2033 * With interrupt-remapping, for now we will use virtual wire A mode,
2034 * as virtual wire B is little complex (need to configure both
2035 * IOAPIC RTE aswell as interrupt-remapping table entry).
2036 * As this gets called during crash dump, keep this simple for now.
2038 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2039 struct IO_APIC_route_entry entry
;
2041 memset(&entry
, 0, sizeof(entry
));
2042 entry
.mask
= 0; /* Enabled */
2043 entry
.trigger
= 0; /* Edge */
2045 entry
.polarity
= 0; /* High */
2046 entry
.delivery_status
= 0;
2047 entry
.dest_mode
= 0; /* Physical */
2048 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2050 entry
.dest
= read_apic_id();
2053 * Add it to the IO-APIC irq-routing table:
2055 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2059 * Use virtual wire A mode when interrupt remapping is enabled.
2061 if (cpu_has_apic
|| apic_from_smp_config())
2062 disconnect_bsp_APIC(!intr_remapping_enabled
&&
2063 ioapic_i8259
.pin
!= -1);
2066 #ifdef CONFIG_X86_32
2068 * function to set the IO-APIC physical IDs based on the
2069 * values stored in the MPC table.
2071 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2074 void __init
setup_ioapic_ids_from_mpc(void)
2076 union IO_APIC_reg_00 reg_00
;
2077 physid_mask_t phys_id_present_map
;
2080 unsigned char old_id
;
2081 unsigned long flags
;
2086 * Don't check I/O APIC IDs for xAPIC systems. They have
2087 * no meaning without the serial APIC bus.
2089 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2090 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2093 * This is broken; anything with a real cpu count has to
2094 * circumvent this idiocy regardless.
2096 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
2099 * Set the IOAPIC ID to the value stored in the MPC table.
2101 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2103 /* Read the register 0 value */
2104 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2105 reg_00
.raw
= io_apic_read(apic_id
, 0);
2106 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2108 old_id
= mp_ioapics
[apic_id
].apicid
;
2110 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2111 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2112 apic_id
, mp_ioapics
[apic_id
].apicid
);
2113 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2115 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2119 * Sanity check, is the ID really free? Every APIC in a
2120 * system must have a unique ID or we get lots of nice
2121 * 'stuck on smp_invalidate_needed IPI wait' messages.
2123 if (apic
->check_apicid_used(&phys_id_present_map
,
2124 mp_ioapics
[apic_id
].apicid
)) {
2125 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2126 apic_id
, mp_ioapics
[apic_id
].apicid
);
2127 for (i
= 0; i
< get_physical_broadcast(); i
++)
2128 if (!physid_isset(i
, phys_id_present_map
))
2130 if (i
>= get_physical_broadcast())
2131 panic("Max APIC ID exceeded!\n");
2132 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2134 physid_set(i
, phys_id_present_map
);
2135 mp_ioapics
[apic_id
].apicid
= i
;
2138 apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
, &tmp
);
2139 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2140 "phys_id_present_map\n",
2141 mp_ioapics
[apic_id
].apicid
);
2142 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2147 * We need to adjust the IRQ routing table
2148 * if the ID changed.
2150 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2151 for (i
= 0; i
< mp_irq_entries
; i
++)
2152 if (mp_irqs
[i
].dstapic
== old_id
)
2154 = mp_ioapics
[apic_id
].apicid
;
2157 * Read the right value from the MPC table and
2158 * write it into the ID register.
2160 apic_printk(APIC_VERBOSE
, KERN_INFO
2161 "...changing IO-APIC physical APIC ID to %d ...",
2162 mp_ioapics
[apic_id
].apicid
);
2164 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2165 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2166 io_apic_write(apic_id
, 0, reg_00
.raw
);
2167 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2172 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2173 reg_00
.raw
= io_apic_read(apic_id
, 0);
2174 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2175 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2176 printk("could not set ID!\n");
2178 apic_printk(APIC_VERBOSE
, " ok.\n");
2183 int no_timer_check __initdata
;
2185 static int __init
notimercheck(char *s
)
2190 __setup("no_timer_check", notimercheck
);
2193 * There is a nasty bug in some older SMP boards, their mptable lies
2194 * about the timer IRQ. We do the following to work around the situation:
2196 * - timer IRQ defaults to IO-APIC IRQ
2197 * - if this function detects that timer IRQs are defunct, then we fall
2198 * back to ISA timer IRQs
2200 static int __init
timer_irq_works(void)
2202 unsigned long t1
= jiffies
;
2203 unsigned long flags
;
2208 local_save_flags(flags
);
2210 /* Let ten ticks pass... */
2211 mdelay((10 * 1000) / HZ
);
2212 local_irq_restore(flags
);
2215 * Expect a few ticks at least, to be sure some possible
2216 * glue logic does not lock up after one or two first
2217 * ticks in a non-ExtINT mode. Also the local APIC
2218 * might have cached one ExtINT interrupt. Finally, at
2219 * least one tick may be lost due to delays.
2223 if (time_after(jiffies
, t1
+ 4))
2229 * In the SMP+IOAPIC case it might happen that there are an unspecified
2230 * number of pending IRQ events unhandled. These cases are very rare,
2231 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2232 * better to do it this way as thus we do not have to be aware of
2233 * 'pending' interrupts in the IRQ path, except at this point.
2236 * Edge triggered needs to resend any interrupt
2237 * that was delayed but this is now handled in the device
2242 * Starting up a edge-triggered IO-APIC interrupt is
2243 * nasty - we need to make sure that we get the edge.
2244 * If it is already asserted for some reason, we need
2245 * return 1 to indicate that is was pending.
2247 * This is not complete - we should be able to fake
2248 * an edge even if it isn't on the 8259A...
2251 static unsigned int startup_ioapic_irq(unsigned int irq
)
2253 int was_pending
= 0;
2254 unsigned long flags
;
2255 struct irq_cfg
*cfg
;
2257 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2258 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2259 legacy_pic
->chip
->mask(irq
);
2260 if (legacy_pic
->irq_pending(irq
))
2264 __unmask_IO_APIC_irq(cfg
);
2265 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2270 static int ioapic_retrigger_irq(unsigned int irq
)
2273 struct irq_cfg
*cfg
= irq_cfg(irq
);
2274 unsigned long flags
;
2276 raw_spin_lock_irqsave(&vector_lock
, flags
);
2277 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2278 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2284 * Level and edge triggered IO-APIC interrupts need different handling,
2285 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2286 * handled with the level-triggered descriptor, but that one has slightly
2287 * more overhead. Level-triggered interrupts cannot be handled with the
2288 * edge-triggered handler, without risking IRQ storms and other ugly
2293 void send_cleanup_vector(struct irq_cfg
*cfg
)
2295 cpumask_var_t cleanup_mask
;
2297 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2299 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2300 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2302 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2303 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2304 free_cpumask_var(cleanup_mask
);
2306 cfg
->move_in_progress
= 0;
2309 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2312 struct irq_pin_list
*entry
;
2313 u8 vector
= cfg
->vector
;
2315 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2321 * With interrupt-remapping, destination information comes
2322 * from interrupt-remapping table entry.
2324 if (!irq_remapped(irq
))
2325 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2326 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2327 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2329 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2334 * Either sets desc->affinity to a valid value, and returns
2335 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2336 * leaves desc->affinity untouched.
2339 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
,
2340 unsigned int *dest_id
)
2342 struct irq_cfg
*cfg
;
2345 if (!cpumask_intersects(mask
, cpu_online_mask
))
2349 cfg
= desc
->chip_data
;
2350 if (assign_irq_vector(irq
, cfg
, mask
))
2353 cpumask_copy(desc
->affinity
, mask
);
2355 *dest_id
= apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2360 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2362 struct irq_cfg
*cfg
;
2363 unsigned long flags
;
2369 cfg
= desc
->chip_data
;
2371 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2372 ret
= set_desc_affinity(desc
, mask
, &dest
);
2374 /* Only the high 8 bits are valid. */
2375 dest
= SET_APIC_LOGICAL_ID(dest
);
2376 __target_IO_APIC_irq(irq
, dest
, cfg
);
2378 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2384 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2386 struct irq_desc
*desc
;
2388 desc
= irq_to_desc(irq
);
2390 return set_ioapic_affinity_irq_desc(desc
, mask
);
2393 #ifdef CONFIG_INTR_REMAP
2396 * Migrate the IO-APIC irq in the presence of intr-remapping.
2398 * For both level and edge triggered, irq migration is a simple atomic
2399 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2401 * For level triggered, we eliminate the io-apic RTE modification (with the
2402 * updated vector information), by using a virtual vector (io-apic pin number).
2403 * Real vector that is used for interrupting cpu will be coming from
2404 * the interrupt-remapping table entry.
2407 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2409 struct irq_cfg
*cfg
;
2415 if (!cpumask_intersects(mask
, cpu_online_mask
))
2419 if (get_irte(irq
, &irte
))
2422 cfg
= desc
->chip_data
;
2423 if (assign_irq_vector(irq
, cfg
, mask
))
2426 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2428 irte
.vector
= cfg
->vector
;
2429 irte
.dest_id
= IRTE_DEST(dest
);
2432 * Modified the IRTE and flushes the Interrupt entry cache.
2434 modify_irte(irq
, &irte
);
2436 if (cfg
->move_in_progress
)
2437 send_cleanup_vector(cfg
);
2439 cpumask_copy(desc
->affinity
, mask
);
2445 * Migrates the IRQ destination in the process context.
2447 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2448 const struct cpumask
*mask
)
2450 return migrate_ioapic_irq_desc(desc
, mask
);
2452 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2453 const struct cpumask
*mask
)
2455 struct irq_desc
*desc
= irq_to_desc(irq
);
2457 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2460 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2461 const struct cpumask
*mask
)
2467 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2469 unsigned vector
, me
;
2475 me
= smp_processor_id();
2476 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2479 struct irq_desc
*desc
;
2480 struct irq_cfg
*cfg
;
2481 irq
= __get_cpu_var(vector_irq
)[vector
];
2486 desc
= irq_to_desc(irq
);
2491 raw_spin_lock(&desc
->lock
);
2494 * Check if the irq migration is in progress. If so, we
2495 * haven't received the cleanup request yet for this irq.
2497 if (cfg
->move_in_progress
)
2500 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2503 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2505 * Check if the vector that needs to be cleanedup is
2506 * registered at the cpu's IRR. If so, then this is not
2507 * the best time to clean it up. Lets clean it up in the
2508 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2511 if (irr
& (1 << (vector
% 32))) {
2512 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2515 __get_cpu_var(vector_irq
)[vector
] = -1;
2517 raw_spin_unlock(&desc
->lock
);
2523 static void __irq_complete_move(struct irq_desc
**descp
, unsigned vector
)
2525 struct irq_desc
*desc
= *descp
;
2526 struct irq_cfg
*cfg
= desc
->chip_data
;
2529 if (likely(!cfg
->move_in_progress
))
2532 me
= smp_processor_id();
2534 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2535 send_cleanup_vector(cfg
);
2538 static void irq_complete_move(struct irq_desc
**descp
)
2540 __irq_complete_move(descp
, ~get_irq_regs()->orig_ax
);
2543 void irq_force_complete_move(int irq
)
2545 struct irq_desc
*desc
= irq_to_desc(irq
);
2546 struct irq_cfg
*cfg
= desc
->chip_data
;
2548 __irq_complete_move(&desc
, cfg
->vector
);
2551 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2554 static void ack_apic_edge(unsigned int irq
)
2556 struct irq_desc
*desc
= irq_to_desc(irq
);
2558 irq_complete_move(&desc
);
2559 move_native_irq(irq
);
2563 atomic_t irq_mis_count
;
2566 * IO-APIC versions below 0x20 don't support EOI register.
2567 * For the record, here is the information about various versions:
2569 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2570 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2573 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2574 * version as 0x2. This is an error with documentation and these ICH chips
2575 * use io-apic's of version 0x20.
2577 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2578 * Otherwise, we simulate the EOI message manually by changing the trigger
2579 * mode to edge and then back to level, with RTE being masked during this.
2581 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2583 struct irq_pin_list
*entry
;
2585 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2586 if (mp_ioapics
[entry
->apic
].apicver
>= 0x20) {
2588 * Intr-remapping uses pin number as the virtual vector
2589 * in the RTE. Actual vector is programmed in
2590 * intr-remapping table entry. Hence for the io-apic
2591 * EOI we use the pin number.
2593 if (irq_remapped(irq
))
2594 io_apic_eoi(entry
->apic
, entry
->pin
);
2596 io_apic_eoi(entry
->apic
, cfg
->vector
);
2598 __mask_and_edge_IO_APIC_irq(entry
);
2599 __unmask_and_level_IO_APIC_irq(entry
);
2604 static void eoi_ioapic_irq(struct irq_desc
*desc
)
2606 struct irq_cfg
*cfg
;
2607 unsigned long flags
;
2611 cfg
= desc
->chip_data
;
2613 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2614 __eoi_ioapic_irq(irq
, cfg
);
2615 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2618 static void ack_apic_level(unsigned int irq
)
2620 struct irq_desc
*desc
= irq_to_desc(irq
);
2623 struct irq_cfg
*cfg
;
2624 int do_unmask_irq
= 0;
2626 irq_complete_move(&desc
);
2627 #ifdef CONFIG_GENERIC_PENDING_IRQ
2628 /* If we are moving the irq we need to mask it */
2629 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2631 mask_IO_APIC_irq_desc(desc
);
2636 * It appears there is an erratum which affects at least version 0x11
2637 * of I/O APIC (that's the 82093AA and cores integrated into various
2638 * chipsets). Under certain conditions a level-triggered interrupt is
2639 * erroneously delivered as edge-triggered one but the respective IRR
2640 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2641 * message but it will never arrive and further interrupts are blocked
2642 * from the source. The exact reason is so far unknown, but the
2643 * phenomenon was observed when two consecutive interrupt requests
2644 * from a given source get delivered to the same CPU and the source is
2645 * temporarily disabled in between.
2647 * A workaround is to simulate an EOI message manually. We achieve it
2648 * by setting the trigger mode to edge and then to level when the edge
2649 * trigger mode gets detected in the TMR of a local APIC for a
2650 * level-triggered interrupt. We mask the source for the time of the
2651 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2652 * The idea is from Manfred Spraul. --macro
2654 * Also in the case when cpu goes offline, fixup_irqs() will forward
2655 * any unhandled interrupt on the offlined cpu to the new cpu
2656 * destination that is handling the corresponding interrupt. This
2657 * interrupt forwarding is done via IPI's. Hence, in this case also
2658 * level-triggered io-apic interrupt will be seen as an edge
2659 * interrupt in the IRR. And we can't rely on the cpu's EOI
2660 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2661 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2662 * supporting EOI register, we do an explicit EOI to clear the
2663 * remote IRR and on IO-APIC's which don't have an EOI register,
2664 * we use the above logic (mask+edge followed by unmask+level) from
2665 * Manfred Spraul to clear the remote IRR.
2667 cfg
= desc
->chip_data
;
2669 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2672 * We must acknowledge the irq before we move it or the acknowledge will
2673 * not propagate properly.
2678 * Tail end of clearing remote IRR bit (either by delivering the EOI
2679 * message via io-apic EOI register write or simulating it using
2680 * mask+edge followed by unnask+level logic) manually when the
2681 * level triggered interrupt is seen as the edge triggered interrupt
2684 if (!(v
& (1 << (i
& 0x1f)))) {
2685 atomic_inc(&irq_mis_count
);
2687 eoi_ioapic_irq(desc
);
2690 /* Now we can move and renable the irq */
2691 if (unlikely(do_unmask_irq
)) {
2692 /* Only migrate the irq if the ack has been received.
2694 * On rare occasions the broadcast level triggered ack gets
2695 * delayed going to ioapics, and if we reprogram the
2696 * vector while Remote IRR is still set the irq will never
2699 * To prevent this scenario we read the Remote IRR bit
2700 * of the ioapic. This has two effects.
2701 * - On any sane system the read of the ioapic will
2702 * flush writes (and acks) going to the ioapic from
2704 * - We get to see if the ACK has actually been delivered.
2706 * Based on failed experiments of reprogramming the
2707 * ioapic entry from outside of irq context starting
2708 * with masking the ioapic entry and then polling until
2709 * Remote IRR was clear before reprogramming the
2710 * ioapic I don't trust the Remote IRR bit to be
2711 * completey accurate.
2713 * However there appears to be no other way to plug
2714 * this race, so if the Remote IRR bit is not
2715 * accurate and is causing problems then it is a hardware bug
2716 * and you can go talk to the chipset vendor about it.
2718 cfg
= desc
->chip_data
;
2719 if (!io_apic_level_ack_pending(cfg
))
2720 move_masked_irq(irq
);
2721 unmask_IO_APIC_irq_desc(desc
);
2725 #ifdef CONFIG_INTR_REMAP
2726 static void ir_ack_apic_edge(unsigned int irq
)
2731 static void ir_ack_apic_level(unsigned int irq
)
2733 struct irq_desc
*desc
= irq_to_desc(irq
);
2736 eoi_ioapic_irq(desc
);
2738 #endif /* CONFIG_INTR_REMAP */
2740 static struct irq_chip ioapic_chip __read_mostly
= {
2742 .startup
= startup_ioapic_irq
,
2743 .mask
= mask_IO_APIC_irq
,
2744 .unmask
= unmask_IO_APIC_irq
,
2745 .ack
= ack_apic_edge
,
2746 .eoi
= ack_apic_level
,
2748 .set_affinity
= set_ioapic_affinity_irq
,
2750 .retrigger
= ioapic_retrigger_irq
,
2753 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2754 .name
= "IR-IO-APIC",
2755 .startup
= startup_ioapic_irq
,
2756 .mask
= mask_IO_APIC_irq
,
2757 .unmask
= unmask_IO_APIC_irq
,
2758 #ifdef CONFIG_INTR_REMAP
2759 .ack
= ir_ack_apic_edge
,
2760 .eoi
= ir_ack_apic_level
,
2762 .set_affinity
= set_ir_ioapic_affinity_irq
,
2765 .retrigger
= ioapic_retrigger_irq
,
2768 static inline void init_IO_APIC_traps(void)
2771 struct irq_desc
*desc
;
2772 struct irq_cfg
*cfg
;
2775 * NOTE! The local APIC isn't very good at handling
2776 * multiple interrupts at the same interrupt level.
2777 * As the interrupt level is determined by taking the
2778 * vector number and shifting that right by 4, we
2779 * want to spread these out a bit so that they don't
2780 * all fall in the same interrupt level.
2782 * Also, we've got to be careful not to trash gate
2783 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2785 for_each_irq_desc(irq
, desc
) {
2786 cfg
= desc
->chip_data
;
2787 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2789 * Hmm.. We don't have an entry for this,
2790 * so default to an old-fashioned 8259
2791 * interrupt if we can..
2793 if (irq
< legacy_pic
->nr_legacy_irqs
)
2794 legacy_pic
->make_irq(irq
);
2796 /* Strange. Oh, well.. */
2797 desc
->chip
= &no_irq_chip
;
2803 * The local APIC irq-chip implementation:
2806 static void mask_lapic_irq(unsigned int irq
)
2810 v
= apic_read(APIC_LVT0
);
2811 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2814 static void unmask_lapic_irq(unsigned int irq
)
2818 v
= apic_read(APIC_LVT0
);
2819 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2822 static void ack_lapic_irq(unsigned int irq
)
2827 static struct irq_chip lapic_chip __read_mostly
= {
2828 .name
= "local-APIC",
2829 .mask
= mask_lapic_irq
,
2830 .unmask
= unmask_lapic_irq
,
2831 .ack
= ack_lapic_irq
,
2834 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2836 desc
->status
&= ~IRQ_LEVEL
;
2837 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2841 static void __init
setup_nmi(void)
2844 * Dirty trick to enable the NMI watchdog ...
2845 * We put the 8259A master into AEOI mode and
2846 * unmask on all local APICs LVT0 as NMI.
2848 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2849 * is from Maciej W. Rozycki - so we do not have to EOI from
2850 * the NMI handler or the timer interrupt.
2852 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2854 enable_NMI_through_LVT0();
2856 apic_printk(APIC_VERBOSE
, " done.\n");
2860 * This looks a bit hackish but it's about the only one way of sending
2861 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2862 * not support the ExtINT mode, unfortunately. We need to send these
2863 * cycles as some i82489DX-based boards have glue logic that keeps the
2864 * 8259A interrupt line asserted until INTA. --macro
2866 static inline void __init
unlock_ExtINT_logic(void)
2869 struct IO_APIC_route_entry entry0
, entry1
;
2870 unsigned char save_control
, save_freq_select
;
2872 pin
= find_isa_irq_pin(8, mp_INT
);
2877 apic
= find_isa_irq_apic(8, mp_INT
);
2883 entry0
= ioapic_read_entry(apic
, pin
);
2884 clear_IO_APIC_pin(apic
, pin
);
2886 memset(&entry1
, 0, sizeof(entry1
));
2888 entry1
.dest_mode
= 0; /* physical delivery */
2889 entry1
.mask
= 0; /* unmask IRQ now */
2890 entry1
.dest
= hard_smp_processor_id();
2891 entry1
.delivery_mode
= dest_ExtINT
;
2892 entry1
.polarity
= entry0
.polarity
;
2896 ioapic_write_entry(apic
, pin
, entry1
);
2898 save_control
= CMOS_READ(RTC_CONTROL
);
2899 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2900 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2902 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2907 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2911 CMOS_WRITE(save_control
, RTC_CONTROL
);
2912 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2913 clear_IO_APIC_pin(apic
, pin
);
2915 ioapic_write_entry(apic
, pin
, entry0
);
2918 static int disable_timer_pin_1 __initdata
;
2919 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2920 static int __init
disable_timer_pin_setup(char *arg
)
2922 disable_timer_pin_1
= 1;
2925 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2927 int timer_through_8259 __initdata
;
2930 * This code may look a bit paranoid, but it's supposed to cooperate with
2931 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2932 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2933 * fanatically on his truly buggy board.
2935 * FIXME: really need to revamp this for all platforms.
2937 static inline void __init
check_timer(void)
2939 struct irq_desc
*desc
= irq_to_desc(0);
2940 struct irq_cfg
*cfg
= desc
->chip_data
;
2941 int node
= cpu_to_node(boot_cpu_id
);
2942 int apic1
, pin1
, apic2
, pin2
;
2943 unsigned long flags
;
2946 local_irq_save(flags
);
2949 * get/set the timer IRQ vector:
2951 legacy_pic
->chip
->mask(0);
2952 assign_irq_vector(0, cfg
, apic
->target_cpus());
2955 * As IRQ0 is to be enabled in the 8259A, the virtual
2956 * wire has to be disabled in the local APIC. Also
2957 * timer interrupts need to be acknowledged manually in
2958 * the 8259A for the i82489DX when using the NMI
2959 * watchdog as that APIC treats NMIs as level-triggered.
2960 * The AEOI mode will finish them in the 8259A
2963 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2964 legacy_pic
->init(1);
2965 #ifdef CONFIG_X86_32
2969 ver
= apic_read(APIC_LVR
);
2970 ver
= GET_APIC_VERSION(ver
);
2971 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2975 pin1
= find_isa_irq_pin(0, mp_INT
);
2976 apic1
= find_isa_irq_apic(0, mp_INT
);
2977 pin2
= ioapic_i8259
.pin
;
2978 apic2
= ioapic_i8259
.apic
;
2980 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2981 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2982 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2985 * Some BIOS writers are clueless and report the ExtINTA
2986 * I/O APIC input from the cascaded 8259A as the timer
2987 * interrupt input. So just in case, if only one pin
2988 * was found above, try it both directly and through the
2992 if (intr_remapping_enabled
)
2993 panic("BIOS bug: timer not connected to IO-APIC");
2997 } else if (pin2
== -1) {
3004 * Ok, does IRQ0 through the IOAPIC work?
3007 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
3008 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
3010 /* for edge trigger, setup_IO_APIC_irq already
3011 * leave it unmasked.
3012 * so only need to unmask if it is level-trigger
3013 * do we really have level trigger timer?
3016 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
3017 if (idx
!= -1 && irq_trigger(idx
))
3018 unmask_IO_APIC_irq_desc(desc
);
3020 if (timer_irq_works()) {
3021 if (nmi_watchdog
== NMI_IO_APIC
) {
3023 legacy_pic
->chip
->unmask(0);
3025 if (disable_timer_pin_1
> 0)
3026 clear_IO_APIC_pin(0, pin1
);
3029 if (intr_remapping_enabled
)
3030 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3031 local_irq_disable();
3032 clear_IO_APIC_pin(apic1
, pin1
);
3034 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
3035 "8254 timer not connected to IO-APIC\n");
3037 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
3038 "(IRQ0) through the 8259A ...\n");
3039 apic_printk(APIC_QUIET
, KERN_INFO
3040 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
3042 * legacy devices should be connected to IO APIC #0
3044 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
3045 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
3046 legacy_pic
->chip
->unmask(0);
3047 if (timer_irq_works()) {
3048 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
3049 timer_through_8259
= 1;
3050 if (nmi_watchdog
== NMI_IO_APIC
) {
3051 legacy_pic
->chip
->mask(0);
3053 legacy_pic
->chip
->unmask(0);
3058 * Cleanup, just in case ...
3060 local_irq_disable();
3061 legacy_pic
->chip
->mask(0);
3062 clear_IO_APIC_pin(apic2
, pin2
);
3063 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
3066 if (nmi_watchdog
== NMI_IO_APIC
) {
3067 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
3068 "through the IO-APIC - disabling NMI Watchdog!\n");
3069 nmi_watchdog
= NMI_NONE
;
3071 #ifdef CONFIG_X86_32
3075 apic_printk(APIC_QUIET
, KERN_INFO
3076 "...trying to set up timer as Virtual Wire IRQ...\n");
3078 lapic_register_intr(0, desc
);
3079 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3080 legacy_pic
->chip
->unmask(0);
3082 if (timer_irq_works()) {
3083 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3086 local_irq_disable();
3087 legacy_pic
->chip
->mask(0);
3088 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3089 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3091 apic_printk(APIC_QUIET
, KERN_INFO
3092 "...trying to set up timer as ExtINT IRQ...\n");
3094 legacy_pic
->init(0);
3095 legacy_pic
->make_irq(0);
3096 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3098 unlock_ExtINT_logic();
3100 if (timer_irq_works()) {
3101 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3104 local_irq_disable();
3105 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3106 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3107 "report. Then try booting with the 'noapic' option.\n");
3109 local_irq_restore(flags
);
3113 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3114 * to devices. However there may be an I/O APIC pin available for
3115 * this interrupt regardless. The pin may be left unconnected, but
3116 * typically it will be reused as an ExtINT cascade interrupt for
3117 * the master 8259A. In the MPS case such a pin will normally be
3118 * reported as an ExtINT interrupt in the MP table. With ACPI
3119 * there is no provision for ExtINT interrupts, and in the absence
3120 * of an override it would be treated as an ordinary ISA I/O APIC
3121 * interrupt, that is edge-triggered and unmasked by default. We
3122 * used to do this, but it caused problems on some systems because
3123 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3124 * the same ExtINT cascade interrupt to drive the local APIC of the
3125 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3126 * the I/O APIC in all cases now. No actual device should request
3127 * it anyway. --macro
3129 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3131 void __init
setup_IO_APIC(void)
3135 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3137 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
3139 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3141 * Set up IO-APIC IRQ routing.
3143 x86_init
.mpparse
.setup_ioapic_ids();
3146 setup_IO_APIC_irqs();
3147 init_IO_APIC_traps();
3148 if (legacy_pic
->nr_legacy_irqs
)
3153 * Called after all the initialization is done. If we didnt find any
3154 * APIC bugs then we can allow the modify fast path
3157 static int __init
io_apic_bug_finalize(void)
3159 if (sis_apic_bug
== -1)
3164 late_initcall(io_apic_bug_finalize
);
3166 struct sysfs_ioapic_data
{
3167 struct sys_device dev
;
3168 struct IO_APIC_route_entry entry
[0];
3170 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3172 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3174 struct IO_APIC_route_entry
*entry
;
3175 struct sysfs_ioapic_data
*data
;
3178 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3179 entry
= data
->entry
;
3180 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3181 *entry
= ioapic_read_entry(dev
->id
, i
);
3186 static int ioapic_resume(struct sys_device
*dev
)
3188 struct IO_APIC_route_entry
*entry
;
3189 struct sysfs_ioapic_data
*data
;
3190 unsigned long flags
;
3191 union IO_APIC_reg_00 reg_00
;
3194 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3195 entry
= data
->entry
;
3197 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3198 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3199 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3200 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3201 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3203 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3204 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3205 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3210 static struct sysdev_class ioapic_sysdev_class
= {
3212 .suspend
= ioapic_suspend
,
3213 .resume
= ioapic_resume
,
3216 static int __init
ioapic_init_sysfs(void)
3218 struct sys_device
* dev
;
3221 error
= sysdev_class_register(&ioapic_sysdev_class
);
3225 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3226 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3227 * sizeof(struct IO_APIC_route_entry
);
3228 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3229 if (!mp_ioapic_data
[i
]) {
3230 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3233 dev
= &mp_ioapic_data
[i
]->dev
;
3235 dev
->cls
= &ioapic_sysdev_class
;
3236 error
= sysdev_register(dev
);
3238 kfree(mp_ioapic_data
[i
]);
3239 mp_ioapic_data
[i
] = NULL
;
3240 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3248 device_initcall(ioapic_init_sysfs
);
3251 * Dynamic irq allocate and deallocation
3253 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3255 /* Allocate an unused irq */
3258 unsigned long flags
;
3259 struct irq_cfg
*cfg_new
= NULL
;
3260 struct irq_desc
*desc_new
= NULL
;
3263 if (irq_want
< nr_irqs_gsi
)
3264 irq_want
= nr_irqs_gsi
;
3266 raw_spin_lock_irqsave(&vector_lock
, flags
);
3267 for (new = irq_want
; new < nr_irqs
; new++) {
3268 desc_new
= irq_to_desc_alloc_node(new, node
);
3270 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3273 cfg_new
= desc_new
->chip_data
;
3275 if (cfg_new
->vector
!= 0)
3278 desc_new
= move_irq_desc(desc_new
, node
);
3279 cfg_new
= desc_new
->chip_data
;
3281 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3285 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3288 dynamic_irq_init_keep_chip_data(irq
);
3293 int create_irq(void)
3295 int node
= cpu_to_node(boot_cpu_id
);
3296 unsigned int irq_want
;
3299 irq_want
= nr_irqs_gsi
;
3300 irq
= create_irq_nr(irq_want
, node
);
3308 void destroy_irq(unsigned int irq
)
3310 unsigned long flags
;
3312 dynamic_irq_cleanup_keep_chip_data(irq
);
3315 raw_spin_lock_irqsave(&vector_lock
, flags
);
3316 __clear_irq_vector(irq
, get_irq_chip_data(irq
));
3317 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3321 * MSI message composition
3323 #ifdef CONFIG_PCI_MSI
3324 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3325 struct msi_msg
*msg
, u8 hpet_id
)
3327 struct irq_cfg
*cfg
;
3335 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3339 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3341 if (irq_remapped(irq
)) {
3346 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3347 BUG_ON(ir_index
== -1);
3349 memset (&irte
, 0, sizeof(irte
));
3352 irte
.dst_mode
= apic
->irq_dest_mode
;
3353 irte
.trigger_mode
= 0; /* edge */
3354 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3355 irte
.vector
= cfg
->vector
;
3356 irte
.dest_id
= IRTE_DEST(dest
);
3358 /* Set source-id of interrupt request */
3360 set_msi_sid(&irte
, pdev
);
3362 set_hpet_sid(&irte
, hpet_id
);
3364 modify_irte(irq
, &irte
);
3366 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3367 msg
->data
= sub_handle
;
3368 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3370 MSI_ADDR_IR_INDEX1(ir_index
) |
3371 MSI_ADDR_IR_INDEX2(ir_index
);
3373 if (x2apic_enabled())
3374 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3375 MSI_ADDR_EXT_DEST_ID(dest
);
3377 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3381 ((apic
->irq_dest_mode
== 0) ?
3382 MSI_ADDR_DEST_MODE_PHYSICAL
:
3383 MSI_ADDR_DEST_MODE_LOGICAL
) |
3384 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3385 MSI_ADDR_REDIRECTION_CPU
:
3386 MSI_ADDR_REDIRECTION_LOWPRI
) |
3387 MSI_ADDR_DEST_ID(dest
);
3390 MSI_DATA_TRIGGER_EDGE
|
3391 MSI_DATA_LEVEL_ASSERT
|
3392 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3393 MSI_DATA_DELIVERY_FIXED
:
3394 MSI_DATA_DELIVERY_LOWPRI
) |
3395 MSI_DATA_VECTOR(cfg
->vector
);
3401 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3403 struct irq_desc
*desc
= irq_to_desc(irq
);
3404 struct irq_cfg
*cfg
;
3408 if (set_desc_affinity(desc
, mask
, &dest
))
3411 cfg
= desc
->chip_data
;
3413 read_msi_msg_desc(desc
, &msg
);
3415 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3416 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3417 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3418 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3420 write_msi_msg_desc(desc
, &msg
);
3424 #ifdef CONFIG_INTR_REMAP
3426 * Migrate the MSI irq to another cpumask. This migration is
3427 * done in the process context using interrupt-remapping hardware.
3430 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3432 struct irq_desc
*desc
= irq_to_desc(irq
);
3433 struct irq_cfg
*cfg
= desc
->chip_data
;
3437 if (get_irte(irq
, &irte
))
3440 if (set_desc_affinity(desc
, mask
, &dest
))
3443 irte
.vector
= cfg
->vector
;
3444 irte
.dest_id
= IRTE_DEST(dest
);
3447 * atomically update the IRTE with the new destination and vector.
3449 modify_irte(irq
, &irte
);
3452 * After this point, all the interrupts will start arriving
3453 * at the new destination. So, time to cleanup the previous
3454 * vector allocation.
3456 if (cfg
->move_in_progress
)
3457 send_cleanup_vector(cfg
);
3463 #endif /* CONFIG_SMP */
3466 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3467 * which implement the MSI or MSI-X Capability Structure.
3469 static struct irq_chip msi_chip
= {
3471 .unmask
= unmask_msi_irq
,
3472 .mask
= mask_msi_irq
,
3473 .ack
= ack_apic_edge
,
3475 .set_affinity
= set_msi_irq_affinity
,
3477 .retrigger
= ioapic_retrigger_irq
,
3480 static struct irq_chip msi_ir_chip
= {
3481 .name
= "IR-PCI-MSI",
3482 .unmask
= unmask_msi_irq
,
3483 .mask
= mask_msi_irq
,
3484 #ifdef CONFIG_INTR_REMAP
3485 .ack
= ir_ack_apic_edge
,
3487 .set_affinity
= ir_set_msi_irq_affinity
,
3490 .retrigger
= ioapic_retrigger_irq
,
3494 * Map the PCI dev to the corresponding remapping hardware unit
3495 * and allocate 'nvec' consecutive interrupt-remapping table entries
3498 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3500 struct intel_iommu
*iommu
;
3503 iommu
= map_dev_to_ir(dev
);
3506 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3510 index
= alloc_irte(iommu
, irq
, nvec
);
3513 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3520 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3525 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3529 set_irq_msi(irq
, msidesc
);
3530 write_msi_msg(irq
, &msg
);
3532 if (irq_remapped(irq
)) {
3533 struct irq_desc
*desc
= irq_to_desc(irq
);
3535 * irq migration in process context
3537 desc
->status
|= IRQ_MOVE_PCNTXT
;
3538 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3540 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3542 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3547 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3550 int ret
, sub_handle
;
3551 struct msi_desc
*msidesc
;
3552 unsigned int irq_want
;
3553 struct intel_iommu
*iommu
= NULL
;
3557 /* x86 doesn't support multiple MSI yet */
3558 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3561 node
= dev_to_node(&dev
->dev
);
3562 irq_want
= nr_irqs_gsi
;
3564 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3565 irq
= create_irq_nr(irq_want
, node
);
3569 if (!intr_remapping_enabled
)
3574 * allocate the consecutive block of IRTE's
3577 index
= msi_alloc_irte(dev
, irq
, nvec
);
3583 iommu
= map_dev_to_ir(dev
);
3589 * setup the mapping between the irq and the IRTE
3590 * base index, the sub_handle pointing to the
3591 * appropriate interrupt remap table entry.
3593 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3596 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3608 void arch_teardown_msi_irq(unsigned int irq
)
3613 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3615 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3617 struct irq_desc
*desc
= irq_to_desc(irq
);
3618 struct irq_cfg
*cfg
;
3622 if (set_desc_affinity(desc
, mask
, &dest
))
3625 cfg
= desc
->chip_data
;
3627 dmar_msi_read(irq
, &msg
);
3629 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3630 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3631 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3632 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3634 dmar_msi_write(irq
, &msg
);
3639 #endif /* CONFIG_SMP */
3641 static struct irq_chip dmar_msi_type
= {
3643 .unmask
= dmar_msi_unmask
,
3644 .mask
= dmar_msi_mask
,
3645 .ack
= ack_apic_edge
,
3647 .set_affinity
= dmar_msi_set_affinity
,
3649 .retrigger
= ioapic_retrigger_irq
,
3652 int arch_setup_dmar_msi(unsigned int irq
)
3657 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3660 dmar_msi_write(irq
, &msg
);
3661 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3667 #ifdef CONFIG_HPET_TIMER
3670 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3672 struct irq_desc
*desc
= irq_to_desc(irq
);
3673 struct irq_cfg
*cfg
;
3677 if (set_desc_affinity(desc
, mask
, &dest
))
3680 cfg
= desc
->chip_data
;
3682 hpet_msi_read(irq
, &msg
);
3684 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3685 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3686 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3687 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3689 hpet_msi_write(irq
, &msg
);
3694 #endif /* CONFIG_SMP */
3696 static struct irq_chip ir_hpet_msi_type
= {
3697 .name
= "IR-HPET_MSI",
3698 .unmask
= hpet_msi_unmask
,
3699 .mask
= hpet_msi_mask
,
3700 #ifdef CONFIG_INTR_REMAP
3701 .ack
= ir_ack_apic_edge
,
3703 .set_affinity
= ir_set_msi_irq_affinity
,
3706 .retrigger
= ioapic_retrigger_irq
,
3709 static struct irq_chip hpet_msi_type
= {
3711 .unmask
= hpet_msi_unmask
,
3712 .mask
= hpet_msi_mask
,
3713 .ack
= ack_apic_edge
,
3715 .set_affinity
= hpet_msi_set_affinity
,
3717 .retrigger
= ioapic_retrigger_irq
,
3720 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3724 struct irq_desc
*desc
= irq_to_desc(irq
);
3726 if (intr_remapping_enabled
) {
3727 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3733 index
= alloc_irte(iommu
, irq
, 1);
3738 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3742 hpet_msi_write(irq
, &msg
);
3743 desc
->status
|= IRQ_MOVE_PCNTXT
;
3744 if (irq_remapped(irq
))
3745 set_irq_chip_and_handler_name(irq
, &ir_hpet_msi_type
,
3746 handle_edge_irq
, "edge");
3748 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
,
3749 handle_edge_irq
, "edge");
3755 #endif /* CONFIG_PCI_MSI */
3757 * Hypertransport interrupt support
3759 #ifdef CONFIG_HT_IRQ
3763 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3765 struct ht_irq_msg msg
;
3766 fetch_ht_irq_msg(irq
, &msg
);
3768 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3769 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3771 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3772 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3774 write_ht_irq_msg(irq
, &msg
);
3777 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3779 struct irq_desc
*desc
= irq_to_desc(irq
);
3780 struct irq_cfg
*cfg
;
3783 if (set_desc_affinity(desc
, mask
, &dest
))
3786 cfg
= desc
->chip_data
;
3788 target_ht_irq(irq
, dest
, cfg
->vector
);
3795 static struct irq_chip ht_irq_chip
= {
3797 .mask
= mask_ht_irq
,
3798 .unmask
= unmask_ht_irq
,
3799 .ack
= ack_apic_edge
,
3801 .set_affinity
= set_ht_irq_affinity
,
3803 .retrigger
= ioapic_retrigger_irq
,
3806 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3808 struct irq_cfg
*cfg
;
3815 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3817 struct ht_irq_msg msg
;
3820 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3821 apic
->target_cpus());
3823 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3827 HT_IRQ_LOW_DEST_ID(dest
) |
3828 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3829 ((apic
->irq_dest_mode
== 0) ?
3830 HT_IRQ_LOW_DM_PHYSICAL
:
3831 HT_IRQ_LOW_DM_LOGICAL
) |
3832 HT_IRQ_LOW_RQEOI_EDGE
|
3833 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3834 HT_IRQ_LOW_MT_FIXED
:
3835 HT_IRQ_LOW_MT_ARBITRATED
) |
3836 HT_IRQ_LOW_IRQ_MASKED
;
3838 write_ht_irq_msg(irq
, &msg
);
3840 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3841 handle_edge_irq
, "edge");
3843 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3847 #endif /* CONFIG_HT_IRQ */
3849 int __init
io_apic_get_redir_entries (int ioapic
)
3851 union IO_APIC_reg_01 reg_01
;
3852 unsigned long flags
;
3854 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3855 reg_01
.raw
= io_apic_read(ioapic
, 1);
3856 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3858 return reg_01
.bits
.entries
;
3861 void __init
probe_nr_irqs_gsi(void)
3865 nr
= acpi_probe_gsi();
3866 if (nr
> nr_irqs_gsi
) {
3869 /* for acpi=off or acpi is not compiled in */
3873 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3874 nr
+= io_apic_get_redir_entries(idx
) + 1;
3876 if (nr
> nr_irqs_gsi
)
3880 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3883 #ifdef CONFIG_SPARSE_IRQ
3884 int __init
arch_probe_nr_irqs(void)
3888 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3889 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3891 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3892 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3894 * for MSI and HT dyn irq
3896 nr
+= nr_irqs_gsi
* 16;
3905 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3906 struct io_apic_irq_attr
*irq_attr
)
3908 struct irq_desc
*desc
;
3909 struct irq_cfg
*cfg
;
3912 int trigger
, polarity
;
3914 ioapic
= irq_attr
->ioapic
;
3915 if (!IO_APIC_IRQ(irq
)) {
3916 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3922 node
= dev_to_node(dev
);
3924 node
= cpu_to_node(boot_cpu_id
);
3926 desc
= irq_to_desc_alloc_node(irq
, node
);
3928 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3932 pin
= irq_attr
->ioapic_pin
;
3933 trigger
= irq_attr
->trigger
;
3934 polarity
= irq_attr
->polarity
;
3937 * IRQs < 16 are already in the irq_2_pin[] map
3939 if (irq
>= legacy_pic
->nr_legacy_irqs
) {
3940 cfg
= desc
->chip_data
;
3941 if (add_pin_to_irq_node_nopanic(cfg
, node
, ioapic
, pin
)) {
3942 printk(KERN_INFO
"can not add pin %d for irq %d\n",
3948 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3953 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3954 struct io_apic_irq_attr
*irq_attr
)
3958 * Avoid pin reprogramming. PRTs typically include entries
3959 * with redundant pin->gsi mappings (but unique PCI devices);
3960 * we only program the IOAPIC on the first.
3962 ioapic
= irq_attr
->ioapic
;
3963 pin
= irq_attr
->ioapic_pin
;
3964 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3965 pr_debug("Pin %d-%d already programmed\n",
3966 mp_ioapics
[ioapic
].apicid
, pin
);
3969 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3971 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3974 u8 __init
io_apic_unique_id(u8 id
)
3976 #ifdef CONFIG_X86_32
3977 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3978 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3979 return io_apic_get_unique_id(nr_ioapics
, id
);
3984 DECLARE_BITMAP(used
, 256);
3986 bitmap_zero(used
, 256);
3987 for (i
= 0; i
< nr_ioapics
; i
++) {
3988 struct mpc_ioapic
*ia
= &mp_ioapics
[i
];
3989 __set_bit(ia
->apicid
, used
);
3991 if (!test_bit(id
, used
))
3993 return find_first_zero_bit(used
, 256);
3997 #ifdef CONFIG_X86_32
3998 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
4000 union IO_APIC_reg_00 reg_00
;
4001 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
4003 unsigned long flags
;
4007 * The P4 platform supports up to 256 APIC IDs on two separate APIC
4008 * buses (one for LAPICs, one for IOAPICs), where predecessors only
4009 * supports up to 16 on one shared APIC bus.
4011 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
4012 * advantage of new APIC bus architecture.
4015 if (physids_empty(apic_id_map
))
4016 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
4018 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4019 reg_00
.raw
= io_apic_read(ioapic
, 0);
4020 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4022 if (apic_id
>= get_physical_broadcast()) {
4023 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
4024 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
4025 apic_id
= reg_00
.bits
.ID
;
4029 * Every APIC in a system must have a unique ID or we get lots of nice
4030 * 'stuck on smp_invalidate_needed IPI wait' messages.
4032 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
4034 for (i
= 0; i
< get_physical_broadcast(); i
++) {
4035 if (!apic
->check_apicid_used(&apic_id_map
, i
))
4039 if (i
== get_physical_broadcast())
4040 panic("Max apic_id exceeded!\n");
4042 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
4043 "trying %d\n", ioapic
, apic_id
, i
);
4048 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
4049 physids_or(apic_id_map
, apic_id_map
, tmp
);
4051 if (reg_00
.bits
.ID
!= apic_id
) {
4052 reg_00
.bits
.ID
= apic_id
;
4054 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4055 io_apic_write(ioapic
, 0, reg_00
.raw
);
4056 reg_00
.raw
= io_apic_read(ioapic
, 0);
4057 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4060 if (reg_00
.bits
.ID
!= apic_id
) {
4061 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4066 apic_printk(APIC_VERBOSE
, KERN_INFO
4067 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4073 int __init
io_apic_get_version(int ioapic
)
4075 union IO_APIC_reg_01 reg_01
;
4076 unsigned long flags
;
4078 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4079 reg_01
.raw
= io_apic_read(ioapic
, 1);
4080 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4082 return reg_01
.bits
.version
;
4085 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
4089 if (skip_ioapic_setup
)
4092 for (i
= 0; i
< mp_irq_entries
; i
++)
4093 if (mp_irqs
[i
].irqtype
== mp_INT
&&
4094 mp_irqs
[i
].srcbusirq
== bus_irq
)
4096 if (i
>= mp_irq_entries
)
4099 *trigger
= irq_trigger(i
);
4100 *polarity
= irq_polarity(i
);
4105 * This function currently is only a helper for the i386 smp boot process where
4106 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4107 * so mask in all cases should simply be apic->target_cpus()
4110 void __init
setup_ioapic_dest(void)
4112 int pin
, ioapic
, irq
, irq_entry
;
4113 struct irq_desc
*desc
;
4114 const struct cpumask
*mask
;
4116 if (skip_ioapic_setup
== 1)
4119 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
4120 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4121 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4122 if (irq_entry
== -1)
4124 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4126 if ((ioapic
> 0) && (irq
> 16))
4129 desc
= irq_to_desc(irq
);
4132 * Honour affinities which have been set in early boot
4135 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4136 mask
= desc
->affinity
;
4138 mask
= apic
->target_cpus();
4140 if (intr_remapping_enabled
)
4141 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4143 set_ioapic_affinity_irq_desc(desc
, mask
);
4149 #define IOAPIC_RESOURCE_NAME_SIZE 11
4151 static struct resource
*ioapic_resources
;
4153 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
4156 struct resource
*res
;
4160 if (nr_ioapics
<= 0)
4163 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4166 mem
= alloc_bootmem(n
);
4169 mem
+= sizeof(struct resource
) * nr_ioapics
;
4171 for (i
= 0; i
< nr_ioapics
; i
++) {
4173 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4174 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
4175 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4178 ioapic_resources
= res
;
4183 void __init
ioapic_init_mappings(void)
4185 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4186 struct resource
*ioapic_res
;
4189 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
4190 for (i
= 0; i
< nr_ioapics
; i
++) {
4191 if (smp_found_config
) {
4192 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4193 #ifdef CONFIG_X86_32
4196 "WARNING: bogus zero IO-APIC "
4197 "address found in MPTABLE, "
4198 "disabling IO/APIC support!\n");
4199 smp_found_config
= 0;
4200 skip_ioapic_setup
= 1;
4201 goto fake_ioapic_page
;
4205 #ifdef CONFIG_X86_32
4208 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
4209 ioapic_phys
= __pa(ioapic_phys
);
4211 set_fixmap_nocache(idx
, ioapic_phys
);
4212 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
4213 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
4217 ioapic_res
->start
= ioapic_phys
;
4218 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
4223 void __init
ioapic_insert_resources(void)
4226 struct resource
*r
= ioapic_resources
;
4231 "IO APIC resources couldn't be allocated.\n");
4235 for (i
= 0; i
< nr_ioapics
; i
++) {
4236 insert_resource(&iomem_resource
, r
);
4241 int mp_find_ioapic(int gsi
)
4245 /* Find the IOAPIC that manages this GSI. */
4246 for (i
= 0; i
< nr_ioapics
; i
++) {
4247 if ((gsi
>= mp_gsi_routing
[i
].gsi_base
)
4248 && (gsi
<= mp_gsi_routing
[i
].gsi_end
))
4252 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
4256 int mp_find_ioapic_pin(int ioapic
, int gsi
)
4258 if (WARN_ON(ioapic
== -1))
4260 if (WARN_ON(gsi
> mp_gsi_routing
[ioapic
].gsi_end
))
4263 return gsi
- mp_gsi_routing
[ioapic
].gsi_base
;
4266 static int bad_ioapic(unsigned long address
)
4268 if (nr_ioapics
>= MAX_IO_APICS
) {
4269 printk(KERN_WARNING
"WARING: Max # of I/O APICs (%d) exceeded "
4270 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
4274 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
4275 " found in table, skipping!\n");
4281 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
4285 if (bad_ioapic(address
))
4290 mp_ioapics
[idx
].type
= MP_IOAPIC
;
4291 mp_ioapics
[idx
].flags
= MPC_APIC_USABLE
;
4292 mp_ioapics
[idx
].apicaddr
= address
;
4294 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
4295 mp_ioapics
[idx
].apicid
= io_apic_unique_id(id
);
4296 mp_ioapics
[idx
].apicver
= io_apic_get_version(idx
);
4299 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4300 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4302 mp_gsi_routing
[idx
].gsi_base
= gsi_base
;
4303 mp_gsi_routing
[idx
].gsi_end
= gsi_base
+
4304 io_apic_get_redir_entries(idx
);
4306 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4307 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].apicid
,
4308 mp_ioapics
[idx
].apicver
, mp_ioapics
[idx
].apicaddr
,
4309 mp_gsi_routing
[idx
].gsi_base
, mp_gsi_routing
[idx
].gsi_end
);
4314 /* Enable IOAPIC early just for system timer */
4315 void __init
pre_init_apic_IRQ0(void)
4317 struct irq_cfg
*cfg
;
4318 struct irq_desc
*desc
;
4320 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4322 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
4324 desc
= irq_to_desc_alloc_node(0, 0);
4329 add_pin_to_irq_node(cfg
, 0, 0, 0);
4330 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
4332 setup_IO_APIC_irq(0, 0, 0, desc
, 0, 0);