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x86/ioapic.c: convert __target_IO_APIC_irq to conventional for() loop
[mirror_ubuntu-kernels.git] / arch / x86 / kernel / apic / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
65
66 #include <asm/apic.h>
67
68 #define __apicdebuginit(type) static type __init
69
70 /*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74 int sis_apic_bug = -1;
75
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
78
79 /*
80 * # of IRQ routing registers
81 */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90
91 /* # of MP IRQ source entries */
92 int mp_irq_entries;
93
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
96 #endif
97
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
100 int skip_ioapic_setup;
101
102 void arch_disable_smp_support(void)
103 {
104 #ifdef CONFIG_PCI
105 noioapicquirk = 1;
106 noioapicreroute = -1;
107 #endif
108 skip_ioapic_setup = 1;
109 }
110
111 static int __init parse_noapic(char *str)
112 {
113 /* disable IO-APIC */
114 arch_disable_smp_support();
115 return 0;
116 }
117 early_param("noapic", parse_noapic);
118
119 struct irq_pin_list {
120 int apic, pin;
121 struct irq_pin_list *next;
122 };
123
124 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
125 {
126 struct irq_pin_list *pin;
127
128 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
129
130 return pin;
131 }
132
133 /*
134 * This is performance-critical, we want to do it O(1)
135 *
136 * Most irqs are mapped 1:1 with pins.
137 */
138 struct irq_cfg {
139 struct irq_pin_list *irq_2_pin;
140 cpumask_var_t domain;
141 cpumask_var_t old_domain;
142 unsigned move_cleanup_count;
143 u8 vector;
144 u8 move_in_progress : 1;
145 };
146
147 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
148 #ifdef CONFIG_SPARSE_IRQ
149 static struct irq_cfg irq_cfgx[] = {
150 #else
151 static struct irq_cfg irq_cfgx[NR_IRQS] = {
152 #endif
153 [0] = { .vector = IRQ0_VECTOR, },
154 [1] = { .vector = IRQ1_VECTOR, },
155 [2] = { .vector = IRQ2_VECTOR, },
156 [3] = { .vector = IRQ3_VECTOR, },
157 [4] = { .vector = IRQ4_VECTOR, },
158 [5] = { .vector = IRQ5_VECTOR, },
159 [6] = { .vector = IRQ6_VECTOR, },
160 [7] = { .vector = IRQ7_VECTOR, },
161 [8] = { .vector = IRQ8_VECTOR, },
162 [9] = { .vector = IRQ9_VECTOR, },
163 [10] = { .vector = IRQ10_VECTOR, },
164 [11] = { .vector = IRQ11_VECTOR, },
165 [12] = { .vector = IRQ12_VECTOR, },
166 [13] = { .vector = IRQ13_VECTOR, },
167 [14] = { .vector = IRQ14_VECTOR, },
168 [15] = { .vector = IRQ15_VECTOR, },
169 };
170
171 int __init arch_early_irq_init(void)
172 {
173 struct irq_cfg *cfg;
174 struct irq_desc *desc;
175 int count;
176 int node;
177 int i;
178
179 cfg = irq_cfgx;
180 count = ARRAY_SIZE(irq_cfgx);
181 node= cpu_to_node(boot_cpu_id);
182
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
187 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
188 if (i < NR_IRQS_LEGACY)
189 cpumask_setall(cfg[i].domain);
190 }
191
192 return 0;
193 }
194
195 #ifdef CONFIG_SPARSE_IRQ
196 static struct irq_cfg *irq_cfg(unsigned int irq)
197 {
198 struct irq_cfg *cfg = NULL;
199 struct irq_desc *desc;
200
201 desc = irq_to_desc(irq);
202 if (desc)
203 cfg = desc->chip_data;
204
205 return cfg;
206 }
207
208 static struct irq_cfg *get_one_free_irq_cfg(int node)
209 {
210 struct irq_cfg *cfg;
211
212 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
213 if (cfg) {
214 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
215 kfree(cfg);
216 cfg = NULL;
217 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
218 GFP_ATOMIC, node)) {
219 free_cpumask_var(cfg->domain);
220 kfree(cfg);
221 cfg = NULL;
222 } else {
223 cpumask_clear(cfg->domain);
224 cpumask_clear(cfg->old_domain);
225 }
226 }
227
228 return cfg;
229 }
230
231 int arch_init_chip_data(struct irq_desc *desc, int node)
232 {
233 struct irq_cfg *cfg;
234
235 cfg = desc->chip_data;
236 if (!cfg) {
237 desc->chip_data = get_one_free_irq_cfg(node);
238 if (!desc->chip_data) {
239 printk(KERN_ERR "can not alloc irq_cfg\n");
240 BUG_ON(1);
241 }
242 }
243
244 return 0;
245 }
246
247 /* for move_irq_desc */
248 static void
249 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
250 {
251 struct irq_pin_list *old_entry, *head, *tail, *entry;
252
253 cfg->irq_2_pin = NULL;
254 old_entry = old_cfg->irq_2_pin;
255 if (!old_entry)
256 return;
257
258 entry = get_one_free_irq_2_pin(node);
259 if (!entry)
260 return;
261
262 entry->apic = old_entry->apic;
263 entry->pin = old_entry->pin;
264 head = entry;
265 tail = entry;
266 old_entry = old_entry->next;
267 while (old_entry) {
268 entry = get_one_free_irq_2_pin(node);
269 if (!entry) {
270 entry = head;
271 while (entry) {
272 head = entry->next;
273 kfree(entry);
274 entry = head;
275 }
276 /* still use the old one */
277 return;
278 }
279 entry->apic = old_entry->apic;
280 entry->pin = old_entry->pin;
281 tail->next = entry;
282 tail = entry;
283 old_entry = old_entry->next;
284 }
285
286 tail->next = NULL;
287 cfg->irq_2_pin = head;
288 }
289
290 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
291 {
292 struct irq_pin_list *entry, *next;
293
294 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
295 return;
296
297 entry = old_cfg->irq_2_pin;
298
299 while (entry) {
300 next = entry->next;
301 kfree(entry);
302 entry = next;
303 }
304 old_cfg->irq_2_pin = NULL;
305 }
306
307 void arch_init_copy_chip_data(struct irq_desc *old_desc,
308 struct irq_desc *desc, int node)
309 {
310 struct irq_cfg *cfg;
311 struct irq_cfg *old_cfg;
312
313 cfg = get_one_free_irq_cfg(node);
314
315 if (!cfg)
316 return;
317
318 desc->chip_data = cfg;
319
320 old_cfg = old_desc->chip_data;
321
322 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
323
324 init_copy_irq_2_pin(old_cfg, cfg, node);
325 }
326
327 static void free_irq_cfg(struct irq_cfg *old_cfg)
328 {
329 kfree(old_cfg);
330 }
331
332 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
333 {
334 struct irq_cfg *old_cfg, *cfg;
335
336 old_cfg = old_desc->chip_data;
337 cfg = desc->chip_data;
338
339 if (old_cfg == cfg)
340 return;
341
342 if (old_cfg) {
343 free_irq_2_pin(old_cfg, cfg);
344 free_irq_cfg(old_cfg);
345 old_desc->chip_data = NULL;
346 }
347 }
348 /* end for move_irq_desc */
349
350 #else
351 static struct irq_cfg *irq_cfg(unsigned int irq)
352 {
353 return irq < nr_irqs ? irq_cfgx + irq : NULL;
354 }
355
356 #endif
357
358 struct io_apic {
359 unsigned int index;
360 unsigned int unused[3];
361 unsigned int data;
362 unsigned int unused2[11];
363 unsigned int eoi;
364 };
365
366 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
367 {
368 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
369 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
370 }
371
372 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
373 {
374 struct io_apic __iomem *io_apic = io_apic_base(apic);
375 writel(vector, &io_apic->eoi);
376 }
377
378 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
379 {
380 struct io_apic __iomem *io_apic = io_apic_base(apic);
381 writel(reg, &io_apic->index);
382 return readl(&io_apic->data);
383 }
384
385 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
386 {
387 struct io_apic __iomem *io_apic = io_apic_base(apic);
388 writel(reg, &io_apic->index);
389 writel(value, &io_apic->data);
390 }
391
392 /*
393 * Re-write a value: to be used for read-modify-write
394 * cycles where the read already set up the index register.
395 *
396 * Older SiS APIC requires we rewrite the index register
397 */
398 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
399 {
400 struct io_apic __iomem *io_apic = io_apic_base(apic);
401
402 if (sis_apic_bug)
403 writel(reg, &io_apic->index);
404 writel(value, &io_apic->data);
405 }
406
407 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
408 {
409 struct irq_pin_list *entry;
410 unsigned long flags;
411
412 spin_lock_irqsave(&ioapic_lock, flags);
413 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
414 unsigned int reg;
415 int pin;
416
417 pin = entry->pin;
418 reg = io_apic_read(entry->apic, 0x10 + pin*2);
419 /* Is the remote IRR bit set? */
420 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
421 spin_unlock_irqrestore(&ioapic_lock, flags);
422 return true;
423 }
424 }
425 spin_unlock_irqrestore(&ioapic_lock, flags);
426
427 return false;
428 }
429
430 union entry_union {
431 struct { u32 w1, w2; };
432 struct IO_APIC_route_entry entry;
433 };
434
435 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
436 {
437 union entry_union eu;
438 unsigned long flags;
439 spin_lock_irqsave(&ioapic_lock, flags);
440 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
441 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
442 spin_unlock_irqrestore(&ioapic_lock, flags);
443 return eu.entry;
444 }
445
446 /*
447 * When we write a new IO APIC routing entry, we need to write the high
448 * word first! If the mask bit in the low word is clear, we will enable
449 * the interrupt, and we need to make sure the entry is fully populated
450 * before that happens.
451 */
452 static void
453 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
454 {
455 union entry_union eu = {{0, 0}};
456
457 eu.entry = e;
458 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
459 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
460 }
461
462 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
463 {
464 unsigned long flags;
465 spin_lock_irqsave(&ioapic_lock, flags);
466 __ioapic_write_entry(apic, pin, e);
467 spin_unlock_irqrestore(&ioapic_lock, flags);
468 }
469
470 /*
471 * When we mask an IO APIC routing entry, we need to write the low
472 * word first, in order to set the mask bit before we change the
473 * high bits!
474 */
475 static void ioapic_mask_entry(int apic, int pin)
476 {
477 unsigned long flags;
478 union entry_union eu = { .entry.mask = 1 };
479
480 spin_lock_irqsave(&ioapic_lock, flags);
481 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
482 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
483 spin_unlock_irqrestore(&ioapic_lock, flags);
484 }
485
486 /*
487 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
488 * shared ISA-space IRQs, so we have to support them. We are super
489 * fast in the common case, and fast for shared ISA-space IRQs.
490 */
491 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
492 {
493 struct irq_pin_list **entryp, *entry;
494
495 for (entryp = &cfg->irq_2_pin;
496 *entryp != NULL;
497 entryp = &(*entryp)->next) {
498 entry = *entryp;
499 /* not again, please */
500 if (entry->apic == apic && entry->pin == pin)
501 return;
502 }
503
504 entry = get_one_free_irq_2_pin(node);
505 entry->apic = apic;
506 entry->pin = pin;
507
508 *entryp = entry;
509 }
510
511 /*
512 * Reroute an IRQ to a different pin.
513 */
514 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
515 int oldapic, int oldpin,
516 int newapic, int newpin)
517 {
518 struct irq_pin_list *entry;
519
520 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
521 if (entry->apic == oldapic && entry->pin == oldpin) {
522 entry->apic = newapic;
523 entry->pin = newpin;
524 /* every one is different, right? */
525 return;
526 }
527 }
528
529 /* old apic/pin didn't exist, so just add new ones */
530 add_pin_to_irq_node(cfg, node, newapic, newpin);
531 }
532
533 static void io_apic_modify_irq(struct irq_cfg *cfg,
534 int mask_and, int mask_or,
535 void (*final)(struct irq_pin_list *entry))
536 {
537 int pin;
538 struct irq_pin_list *entry;
539
540 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
541 unsigned int reg;
542 pin = entry->pin;
543 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
544 reg &= mask_and;
545 reg |= mask_or;
546 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
547 if (final)
548 final(entry);
549 }
550 }
551
552 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
553 {
554 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
555 }
556
557 static void io_apic_sync(struct irq_pin_list *entry)
558 {
559 /*
560 * Synchronize the IO-APIC and the CPU by doing
561 * a dummy read from the IO-APIC
562 */
563 struct io_apic __iomem *io_apic;
564 io_apic = io_apic_base(entry->apic);
565 readl(&io_apic->data);
566 }
567
568 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
569 {
570 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
571 }
572
573 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
574 {
575 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
576 IO_APIC_REDIR_MASKED, NULL);
577 }
578
579 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
580 {
581 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
582 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
583 }
584
585 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
586 {
587 struct irq_cfg *cfg = desc->chip_data;
588 unsigned long flags;
589
590 BUG_ON(!cfg);
591
592 spin_lock_irqsave(&ioapic_lock, flags);
593 __mask_IO_APIC_irq(cfg);
594 spin_unlock_irqrestore(&ioapic_lock, flags);
595 }
596
597 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
598 {
599 struct irq_cfg *cfg = desc->chip_data;
600 unsigned long flags;
601
602 spin_lock_irqsave(&ioapic_lock, flags);
603 __unmask_IO_APIC_irq(cfg);
604 spin_unlock_irqrestore(&ioapic_lock, flags);
605 }
606
607 static void mask_IO_APIC_irq(unsigned int irq)
608 {
609 struct irq_desc *desc = irq_to_desc(irq);
610
611 mask_IO_APIC_irq_desc(desc);
612 }
613 static void unmask_IO_APIC_irq(unsigned int irq)
614 {
615 struct irq_desc *desc = irq_to_desc(irq);
616
617 unmask_IO_APIC_irq_desc(desc);
618 }
619
620 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
621 {
622 struct IO_APIC_route_entry entry;
623
624 /* Check delivery_mode to be sure we're not clearing an SMI pin */
625 entry = ioapic_read_entry(apic, pin);
626 if (entry.delivery_mode == dest_SMI)
627 return;
628 /*
629 * Disable it in the IO-APIC irq-routing table:
630 */
631 ioapic_mask_entry(apic, pin);
632 }
633
634 static void clear_IO_APIC (void)
635 {
636 int apic, pin;
637
638 for (apic = 0; apic < nr_ioapics; apic++)
639 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
640 clear_IO_APIC_pin(apic, pin);
641 }
642
643 #ifdef CONFIG_X86_32
644 /*
645 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
646 * specific CPU-side IRQs.
647 */
648
649 #define MAX_PIRQS 8
650 static int pirq_entries[MAX_PIRQS] = {
651 [0 ... MAX_PIRQS - 1] = -1
652 };
653
654 static int __init ioapic_pirq_setup(char *str)
655 {
656 int i, max;
657 int ints[MAX_PIRQS+1];
658
659 get_options(str, ARRAY_SIZE(ints), ints);
660
661 apic_printk(APIC_VERBOSE, KERN_INFO
662 "PIRQ redirection, working around broken MP-BIOS.\n");
663 max = MAX_PIRQS;
664 if (ints[0] < MAX_PIRQS)
665 max = ints[0];
666
667 for (i = 0; i < max; i++) {
668 apic_printk(APIC_VERBOSE, KERN_DEBUG
669 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
670 /*
671 * PIRQs are mapped upside down, usually.
672 */
673 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
674 }
675 return 1;
676 }
677
678 __setup("pirq=", ioapic_pirq_setup);
679 #endif /* CONFIG_X86_32 */
680
681 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
682 {
683 int apic;
684 struct IO_APIC_route_entry **ioapic_entries;
685
686 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
687 GFP_ATOMIC);
688 if (!ioapic_entries)
689 return 0;
690
691 for (apic = 0; apic < nr_ioapics; apic++) {
692 ioapic_entries[apic] =
693 kzalloc(sizeof(struct IO_APIC_route_entry) *
694 nr_ioapic_registers[apic], GFP_ATOMIC);
695 if (!ioapic_entries[apic])
696 goto nomem;
697 }
698
699 return ioapic_entries;
700
701 nomem:
702 while (--apic >= 0)
703 kfree(ioapic_entries[apic]);
704 kfree(ioapic_entries);
705
706 return 0;
707 }
708
709 /*
710 * Saves all the IO-APIC RTE's
711 */
712 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
713 {
714 int apic, pin;
715
716 if (!ioapic_entries)
717 return -ENOMEM;
718
719 for (apic = 0; apic < nr_ioapics; apic++) {
720 if (!ioapic_entries[apic])
721 return -ENOMEM;
722
723 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
724 ioapic_entries[apic][pin] =
725 ioapic_read_entry(apic, pin);
726 }
727
728 return 0;
729 }
730
731 /*
732 * Mask all IO APIC entries.
733 */
734 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
735 {
736 int apic, pin;
737
738 if (!ioapic_entries)
739 return;
740
741 for (apic = 0; apic < nr_ioapics; apic++) {
742 if (!ioapic_entries[apic])
743 break;
744
745 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
746 struct IO_APIC_route_entry entry;
747
748 entry = ioapic_entries[apic][pin];
749 if (!entry.mask) {
750 entry.mask = 1;
751 ioapic_write_entry(apic, pin, entry);
752 }
753 }
754 }
755 }
756
757 /*
758 * Restore IO APIC entries which was saved in ioapic_entries.
759 */
760 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
761 {
762 int apic, pin;
763
764 if (!ioapic_entries)
765 return -ENOMEM;
766
767 for (apic = 0; apic < nr_ioapics; apic++) {
768 if (!ioapic_entries[apic])
769 return -ENOMEM;
770
771 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
772 ioapic_write_entry(apic, pin,
773 ioapic_entries[apic][pin]);
774 }
775 return 0;
776 }
777
778 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
779 {
780 int apic;
781
782 for (apic = 0; apic < nr_ioapics; apic++)
783 kfree(ioapic_entries[apic]);
784
785 kfree(ioapic_entries);
786 }
787
788 /*
789 * Find the IRQ entry number of a certain pin.
790 */
791 static int find_irq_entry(int apic, int pin, int type)
792 {
793 int i;
794
795 for (i = 0; i < mp_irq_entries; i++)
796 if (mp_irqs[i].irqtype == type &&
797 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
798 mp_irqs[i].dstapic == MP_APIC_ALL) &&
799 mp_irqs[i].dstirq == pin)
800 return i;
801
802 return -1;
803 }
804
805 /*
806 * Find the pin to which IRQ[irq] (ISA) is connected
807 */
808 static int __init find_isa_irq_pin(int irq, int type)
809 {
810 int i;
811
812 for (i = 0; i < mp_irq_entries; i++) {
813 int lbus = mp_irqs[i].srcbus;
814
815 if (test_bit(lbus, mp_bus_not_pci) &&
816 (mp_irqs[i].irqtype == type) &&
817 (mp_irqs[i].srcbusirq == irq))
818
819 return mp_irqs[i].dstirq;
820 }
821 return -1;
822 }
823
824 static int __init find_isa_irq_apic(int irq, int type)
825 {
826 int i;
827
828 for (i = 0; i < mp_irq_entries; i++) {
829 int lbus = mp_irqs[i].srcbus;
830
831 if (test_bit(lbus, mp_bus_not_pci) &&
832 (mp_irqs[i].irqtype == type) &&
833 (mp_irqs[i].srcbusirq == irq))
834 break;
835 }
836 if (i < mp_irq_entries) {
837 int apic;
838 for(apic = 0; apic < nr_ioapics; apic++) {
839 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
840 return apic;
841 }
842 }
843
844 return -1;
845 }
846
847 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
848 /*
849 * EISA Edge/Level control register, ELCR
850 */
851 static int EISA_ELCR(unsigned int irq)
852 {
853 if (irq < NR_IRQS_LEGACY) {
854 unsigned int port = 0x4d0 + (irq >> 3);
855 return (inb(port) >> (irq & 7)) & 1;
856 }
857 apic_printk(APIC_VERBOSE, KERN_INFO
858 "Broken MPtable reports ISA irq %d\n", irq);
859 return 0;
860 }
861
862 #endif
863
864 /* ISA interrupts are always polarity zero edge triggered,
865 * when listed as conforming in the MP table. */
866
867 #define default_ISA_trigger(idx) (0)
868 #define default_ISA_polarity(idx) (0)
869
870 /* EISA interrupts are always polarity zero and can be edge or level
871 * trigger depending on the ELCR value. If an interrupt is listed as
872 * EISA conforming in the MP table, that means its trigger type must
873 * be read in from the ELCR */
874
875 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
876 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
877
878 /* PCI interrupts are always polarity one level triggered,
879 * when listed as conforming in the MP table. */
880
881 #define default_PCI_trigger(idx) (1)
882 #define default_PCI_polarity(idx) (1)
883
884 /* MCA interrupts are always polarity zero level triggered,
885 * when listed as conforming in the MP table. */
886
887 #define default_MCA_trigger(idx) (1)
888 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
889
890 static int MPBIOS_polarity(int idx)
891 {
892 int bus = mp_irqs[idx].srcbus;
893 int polarity;
894
895 /*
896 * Determine IRQ line polarity (high active or low active):
897 */
898 switch (mp_irqs[idx].irqflag & 3)
899 {
900 case 0: /* conforms, ie. bus-type dependent polarity */
901 if (test_bit(bus, mp_bus_not_pci))
902 polarity = default_ISA_polarity(idx);
903 else
904 polarity = default_PCI_polarity(idx);
905 break;
906 case 1: /* high active */
907 {
908 polarity = 0;
909 break;
910 }
911 case 2: /* reserved */
912 {
913 printk(KERN_WARNING "broken BIOS!!\n");
914 polarity = 1;
915 break;
916 }
917 case 3: /* low active */
918 {
919 polarity = 1;
920 break;
921 }
922 default: /* invalid */
923 {
924 printk(KERN_WARNING "broken BIOS!!\n");
925 polarity = 1;
926 break;
927 }
928 }
929 return polarity;
930 }
931
932 static int MPBIOS_trigger(int idx)
933 {
934 int bus = mp_irqs[idx].srcbus;
935 int trigger;
936
937 /*
938 * Determine IRQ trigger mode (edge or level sensitive):
939 */
940 switch ((mp_irqs[idx].irqflag>>2) & 3)
941 {
942 case 0: /* conforms, ie. bus-type dependent */
943 if (test_bit(bus, mp_bus_not_pci))
944 trigger = default_ISA_trigger(idx);
945 else
946 trigger = default_PCI_trigger(idx);
947 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
948 switch (mp_bus_id_to_type[bus]) {
949 case MP_BUS_ISA: /* ISA pin */
950 {
951 /* set before the switch */
952 break;
953 }
954 case MP_BUS_EISA: /* EISA pin */
955 {
956 trigger = default_EISA_trigger(idx);
957 break;
958 }
959 case MP_BUS_PCI: /* PCI pin */
960 {
961 /* set before the switch */
962 break;
963 }
964 case MP_BUS_MCA: /* MCA pin */
965 {
966 trigger = default_MCA_trigger(idx);
967 break;
968 }
969 default:
970 {
971 printk(KERN_WARNING "broken BIOS!!\n");
972 trigger = 1;
973 break;
974 }
975 }
976 #endif
977 break;
978 case 1: /* edge */
979 {
980 trigger = 0;
981 break;
982 }
983 case 2: /* reserved */
984 {
985 printk(KERN_WARNING "broken BIOS!!\n");
986 trigger = 1;
987 break;
988 }
989 case 3: /* level */
990 {
991 trigger = 1;
992 break;
993 }
994 default: /* invalid */
995 {
996 printk(KERN_WARNING "broken BIOS!!\n");
997 trigger = 0;
998 break;
999 }
1000 }
1001 return trigger;
1002 }
1003
1004 static inline int irq_polarity(int idx)
1005 {
1006 return MPBIOS_polarity(idx);
1007 }
1008
1009 static inline int irq_trigger(int idx)
1010 {
1011 return MPBIOS_trigger(idx);
1012 }
1013
1014 int (*ioapic_renumber_irq)(int ioapic, int irq);
1015 static int pin_2_irq(int idx, int apic, int pin)
1016 {
1017 int irq, i;
1018 int bus = mp_irqs[idx].srcbus;
1019
1020 /*
1021 * Debugging check, we are in big trouble if this message pops up!
1022 */
1023 if (mp_irqs[idx].dstirq != pin)
1024 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1025
1026 if (test_bit(bus, mp_bus_not_pci)) {
1027 irq = mp_irqs[idx].srcbusirq;
1028 } else {
1029 /*
1030 * PCI IRQs are mapped in order
1031 */
1032 i = irq = 0;
1033 while (i < apic)
1034 irq += nr_ioapic_registers[i++];
1035 irq += pin;
1036 /*
1037 * For MPS mode, so far only needed by ES7000 platform
1038 */
1039 if (ioapic_renumber_irq)
1040 irq = ioapic_renumber_irq(apic, irq);
1041 }
1042
1043 #ifdef CONFIG_X86_32
1044 /*
1045 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1046 */
1047 if ((pin >= 16) && (pin <= 23)) {
1048 if (pirq_entries[pin-16] != -1) {
1049 if (!pirq_entries[pin-16]) {
1050 apic_printk(APIC_VERBOSE, KERN_DEBUG
1051 "disabling PIRQ%d\n", pin-16);
1052 } else {
1053 irq = pirq_entries[pin-16];
1054 apic_printk(APIC_VERBOSE, KERN_DEBUG
1055 "using PIRQ%d -> IRQ %d\n",
1056 pin-16, irq);
1057 }
1058 }
1059 }
1060 #endif
1061
1062 return irq;
1063 }
1064
1065 /*
1066 * Find a specific PCI IRQ entry.
1067 * Not an __init, possibly needed by modules
1068 */
1069 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1070 struct io_apic_irq_attr *irq_attr)
1071 {
1072 int apic, i, best_guess = -1;
1073
1074 apic_printk(APIC_DEBUG,
1075 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1076 bus, slot, pin);
1077 if (test_bit(bus, mp_bus_not_pci)) {
1078 apic_printk(APIC_VERBOSE,
1079 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1080 return -1;
1081 }
1082 for (i = 0; i < mp_irq_entries; i++) {
1083 int lbus = mp_irqs[i].srcbus;
1084
1085 for (apic = 0; apic < nr_ioapics; apic++)
1086 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1087 mp_irqs[i].dstapic == MP_APIC_ALL)
1088 break;
1089
1090 if (!test_bit(lbus, mp_bus_not_pci) &&
1091 !mp_irqs[i].irqtype &&
1092 (bus == lbus) &&
1093 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1094 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1095
1096 if (!(apic || IO_APIC_IRQ(irq)))
1097 continue;
1098
1099 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1100 set_io_apic_irq_attr(irq_attr, apic,
1101 mp_irqs[i].dstirq,
1102 irq_trigger(i),
1103 irq_polarity(i));
1104 return irq;
1105 }
1106 /*
1107 * Use the first all-but-pin matching entry as a
1108 * best-guess fuzzy result for broken mptables.
1109 */
1110 if (best_guess < 0) {
1111 set_io_apic_irq_attr(irq_attr, apic,
1112 mp_irqs[i].dstirq,
1113 irq_trigger(i),
1114 irq_polarity(i));
1115 best_guess = irq;
1116 }
1117 }
1118 }
1119 return best_guess;
1120 }
1121 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1122
1123 void lock_vector_lock(void)
1124 {
1125 /* Used to the online set of cpus does not change
1126 * during assign_irq_vector.
1127 */
1128 spin_lock(&vector_lock);
1129 }
1130
1131 void unlock_vector_lock(void)
1132 {
1133 spin_unlock(&vector_lock);
1134 }
1135
1136 static int
1137 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1138 {
1139 /*
1140 * NOTE! The local APIC isn't very good at handling
1141 * multiple interrupts at the same interrupt level.
1142 * As the interrupt level is determined by taking the
1143 * vector number and shifting that right by 4, we
1144 * want to spread these out a bit so that they don't
1145 * all fall in the same interrupt level.
1146 *
1147 * Also, we've got to be careful not to trash gate
1148 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1149 */
1150 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1151 unsigned int old_vector;
1152 int cpu, err;
1153 cpumask_var_t tmp_mask;
1154
1155 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1156 return -EBUSY;
1157
1158 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1159 return -ENOMEM;
1160
1161 old_vector = cfg->vector;
1162 if (old_vector) {
1163 cpumask_and(tmp_mask, mask, cpu_online_mask);
1164 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1165 if (!cpumask_empty(tmp_mask)) {
1166 free_cpumask_var(tmp_mask);
1167 return 0;
1168 }
1169 }
1170
1171 /* Only try and allocate irqs on cpus that are present */
1172 err = -ENOSPC;
1173 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1174 int new_cpu;
1175 int vector, offset;
1176
1177 apic->vector_allocation_domain(cpu, tmp_mask);
1178
1179 vector = current_vector;
1180 offset = current_offset;
1181 next:
1182 vector += 8;
1183 if (vector >= first_system_vector) {
1184 /* If out of vectors on large boxen, must share them. */
1185 offset = (offset + 1) % 8;
1186 vector = FIRST_DEVICE_VECTOR + offset;
1187 }
1188 if (unlikely(current_vector == vector))
1189 continue;
1190
1191 if (test_bit(vector, used_vectors))
1192 goto next;
1193
1194 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1195 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1196 goto next;
1197 /* Found one! */
1198 current_vector = vector;
1199 current_offset = offset;
1200 if (old_vector) {
1201 cfg->move_in_progress = 1;
1202 cpumask_copy(cfg->old_domain, cfg->domain);
1203 }
1204 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1205 per_cpu(vector_irq, new_cpu)[vector] = irq;
1206 cfg->vector = vector;
1207 cpumask_copy(cfg->domain, tmp_mask);
1208 err = 0;
1209 break;
1210 }
1211 free_cpumask_var(tmp_mask);
1212 return err;
1213 }
1214
1215 static int
1216 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1217 {
1218 int err;
1219 unsigned long flags;
1220
1221 spin_lock_irqsave(&vector_lock, flags);
1222 err = __assign_irq_vector(irq, cfg, mask);
1223 spin_unlock_irqrestore(&vector_lock, flags);
1224 return err;
1225 }
1226
1227 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1228 {
1229 int cpu, vector;
1230
1231 BUG_ON(!cfg->vector);
1232
1233 vector = cfg->vector;
1234 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1235 per_cpu(vector_irq, cpu)[vector] = -1;
1236
1237 cfg->vector = 0;
1238 cpumask_clear(cfg->domain);
1239
1240 if (likely(!cfg->move_in_progress))
1241 return;
1242 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1243 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1244 vector++) {
1245 if (per_cpu(vector_irq, cpu)[vector] != irq)
1246 continue;
1247 per_cpu(vector_irq, cpu)[vector] = -1;
1248 break;
1249 }
1250 }
1251 cfg->move_in_progress = 0;
1252 }
1253
1254 void __setup_vector_irq(int cpu)
1255 {
1256 /* Initialize vector_irq on a new cpu */
1257 /* This function must be called with vector_lock held */
1258 int irq, vector;
1259 struct irq_cfg *cfg;
1260 struct irq_desc *desc;
1261
1262 /* Mark the inuse vectors */
1263 for_each_irq_desc(irq, desc) {
1264 cfg = desc->chip_data;
1265 if (!cpumask_test_cpu(cpu, cfg->domain))
1266 continue;
1267 vector = cfg->vector;
1268 per_cpu(vector_irq, cpu)[vector] = irq;
1269 }
1270 /* Mark the free vectors */
1271 for (vector = 0; vector < NR_VECTORS; ++vector) {
1272 irq = per_cpu(vector_irq, cpu)[vector];
1273 if (irq < 0)
1274 continue;
1275
1276 cfg = irq_cfg(irq);
1277 if (!cpumask_test_cpu(cpu, cfg->domain))
1278 per_cpu(vector_irq, cpu)[vector] = -1;
1279 }
1280 }
1281
1282 static struct irq_chip ioapic_chip;
1283 static struct irq_chip ir_ioapic_chip;
1284
1285 #define IOAPIC_AUTO -1
1286 #define IOAPIC_EDGE 0
1287 #define IOAPIC_LEVEL 1
1288
1289 #ifdef CONFIG_X86_32
1290 static inline int IO_APIC_irq_trigger(int irq)
1291 {
1292 int apic, idx, pin;
1293
1294 for (apic = 0; apic < nr_ioapics; apic++) {
1295 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1296 idx = find_irq_entry(apic, pin, mp_INT);
1297 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1298 return irq_trigger(idx);
1299 }
1300 }
1301 /*
1302 * nonexistent IRQs are edge default
1303 */
1304 return 0;
1305 }
1306 #else
1307 static inline int IO_APIC_irq_trigger(int irq)
1308 {
1309 return 1;
1310 }
1311 #endif
1312
1313 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1314 {
1315
1316 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1317 trigger == IOAPIC_LEVEL)
1318 desc->status |= IRQ_LEVEL;
1319 else
1320 desc->status &= ~IRQ_LEVEL;
1321
1322 if (irq_remapped(irq)) {
1323 desc->status |= IRQ_MOVE_PCNTXT;
1324 if (trigger)
1325 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1326 handle_fasteoi_irq,
1327 "fasteoi");
1328 else
1329 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1330 handle_edge_irq, "edge");
1331 return;
1332 }
1333
1334 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1335 trigger == IOAPIC_LEVEL)
1336 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1337 handle_fasteoi_irq,
1338 "fasteoi");
1339 else
1340 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1341 handle_edge_irq, "edge");
1342 }
1343
1344 int setup_ioapic_entry(int apic_id, int irq,
1345 struct IO_APIC_route_entry *entry,
1346 unsigned int destination, int trigger,
1347 int polarity, int vector, int pin)
1348 {
1349 /*
1350 * add it to the IO-APIC irq-routing table:
1351 */
1352 memset(entry,0,sizeof(*entry));
1353
1354 if (intr_remapping_enabled) {
1355 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1356 struct irte irte;
1357 struct IR_IO_APIC_route_entry *ir_entry =
1358 (struct IR_IO_APIC_route_entry *) entry;
1359 int index;
1360
1361 if (!iommu)
1362 panic("No mapping iommu for ioapic %d\n", apic_id);
1363
1364 index = alloc_irte(iommu, irq, 1);
1365 if (index < 0)
1366 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1367
1368 memset(&irte, 0, sizeof(irte));
1369
1370 irte.present = 1;
1371 irte.dst_mode = apic->irq_dest_mode;
1372 /*
1373 * Trigger mode in the IRTE will always be edge, and the
1374 * actual level or edge trigger will be setup in the IO-APIC
1375 * RTE. This will help simplify level triggered irq migration.
1376 * For more details, see the comments above explainig IO-APIC
1377 * irq migration in the presence of interrupt-remapping.
1378 */
1379 irte.trigger_mode = 0;
1380 irte.dlvry_mode = apic->irq_delivery_mode;
1381 irte.vector = vector;
1382 irte.dest_id = IRTE_DEST(destination);
1383
1384 /* Set source-id of interrupt request */
1385 set_ioapic_sid(&irte, apic_id);
1386
1387 modify_irte(irq, &irte);
1388
1389 ir_entry->index2 = (index >> 15) & 0x1;
1390 ir_entry->zero = 0;
1391 ir_entry->format = 1;
1392 ir_entry->index = (index & 0x7fff);
1393 /*
1394 * IO-APIC RTE will be configured with virtual vector.
1395 * irq handler will do the explicit EOI to the io-apic.
1396 */
1397 ir_entry->vector = pin;
1398 } else {
1399 entry->delivery_mode = apic->irq_delivery_mode;
1400 entry->dest_mode = apic->irq_dest_mode;
1401 entry->dest = destination;
1402 entry->vector = vector;
1403 }
1404
1405 entry->mask = 0; /* enable IRQ */
1406 entry->trigger = trigger;
1407 entry->polarity = polarity;
1408
1409 /* Mask level triggered irqs.
1410 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1411 */
1412 if (trigger)
1413 entry->mask = 1;
1414 return 0;
1415 }
1416
1417 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1418 int trigger, int polarity)
1419 {
1420 struct irq_cfg *cfg;
1421 struct IO_APIC_route_entry entry;
1422 unsigned int dest;
1423
1424 if (!IO_APIC_IRQ(irq))
1425 return;
1426
1427 cfg = desc->chip_data;
1428
1429 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1430 return;
1431
1432 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1433
1434 apic_printk(APIC_VERBOSE,KERN_DEBUG
1435 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1436 "IRQ %d Mode:%i Active:%i)\n",
1437 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1438 irq, trigger, polarity);
1439
1440
1441 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1442 dest, trigger, polarity, cfg->vector, pin)) {
1443 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1444 mp_ioapics[apic_id].apicid, pin);
1445 __clear_irq_vector(irq, cfg);
1446 return;
1447 }
1448
1449 ioapic_register_intr(irq, desc, trigger);
1450 if (irq < NR_IRQS_LEGACY)
1451 disable_8259A_irq(irq);
1452
1453 ioapic_write_entry(apic_id, pin, entry);
1454 }
1455
1456 static struct {
1457 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1458 } mp_ioapic_routing[MAX_IO_APICS];
1459
1460 static void __init setup_IO_APIC_irqs(void)
1461 {
1462 int apic_id = 0, pin, idx, irq;
1463 int notcon = 0;
1464 struct irq_desc *desc;
1465 struct irq_cfg *cfg;
1466 int node = cpu_to_node(boot_cpu_id);
1467
1468 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1469
1470 #ifdef CONFIG_ACPI
1471 if (!acpi_disabled && acpi_ioapic) {
1472 apic_id = mp_find_ioapic(0);
1473 if (apic_id < 0)
1474 apic_id = 0;
1475 }
1476 #endif
1477
1478 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1479 idx = find_irq_entry(apic_id, pin, mp_INT);
1480 if (idx == -1) {
1481 if (!notcon) {
1482 notcon = 1;
1483 apic_printk(APIC_VERBOSE,
1484 KERN_DEBUG " %d-%d",
1485 mp_ioapics[apic_id].apicid, pin);
1486 } else
1487 apic_printk(APIC_VERBOSE, " %d-%d",
1488 mp_ioapics[apic_id].apicid, pin);
1489 continue;
1490 }
1491 if (notcon) {
1492 apic_printk(APIC_VERBOSE,
1493 " (apicid-pin) not connected\n");
1494 notcon = 0;
1495 }
1496
1497 irq = pin_2_irq(idx, apic_id, pin);
1498
1499 /*
1500 * Skip the timer IRQ if there's a quirk handler
1501 * installed and if it returns 1:
1502 */
1503 if (apic->multi_timer_check &&
1504 apic->multi_timer_check(apic_id, irq))
1505 continue;
1506
1507 desc = irq_to_desc_alloc_node(irq, node);
1508 if (!desc) {
1509 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1510 continue;
1511 }
1512 cfg = desc->chip_data;
1513 add_pin_to_irq_node(cfg, node, apic_id, pin);
1514 /*
1515 * don't mark it in pin_programmed, so later acpi could
1516 * set it correctly when irq < 16
1517 */
1518 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1519 irq_trigger(idx), irq_polarity(idx));
1520 }
1521
1522 if (notcon)
1523 apic_printk(APIC_VERBOSE,
1524 " (apicid-pin) not connected\n");
1525 }
1526
1527 /*
1528 * Set up the timer pin, possibly with the 8259A-master behind.
1529 */
1530 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1531 int vector)
1532 {
1533 struct IO_APIC_route_entry entry;
1534
1535 if (intr_remapping_enabled)
1536 return;
1537
1538 memset(&entry, 0, sizeof(entry));
1539
1540 /*
1541 * We use logical delivery to get the timer IRQ
1542 * to the first CPU.
1543 */
1544 entry.dest_mode = apic->irq_dest_mode;
1545 entry.mask = 0; /* don't mask IRQ for edge */
1546 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1547 entry.delivery_mode = apic->irq_delivery_mode;
1548 entry.polarity = 0;
1549 entry.trigger = 0;
1550 entry.vector = vector;
1551
1552 /*
1553 * The timer IRQ doesn't have to know that behind the
1554 * scene we may have a 8259A-master in AEOI mode ...
1555 */
1556 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1557
1558 /*
1559 * Add it to the IO-APIC irq-routing table:
1560 */
1561 ioapic_write_entry(apic_id, pin, entry);
1562 }
1563
1564
1565 __apicdebuginit(void) print_IO_APIC(void)
1566 {
1567 int apic, i;
1568 union IO_APIC_reg_00 reg_00;
1569 union IO_APIC_reg_01 reg_01;
1570 union IO_APIC_reg_02 reg_02;
1571 union IO_APIC_reg_03 reg_03;
1572 unsigned long flags;
1573 struct irq_cfg *cfg;
1574 struct irq_desc *desc;
1575 unsigned int irq;
1576
1577 if (apic_verbosity == APIC_QUIET)
1578 return;
1579
1580 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1581 for (i = 0; i < nr_ioapics; i++)
1582 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1583 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1584
1585 /*
1586 * We are a bit conservative about what we expect. We have to
1587 * know about every hardware change ASAP.
1588 */
1589 printk(KERN_INFO "testing the IO APIC.......................\n");
1590
1591 for (apic = 0; apic < nr_ioapics; apic++) {
1592
1593 spin_lock_irqsave(&ioapic_lock, flags);
1594 reg_00.raw = io_apic_read(apic, 0);
1595 reg_01.raw = io_apic_read(apic, 1);
1596 if (reg_01.bits.version >= 0x10)
1597 reg_02.raw = io_apic_read(apic, 2);
1598 if (reg_01.bits.version >= 0x20)
1599 reg_03.raw = io_apic_read(apic, 3);
1600 spin_unlock_irqrestore(&ioapic_lock, flags);
1601
1602 printk("\n");
1603 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1604 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1605 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1606 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1607 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1608
1609 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1610 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1611
1612 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1613 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1614
1615 /*
1616 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1617 * but the value of reg_02 is read as the previous read register
1618 * value, so ignore it if reg_02 == reg_01.
1619 */
1620 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1621 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1622 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1623 }
1624
1625 /*
1626 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1627 * or reg_03, but the value of reg_0[23] is read as the previous read
1628 * register value, so ignore it if reg_03 == reg_0[12].
1629 */
1630 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1631 reg_03.raw != reg_01.raw) {
1632 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1633 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1634 }
1635
1636 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1637
1638 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1639 " Stat Dmod Deli Vect: \n");
1640
1641 for (i = 0; i <= reg_01.bits.entries; i++) {
1642 struct IO_APIC_route_entry entry;
1643
1644 entry = ioapic_read_entry(apic, i);
1645
1646 printk(KERN_DEBUG " %02x %03X ",
1647 i,
1648 entry.dest
1649 );
1650
1651 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1652 entry.mask,
1653 entry.trigger,
1654 entry.irr,
1655 entry.polarity,
1656 entry.delivery_status,
1657 entry.dest_mode,
1658 entry.delivery_mode,
1659 entry.vector
1660 );
1661 }
1662 }
1663 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1664 for_each_irq_desc(irq, desc) {
1665 struct irq_pin_list *entry;
1666
1667 cfg = desc->chip_data;
1668 entry = cfg->irq_2_pin;
1669 if (!entry)
1670 continue;
1671 printk(KERN_DEBUG "IRQ%d ", irq);
1672 for (;;) {
1673 printk("-> %d:%d", entry->apic, entry->pin);
1674 if (!entry->next)
1675 break;
1676 entry = entry->next;
1677 }
1678 printk("\n");
1679 }
1680
1681 printk(KERN_INFO ".................................... done.\n");
1682
1683 return;
1684 }
1685
1686 __apicdebuginit(void) print_APIC_field(int base)
1687 {
1688 int i;
1689
1690 if (apic_verbosity == APIC_QUIET)
1691 return;
1692
1693 printk(KERN_DEBUG);
1694
1695 for (i = 0; i < 8; i++)
1696 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1697
1698 printk(KERN_CONT "\n");
1699 }
1700
1701 __apicdebuginit(void) print_local_APIC(void *dummy)
1702 {
1703 unsigned int i, v, ver, maxlvt;
1704 u64 icr;
1705
1706 if (apic_verbosity == APIC_QUIET)
1707 return;
1708
1709 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1710 smp_processor_id(), hard_smp_processor_id());
1711 v = apic_read(APIC_ID);
1712 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1713 v = apic_read(APIC_LVR);
1714 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1715 ver = GET_APIC_VERSION(v);
1716 maxlvt = lapic_get_maxlvt();
1717
1718 v = apic_read(APIC_TASKPRI);
1719 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1720
1721 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1722 if (!APIC_XAPIC(ver)) {
1723 v = apic_read(APIC_ARBPRI);
1724 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1725 v & APIC_ARBPRI_MASK);
1726 }
1727 v = apic_read(APIC_PROCPRI);
1728 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1729 }
1730
1731 /*
1732 * Remote read supported only in the 82489DX and local APIC for
1733 * Pentium processors.
1734 */
1735 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1736 v = apic_read(APIC_RRR);
1737 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1738 }
1739
1740 v = apic_read(APIC_LDR);
1741 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1742 if (!x2apic_enabled()) {
1743 v = apic_read(APIC_DFR);
1744 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1745 }
1746 v = apic_read(APIC_SPIV);
1747 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1748
1749 printk(KERN_DEBUG "... APIC ISR field:\n");
1750 print_APIC_field(APIC_ISR);
1751 printk(KERN_DEBUG "... APIC TMR field:\n");
1752 print_APIC_field(APIC_TMR);
1753 printk(KERN_DEBUG "... APIC IRR field:\n");
1754 print_APIC_field(APIC_IRR);
1755
1756 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1757 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1758 apic_write(APIC_ESR, 0);
1759
1760 v = apic_read(APIC_ESR);
1761 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1762 }
1763
1764 icr = apic_icr_read();
1765 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1766 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1767
1768 v = apic_read(APIC_LVTT);
1769 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1770
1771 if (maxlvt > 3) { /* PC is LVT#4. */
1772 v = apic_read(APIC_LVTPC);
1773 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1774 }
1775 v = apic_read(APIC_LVT0);
1776 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1777 v = apic_read(APIC_LVT1);
1778 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1779
1780 if (maxlvt > 2) { /* ERR is LVT#3. */
1781 v = apic_read(APIC_LVTERR);
1782 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1783 }
1784
1785 v = apic_read(APIC_TMICT);
1786 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1787 v = apic_read(APIC_TMCCT);
1788 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1789 v = apic_read(APIC_TDCR);
1790 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1791
1792 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1793 v = apic_read(APIC_EFEAT);
1794 maxlvt = (v >> 16) & 0xff;
1795 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1796 v = apic_read(APIC_ECTRL);
1797 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1798 for (i = 0; i < maxlvt; i++) {
1799 v = apic_read(APIC_EILVTn(i));
1800 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1801 }
1802 }
1803 printk("\n");
1804 }
1805
1806 __apicdebuginit(void) print_all_local_APICs(void)
1807 {
1808 int cpu;
1809
1810 preempt_disable();
1811 for_each_online_cpu(cpu)
1812 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1813 preempt_enable();
1814 }
1815
1816 __apicdebuginit(void) print_PIC(void)
1817 {
1818 unsigned int v;
1819 unsigned long flags;
1820
1821 if (apic_verbosity == APIC_QUIET)
1822 return;
1823
1824 printk(KERN_DEBUG "\nprinting PIC contents\n");
1825
1826 spin_lock_irqsave(&i8259A_lock, flags);
1827
1828 v = inb(0xa1) << 8 | inb(0x21);
1829 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1830
1831 v = inb(0xa0) << 8 | inb(0x20);
1832 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1833
1834 outb(0x0b,0xa0);
1835 outb(0x0b,0x20);
1836 v = inb(0xa0) << 8 | inb(0x20);
1837 outb(0x0a,0xa0);
1838 outb(0x0a,0x20);
1839
1840 spin_unlock_irqrestore(&i8259A_lock, flags);
1841
1842 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1843
1844 v = inb(0x4d1) << 8 | inb(0x4d0);
1845 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1846 }
1847
1848 __apicdebuginit(int) print_all_ICs(void)
1849 {
1850 print_PIC();
1851
1852 /* don't print out if apic is not there */
1853 if (!cpu_has_apic || disable_apic)
1854 return 0;
1855
1856 print_all_local_APICs();
1857 print_IO_APIC();
1858
1859 return 0;
1860 }
1861
1862 fs_initcall(print_all_ICs);
1863
1864
1865 /* Where if anywhere is the i8259 connect in external int mode */
1866 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1867
1868 void __init enable_IO_APIC(void)
1869 {
1870 union IO_APIC_reg_01 reg_01;
1871 int i8259_apic, i8259_pin;
1872 int apic;
1873 unsigned long flags;
1874
1875 /*
1876 * The number of IO-APIC IRQ registers (== #pins):
1877 */
1878 for (apic = 0; apic < nr_ioapics; apic++) {
1879 spin_lock_irqsave(&ioapic_lock, flags);
1880 reg_01.raw = io_apic_read(apic, 1);
1881 spin_unlock_irqrestore(&ioapic_lock, flags);
1882 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1883 }
1884 for(apic = 0; apic < nr_ioapics; apic++) {
1885 int pin;
1886 /* See if any of the pins is in ExtINT mode */
1887 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1888 struct IO_APIC_route_entry entry;
1889 entry = ioapic_read_entry(apic, pin);
1890
1891 /* If the interrupt line is enabled and in ExtInt mode
1892 * I have found the pin where the i8259 is connected.
1893 */
1894 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1895 ioapic_i8259.apic = apic;
1896 ioapic_i8259.pin = pin;
1897 goto found_i8259;
1898 }
1899 }
1900 }
1901 found_i8259:
1902 /* Look to see what if the MP table has reported the ExtINT */
1903 /* If we could not find the appropriate pin by looking at the ioapic
1904 * the i8259 probably is not connected the ioapic but give the
1905 * mptable a chance anyway.
1906 */
1907 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1908 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1909 /* Trust the MP table if nothing is setup in the hardware */
1910 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1911 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1912 ioapic_i8259.pin = i8259_pin;
1913 ioapic_i8259.apic = i8259_apic;
1914 }
1915 /* Complain if the MP table and the hardware disagree */
1916 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1917 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1918 {
1919 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1920 }
1921
1922 /*
1923 * Do not trust the IO-APIC being empty at bootup
1924 */
1925 clear_IO_APIC();
1926 }
1927
1928 /*
1929 * Not an __init, needed by the reboot code
1930 */
1931 void disable_IO_APIC(void)
1932 {
1933 /*
1934 * Clear the IO-APIC before rebooting:
1935 */
1936 clear_IO_APIC();
1937
1938 /*
1939 * If the i8259 is routed through an IOAPIC
1940 * Put that IOAPIC in virtual wire mode
1941 * so legacy interrupts can be delivered.
1942 *
1943 * With interrupt-remapping, for now we will use virtual wire A mode,
1944 * as virtual wire B is little complex (need to configure both
1945 * IOAPIC RTE aswell as interrupt-remapping table entry).
1946 * As this gets called during crash dump, keep this simple for now.
1947 */
1948 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1949 struct IO_APIC_route_entry entry;
1950
1951 memset(&entry, 0, sizeof(entry));
1952 entry.mask = 0; /* Enabled */
1953 entry.trigger = 0; /* Edge */
1954 entry.irr = 0;
1955 entry.polarity = 0; /* High */
1956 entry.delivery_status = 0;
1957 entry.dest_mode = 0; /* Physical */
1958 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1959 entry.vector = 0;
1960 entry.dest = read_apic_id();
1961
1962 /*
1963 * Add it to the IO-APIC irq-routing table:
1964 */
1965 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1966 }
1967
1968 /*
1969 * Use virtual wire A mode when interrupt remapping is enabled.
1970 */
1971 if (cpu_has_apic)
1972 disconnect_bsp_APIC(!intr_remapping_enabled &&
1973 ioapic_i8259.pin != -1);
1974 }
1975
1976 #ifdef CONFIG_X86_32
1977 /*
1978 * function to set the IO-APIC physical IDs based on the
1979 * values stored in the MPC table.
1980 *
1981 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1982 */
1983
1984 static void __init setup_ioapic_ids_from_mpc(void)
1985 {
1986 union IO_APIC_reg_00 reg_00;
1987 physid_mask_t phys_id_present_map;
1988 int apic_id;
1989 int i;
1990 unsigned char old_id;
1991 unsigned long flags;
1992
1993 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1994 return;
1995
1996 /*
1997 * Don't check I/O APIC IDs for xAPIC systems. They have
1998 * no meaning without the serial APIC bus.
1999 */
2000 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2001 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2002 return;
2003 /*
2004 * This is broken; anything with a real cpu count has to
2005 * circumvent this idiocy regardless.
2006 */
2007 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2008
2009 /*
2010 * Set the IOAPIC ID to the value stored in the MPC table.
2011 */
2012 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2013
2014 /* Read the register 0 value */
2015 spin_lock_irqsave(&ioapic_lock, flags);
2016 reg_00.raw = io_apic_read(apic_id, 0);
2017 spin_unlock_irqrestore(&ioapic_lock, flags);
2018
2019 old_id = mp_ioapics[apic_id].apicid;
2020
2021 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2022 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2023 apic_id, mp_ioapics[apic_id].apicid);
2024 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2025 reg_00.bits.ID);
2026 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2027 }
2028
2029 /*
2030 * Sanity check, is the ID really free? Every APIC in a
2031 * system must have a unique ID or we get lots of nice
2032 * 'stuck on smp_invalidate_needed IPI wait' messages.
2033 */
2034 if (apic->check_apicid_used(phys_id_present_map,
2035 mp_ioapics[apic_id].apicid)) {
2036 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2037 apic_id, mp_ioapics[apic_id].apicid);
2038 for (i = 0; i < get_physical_broadcast(); i++)
2039 if (!physid_isset(i, phys_id_present_map))
2040 break;
2041 if (i >= get_physical_broadcast())
2042 panic("Max APIC ID exceeded!\n");
2043 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2044 i);
2045 physid_set(i, phys_id_present_map);
2046 mp_ioapics[apic_id].apicid = i;
2047 } else {
2048 physid_mask_t tmp;
2049 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2050 apic_printk(APIC_VERBOSE, "Setting %d in the "
2051 "phys_id_present_map\n",
2052 mp_ioapics[apic_id].apicid);
2053 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2054 }
2055
2056
2057 /*
2058 * We need to adjust the IRQ routing table
2059 * if the ID changed.
2060 */
2061 if (old_id != mp_ioapics[apic_id].apicid)
2062 for (i = 0; i < mp_irq_entries; i++)
2063 if (mp_irqs[i].dstapic == old_id)
2064 mp_irqs[i].dstapic
2065 = mp_ioapics[apic_id].apicid;
2066
2067 /*
2068 * Read the right value from the MPC table and
2069 * write it into the ID register.
2070 */
2071 apic_printk(APIC_VERBOSE, KERN_INFO
2072 "...changing IO-APIC physical APIC ID to %d ...",
2073 mp_ioapics[apic_id].apicid);
2074
2075 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2076 spin_lock_irqsave(&ioapic_lock, flags);
2077 io_apic_write(apic_id, 0, reg_00.raw);
2078 spin_unlock_irqrestore(&ioapic_lock, flags);
2079
2080 /*
2081 * Sanity check
2082 */
2083 spin_lock_irqsave(&ioapic_lock, flags);
2084 reg_00.raw = io_apic_read(apic_id, 0);
2085 spin_unlock_irqrestore(&ioapic_lock, flags);
2086 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2087 printk("could not set ID!\n");
2088 else
2089 apic_printk(APIC_VERBOSE, " ok.\n");
2090 }
2091 }
2092 #endif
2093
2094 int no_timer_check __initdata;
2095
2096 static int __init notimercheck(char *s)
2097 {
2098 no_timer_check = 1;
2099 return 1;
2100 }
2101 __setup("no_timer_check", notimercheck);
2102
2103 /*
2104 * There is a nasty bug in some older SMP boards, their mptable lies
2105 * about the timer IRQ. We do the following to work around the situation:
2106 *
2107 * - timer IRQ defaults to IO-APIC IRQ
2108 * - if this function detects that timer IRQs are defunct, then we fall
2109 * back to ISA timer IRQs
2110 */
2111 static int __init timer_irq_works(void)
2112 {
2113 unsigned long t1 = jiffies;
2114 unsigned long flags;
2115
2116 if (no_timer_check)
2117 return 1;
2118
2119 local_save_flags(flags);
2120 local_irq_enable();
2121 /* Let ten ticks pass... */
2122 mdelay((10 * 1000) / HZ);
2123 local_irq_restore(flags);
2124
2125 /*
2126 * Expect a few ticks at least, to be sure some possible
2127 * glue logic does not lock up after one or two first
2128 * ticks in a non-ExtINT mode. Also the local APIC
2129 * might have cached one ExtINT interrupt. Finally, at
2130 * least one tick may be lost due to delays.
2131 */
2132
2133 /* jiffies wrap? */
2134 if (time_after(jiffies, t1 + 4))
2135 return 1;
2136 return 0;
2137 }
2138
2139 /*
2140 * In the SMP+IOAPIC case it might happen that there are an unspecified
2141 * number of pending IRQ events unhandled. These cases are very rare,
2142 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2143 * better to do it this way as thus we do not have to be aware of
2144 * 'pending' interrupts in the IRQ path, except at this point.
2145 */
2146 /*
2147 * Edge triggered needs to resend any interrupt
2148 * that was delayed but this is now handled in the device
2149 * independent code.
2150 */
2151
2152 /*
2153 * Starting up a edge-triggered IO-APIC interrupt is
2154 * nasty - we need to make sure that we get the edge.
2155 * If it is already asserted for some reason, we need
2156 * return 1 to indicate that is was pending.
2157 *
2158 * This is not complete - we should be able to fake
2159 * an edge even if it isn't on the 8259A...
2160 */
2161
2162 static unsigned int startup_ioapic_irq(unsigned int irq)
2163 {
2164 int was_pending = 0;
2165 unsigned long flags;
2166 struct irq_cfg *cfg;
2167
2168 spin_lock_irqsave(&ioapic_lock, flags);
2169 if (irq < NR_IRQS_LEGACY) {
2170 disable_8259A_irq(irq);
2171 if (i8259A_irq_pending(irq))
2172 was_pending = 1;
2173 }
2174 cfg = irq_cfg(irq);
2175 __unmask_IO_APIC_irq(cfg);
2176 spin_unlock_irqrestore(&ioapic_lock, flags);
2177
2178 return was_pending;
2179 }
2180
2181 #ifdef CONFIG_X86_64
2182 static int ioapic_retrigger_irq(unsigned int irq)
2183 {
2184
2185 struct irq_cfg *cfg = irq_cfg(irq);
2186 unsigned long flags;
2187
2188 spin_lock_irqsave(&vector_lock, flags);
2189 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2190 spin_unlock_irqrestore(&vector_lock, flags);
2191
2192 return 1;
2193 }
2194 #else
2195 static int ioapic_retrigger_irq(unsigned int irq)
2196 {
2197 apic->send_IPI_self(irq_cfg(irq)->vector);
2198
2199 return 1;
2200 }
2201 #endif
2202
2203 /*
2204 * Level and edge triggered IO-APIC interrupts need different handling,
2205 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2206 * handled with the level-triggered descriptor, but that one has slightly
2207 * more overhead. Level-triggered interrupts cannot be handled with the
2208 * edge-triggered handler, without risking IRQ storms and other ugly
2209 * races.
2210 */
2211
2212 #ifdef CONFIG_SMP
2213 static void send_cleanup_vector(struct irq_cfg *cfg)
2214 {
2215 cpumask_var_t cleanup_mask;
2216
2217 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2218 unsigned int i;
2219 cfg->move_cleanup_count = 0;
2220 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2221 cfg->move_cleanup_count++;
2222 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2223 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2224 } else {
2225 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2226 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2227 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2228 free_cpumask_var(cleanup_mask);
2229 }
2230 cfg->move_in_progress = 0;
2231 }
2232
2233 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2234 {
2235 int apic, pin;
2236 struct irq_pin_list *entry;
2237 u8 vector = cfg->vector;
2238
2239 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
2240 unsigned int reg;
2241
2242 apic = entry->apic;
2243 pin = entry->pin;
2244 /*
2245 * With interrupt-remapping, destination information comes
2246 * from interrupt-remapping table entry.
2247 */
2248 if (!irq_remapped(irq))
2249 io_apic_write(apic, 0x11 + pin*2, dest);
2250 reg = io_apic_read(apic, 0x10 + pin*2);
2251 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2252 reg |= vector;
2253 io_apic_modify(apic, 0x10 + pin*2, reg);
2254 }
2255 }
2256
2257 static int
2258 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2259
2260 /*
2261 * Either sets desc->affinity to a valid value, and returns
2262 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2263 * leaves desc->affinity untouched.
2264 */
2265 static unsigned int
2266 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2267 {
2268 struct irq_cfg *cfg;
2269 unsigned int irq;
2270
2271 if (!cpumask_intersects(mask, cpu_online_mask))
2272 return BAD_APICID;
2273
2274 irq = desc->irq;
2275 cfg = desc->chip_data;
2276 if (assign_irq_vector(irq, cfg, mask))
2277 return BAD_APICID;
2278
2279 cpumask_copy(desc->affinity, mask);
2280
2281 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2282 }
2283
2284 static int
2285 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2286 {
2287 struct irq_cfg *cfg;
2288 unsigned long flags;
2289 unsigned int dest;
2290 unsigned int irq;
2291 int ret = -1;
2292
2293 irq = desc->irq;
2294 cfg = desc->chip_data;
2295
2296 spin_lock_irqsave(&ioapic_lock, flags);
2297 dest = set_desc_affinity(desc, mask);
2298 if (dest != BAD_APICID) {
2299 /* Only the high 8 bits are valid. */
2300 dest = SET_APIC_LOGICAL_ID(dest);
2301 __target_IO_APIC_irq(irq, dest, cfg);
2302 ret = 0;
2303 }
2304 spin_unlock_irqrestore(&ioapic_lock, flags);
2305
2306 return ret;
2307 }
2308
2309 static int
2310 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2311 {
2312 struct irq_desc *desc;
2313
2314 desc = irq_to_desc(irq);
2315
2316 return set_ioapic_affinity_irq_desc(desc, mask);
2317 }
2318
2319 #ifdef CONFIG_INTR_REMAP
2320
2321 /*
2322 * Migrate the IO-APIC irq in the presence of intr-remapping.
2323 *
2324 * For both level and edge triggered, irq migration is a simple atomic
2325 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2326 *
2327 * For level triggered, we eliminate the io-apic RTE modification (with the
2328 * updated vector information), by using a virtual vector (io-apic pin number).
2329 * Real vector that is used for interrupting cpu will be coming from
2330 * the interrupt-remapping table entry.
2331 */
2332 static int
2333 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2334 {
2335 struct irq_cfg *cfg;
2336 struct irte irte;
2337 unsigned int dest;
2338 unsigned int irq;
2339 int ret = -1;
2340
2341 if (!cpumask_intersects(mask, cpu_online_mask))
2342 return ret;
2343
2344 irq = desc->irq;
2345 if (get_irte(irq, &irte))
2346 return ret;
2347
2348 cfg = desc->chip_data;
2349 if (assign_irq_vector(irq, cfg, mask))
2350 return ret;
2351
2352 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2353
2354 irte.vector = cfg->vector;
2355 irte.dest_id = IRTE_DEST(dest);
2356
2357 /*
2358 * Modified the IRTE and flushes the Interrupt entry cache.
2359 */
2360 modify_irte(irq, &irte);
2361
2362 if (cfg->move_in_progress)
2363 send_cleanup_vector(cfg);
2364
2365 cpumask_copy(desc->affinity, mask);
2366
2367 return 0;
2368 }
2369
2370 /*
2371 * Migrates the IRQ destination in the process context.
2372 */
2373 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2374 const struct cpumask *mask)
2375 {
2376 return migrate_ioapic_irq_desc(desc, mask);
2377 }
2378 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2379 const struct cpumask *mask)
2380 {
2381 struct irq_desc *desc = irq_to_desc(irq);
2382
2383 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2384 }
2385 #else
2386 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2387 const struct cpumask *mask)
2388 {
2389 return 0;
2390 }
2391 #endif
2392
2393 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2394 {
2395 unsigned vector, me;
2396
2397 ack_APIC_irq();
2398 exit_idle();
2399 irq_enter();
2400
2401 me = smp_processor_id();
2402 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2403 unsigned int irq;
2404 unsigned int irr;
2405 struct irq_desc *desc;
2406 struct irq_cfg *cfg;
2407 irq = __get_cpu_var(vector_irq)[vector];
2408
2409 if (irq == -1)
2410 continue;
2411
2412 desc = irq_to_desc(irq);
2413 if (!desc)
2414 continue;
2415
2416 cfg = irq_cfg(irq);
2417 spin_lock(&desc->lock);
2418 if (!cfg->move_cleanup_count)
2419 goto unlock;
2420
2421 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2422 goto unlock;
2423
2424 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2425 /*
2426 * Check if the vector that needs to be cleanedup is
2427 * registered at the cpu's IRR. If so, then this is not
2428 * the best time to clean it up. Lets clean it up in the
2429 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2430 * to myself.
2431 */
2432 if (irr & (1 << (vector % 32))) {
2433 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2434 goto unlock;
2435 }
2436 __get_cpu_var(vector_irq)[vector] = -1;
2437 cfg->move_cleanup_count--;
2438 unlock:
2439 spin_unlock(&desc->lock);
2440 }
2441
2442 irq_exit();
2443 }
2444
2445 static void irq_complete_move(struct irq_desc **descp)
2446 {
2447 struct irq_desc *desc = *descp;
2448 struct irq_cfg *cfg = desc->chip_data;
2449 unsigned vector, me;
2450
2451 if (likely(!cfg->move_in_progress))
2452 return;
2453
2454 vector = ~get_irq_regs()->orig_ax;
2455 me = smp_processor_id();
2456
2457 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2458 send_cleanup_vector(cfg);
2459 }
2460 #else
2461 static inline void irq_complete_move(struct irq_desc **descp) {}
2462 #endif
2463
2464 static void ack_apic_edge(unsigned int irq)
2465 {
2466 struct irq_desc *desc = irq_to_desc(irq);
2467
2468 irq_complete_move(&desc);
2469 move_native_irq(irq);
2470 ack_APIC_irq();
2471 }
2472
2473 atomic_t irq_mis_count;
2474
2475 static void ack_apic_level(unsigned int irq)
2476 {
2477 struct irq_desc *desc = irq_to_desc(irq);
2478 unsigned long v;
2479 int i;
2480 struct irq_cfg *cfg;
2481 int do_unmask_irq = 0;
2482
2483 irq_complete_move(&desc);
2484 #ifdef CONFIG_GENERIC_PENDING_IRQ
2485 /* If we are moving the irq we need to mask it */
2486 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2487 do_unmask_irq = 1;
2488 mask_IO_APIC_irq_desc(desc);
2489 }
2490 #endif
2491
2492 /*
2493 * It appears there is an erratum which affects at least version 0x11
2494 * of I/O APIC (that's the 82093AA and cores integrated into various
2495 * chipsets). Under certain conditions a level-triggered interrupt is
2496 * erroneously delivered as edge-triggered one but the respective IRR
2497 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2498 * message but it will never arrive and further interrupts are blocked
2499 * from the source. The exact reason is so far unknown, but the
2500 * phenomenon was observed when two consecutive interrupt requests
2501 * from a given source get delivered to the same CPU and the source is
2502 * temporarily disabled in between.
2503 *
2504 * A workaround is to simulate an EOI message manually. We achieve it
2505 * by setting the trigger mode to edge and then to level when the edge
2506 * trigger mode gets detected in the TMR of a local APIC for a
2507 * level-triggered interrupt. We mask the source for the time of the
2508 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2509 * The idea is from Manfred Spraul. --macro
2510 */
2511 cfg = desc->chip_data;
2512 i = cfg->vector;
2513 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2514
2515 /*
2516 * We must acknowledge the irq before we move it or the acknowledge will
2517 * not propagate properly.
2518 */
2519 ack_APIC_irq();
2520
2521 /* Now we can move and renable the irq */
2522 if (unlikely(do_unmask_irq)) {
2523 /* Only migrate the irq if the ack has been received.
2524 *
2525 * On rare occasions the broadcast level triggered ack gets
2526 * delayed going to ioapics, and if we reprogram the
2527 * vector while Remote IRR is still set the irq will never
2528 * fire again.
2529 *
2530 * To prevent this scenario we read the Remote IRR bit
2531 * of the ioapic. This has two effects.
2532 * - On any sane system the read of the ioapic will
2533 * flush writes (and acks) going to the ioapic from
2534 * this cpu.
2535 * - We get to see if the ACK has actually been delivered.
2536 *
2537 * Based on failed experiments of reprogramming the
2538 * ioapic entry from outside of irq context starting
2539 * with masking the ioapic entry and then polling until
2540 * Remote IRR was clear before reprogramming the
2541 * ioapic I don't trust the Remote IRR bit to be
2542 * completey accurate.
2543 *
2544 * However there appears to be no other way to plug
2545 * this race, so if the Remote IRR bit is not
2546 * accurate and is causing problems then it is a hardware bug
2547 * and you can go talk to the chipset vendor about it.
2548 */
2549 cfg = desc->chip_data;
2550 if (!io_apic_level_ack_pending(cfg))
2551 move_masked_irq(irq);
2552 unmask_IO_APIC_irq_desc(desc);
2553 }
2554
2555 /* Tail end of version 0x11 I/O APIC bug workaround */
2556 if (!(v & (1 << (i & 0x1f)))) {
2557 atomic_inc(&irq_mis_count);
2558 spin_lock(&ioapic_lock);
2559 __mask_and_edge_IO_APIC_irq(cfg);
2560 __unmask_and_level_IO_APIC_irq(cfg);
2561 spin_unlock(&ioapic_lock);
2562 }
2563 }
2564
2565 #ifdef CONFIG_INTR_REMAP
2566 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2567 {
2568 int apic, pin;
2569 struct irq_pin_list *entry;
2570
2571 entry = cfg->irq_2_pin;
2572 for (;;) {
2573
2574 if (!entry)
2575 break;
2576
2577 apic = entry->apic;
2578 pin = entry->pin;
2579 io_apic_eoi(apic, pin);
2580 entry = entry->next;
2581 }
2582 }
2583
2584 static void
2585 eoi_ioapic_irq(struct irq_desc *desc)
2586 {
2587 struct irq_cfg *cfg;
2588 unsigned long flags;
2589 unsigned int irq;
2590
2591 irq = desc->irq;
2592 cfg = desc->chip_data;
2593
2594 spin_lock_irqsave(&ioapic_lock, flags);
2595 __eoi_ioapic_irq(irq, cfg);
2596 spin_unlock_irqrestore(&ioapic_lock, flags);
2597 }
2598
2599 static void ir_ack_apic_edge(unsigned int irq)
2600 {
2601 ack_APIC_irq();
2602 }
2603
2604 static void ir_ack_apic_level(unsigned int irq)
2605 {
2606 struct irq_desc *desc = irq_to_desc(irq);
2607
2608 ack_APIC_irq();
2609 eoi_ioapic_irq(desc);
2610 }
2611 #endif /* CONFIG_INTR_REMAP */
2612
2613 static struct irq_chip ioapic_chip __read_mostly = {
2614 .name = "IO-APIC",
2615 .startup = startup_ioapic_irq,
2616 .mask = mask_IO_APIC_irq,
2617 .unmask = unmask_IO_APIC_irq,
2618 .ack = ack_apic_edge,
2619 .eoi = ack_apic_level,
2620 #ifdef CONFIG_SMP
2621 .set_affinity = set_ioapic_affinity_irq,
2622 #endif
2623 .retrigger = ioapic_retrigger_irq,
2624 };
2625
2626 static struct irq_chip ir_ioapic_chip __read_mostly = {
2627 .name = "IR-IO-APIC",
2628 .startup = startup_ioapic_irq,
2629 .mask = mask_IO_APIC_irq,
2630 .unmask = unmask_IO_APIC_irq,
2631 #ifdef CONFIG_INTR_REMAP
2632 .ack = ir_ack_apic_edge,
2633 .eoi = ir_ack_apic_level,
2634 #ifdef CONFIG_SMP
2635 .set_affinity = set_ir_ioapic_affinity_irq,
2636 #endif
2637 #endif
2638 .retrigger = ioapic_retrigger_irq,
2639 };
2640
2641 static inline void init_IO_APIC_traps(void)
2642 {
2643 int irq;
2644 struct irq_desc *desc;
2645 struct irq_cfg *cfg;
2646
2647 /*
2648 * NOTE! The local APIC isn't very good at handling
2649 * multiple interrupts at the same interrupt level.
2650 * As the interrupt level is determined by taking the
2651 * vector number and shifting that right by 4, we
2652 * want to spread these out a bit so that they don't
2653 * all fall in the same interrupt level.
2654 *
2655 * Also, we've got to be careful not to trash gate
2656 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2657 */
2658 for_each_irq_desc(irq, desc) {
2659 cfg = desc->chip_data;
2660 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2661 /*
2662 * Hmm.. We don't have an entry for this,
2663 * so default to an old-fashioned 8259
2664 * interrupt if we can..
2665 */
2666 if (irq < NR_IRQS_LEGACY)
2667 make_8259A_irq(irq);
2668 else
2669 /* Strange. Oh, well.. */
2670 desc->chip = &no_irq_chip;
2671 }
2672 }
2673 }
2674
2675 /*
2676 * The local APIC irq-chip implementation:
2677 */
2678
2679 static void mask_lapic_irq(unsigned int irq)
2680 {
2681 unsigned long v;
2682
2683 v = apic_read(APIC_LVT0);
2684 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2685 }
2686
2687 static void unmask_lapic_irq(unsigned int irq)
2688 {
2689 unsigned long v;
2690
2691 v = apic_read(APIC_LVT0);
2692 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2693 }
2694
2695 static void ack_lapic_irq(unsigned int irq)
2696 {
2697 ack_APIC_irq();
2698 }
2699
2700 static struct irq_chip lapic_chip __read_mostly = {
2701 .name = "local-APIC",
2702 .mask = mask_lapic_irq,
2703 .unmask = unmask_lapic_irq,
2704 .ack = ack_lapic_irq,
2705 };
2706
2707 static void lapic_register_intr(int irq, struct irq_desc *desc)
2708 {
2709 desc->status &= ~IRQ_LEVEL;
2710 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2711 "edge");
2712 }
2713
2714 static void __init setup_nmi(void)
2715 {
2716 /*
2717 * Dirty trick to enable the NMI watchdog ...
2718 * We put the 8259A master into AEOI mode and
2719 * unmask on all local APICs LVT0 as NMI.
2720 *
2721 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2722 * is from Maciej W. Rozycki - so we do not have to EOI from
2723 * the NMI handler or the timer interrupt.
2724 */
2725 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2726
2727 enable_NMI_through_LVT0();
2728
2729 apic_printk(APIC_VERBOSE, " done.\n");
2730 }
2731
2732 /*
2733 * This looks a bit hackish but it's about the only one way of sending
2734 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2735 * not support the ExtINT mode, unfortunately. We need to send these
2736 * cycles as some i82489DX-based boards have glue logic that keeps the
2737 * 8259A interrupt line asserted until INTA. --macro
2738 */
2739 static inline void __init unlock_ExtINT_logic(void)
2740 {
2741 int apic, pin, i;
2742 struct IO_APIC_route_entry entry0, entry1;
2743 unsigned char save_control, save_freq_select;
2744
2745 pin = find_isa_irq_pin(8, mp_INT);
2746 if (pin == -1) {
2747 WARN_ON_ONCE(1);
2748 return;
2749 }
2750 apic = find_isa_irq_apic(8, mp_INT);
2751 if (apic == -1) {
2752 WARN_ON_ONCE(1);
2753 return;
2754 }
2755
2756 entry0 = ioapic_read_entry(apic, pin);
2757 clear_IO_APIC_pin(apic, pin);
2758
2759 memset(&entry1, 0, sizeof(entry1));
2760
2761 entry1.dest_mode = 0; /* physical delivery */
2762 entry1.mask = 0; /* unmask IRQ now */
2763 entry1.dest = hard_smp_processor_id();
2764 entry1.delivery_mode = dest_ExtINT;
2765 entry1.polarity = entry0.polarity;
2766 entry1.trigger = 0;
2767 entry1.vector = 0;
2768
2769 ioapic_write_entry(apic, pin, entry1);
2770
2771 save_control = CMOS_READ(RTC_CONTROL);
2772 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2773 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2774 RTC_FREQ_SELECT);
2775 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2776
2777 i = 100;
2778 while (i-- > 0) {
2779 mdelay(10);
2780 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2781 i -= 10;
2782 }
2783
2784 CMOS_WRITE(save_control, RTC_CONTROL);
2785 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2786 clear_IO_APIC_pin(apic, pin);
2787
2788 ioapic_write_entry(apic, pin, entry0);
2789 }
2790
2791 static int disable_timer_pin_1 __initdata;
2792 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2793 static int __init disable_timer_pin_setup(char *arg)
2794 {
2795 disable_timer_pin_1 = 1;
2796 return 0;
2797 }
2798 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2799
2800 int timer_through_8259 __initdata;
2801
2802 /*
2803 * This code may look a bit paranoid, but it's supposed to cooperate with
2804 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2805 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2806 * fanatically on his truly buggy board.
2807 *
2808 * FIXME: really need to revamp this for all platforms.
2809 */
2810 static inline void __init check_timer(void)
2811 {
2812 struct irq_desc *desc = irq_to_desc(0);
2813 struct irq_cfg *cfg = desc->chip_data;
2814 int node = cpu_to_node(boot_cpu_id);
2815 int apic1, pin1, apic2, pin2;
2816 unsigned long flags;
2817 int no_pin1 = 0;
2818
2819 local_irq_save(flags);
2820
2821 /*
2822 * get/set the timer IRQ vector:
2823 */
2824 disable_8259A_irq(0);
2825 assign_irq_vector(0, cfg, apic->target_cpus());
2826
2827 /*
2828 * As IRQ0 is to be enabled in the 8259A, the virtual
2829 * wire has to be disabled in the local APIC. Also
2830 * timer interrupts need to be acknowledged manually in
2831 * the 8259A for the i82489DX when using the NMI
2832 * watchdog as that APIC treats NMIs as level-triggered.
2833 * The AEOI mode will finish them in the 8259A
2834 * automatically.
2835 */
2836 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2837 init_8259A(1);
2838 #ifdef CONFIG_X86_32
2839 {
2840 unsigned int ver;
2841
2842 ver = apic_read(APIC_LVR);
2843 ver = GET_APIC_VERSION(ver);
2844 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2845 }
2846 #endif
2847
2848 pin1 = find_isa_irq_pin(0, mp_INT);
2849 apic1 = find_isa_irq_apic(0, mp_INT);
2850 pin2 = ioapic_i8259.pin;
2851 apic2 = ioapic_i8259.apic;
2852
2853 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2854 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2855 cfg->vector, apic1, pin1, apic2, pin2);
2856
2857 /*
2858 * Some BIOS writers are clueless and report the ExtINTA
2859 * I/O APIC input from the cascaded 8259A as the timer
2860 * interrupt input. So just in case, if only one pin
2861 * was found above, try it both directly and through the
2862 * 8259A.
2863 */
2864 if (pin1 == -1) {
2865 if (intr_remapping_enabled)
2866 panic("BIOS bug: timer not connected to IO-APIC");
2867 pin1 = pin2;
2868 apic1 = apic2;
2869 no_pin1 = 1;
2870 } else if (pin2 == -1) {
2871 pin2 = pin1;
2872 apic2 = apic1;
2873 }
2874
2875 if (pin1 != -1) {
2876 /*
2877 * Ok, does IRQ0 through the IOAPIC work?
2878 */
2879 if (no_pin1) {
2880 add_pin_to_irq_node(cfg, node, apic1, pin1);
2881 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2882 } else {
2883 /* for edge trigger, setup_IO_APIC_irq already
2884 * leave it unmasked.
2885 * so only need to unmask if it is level-trigger
2886 * do we really have level trigger timer?
2887 */
2888 int idx;
2889 idx = find_irq_entry(apic1, pin1, mp_INT);
2890 if (idx != -1 && irq_trigger(idx))
2891 unmask_IO_APIC_irq_desc(desc);
2892 }
2893 if (timer_irq_works()) {
2894 if (nmi_watchdog == NMI_IO_APIC) {
2895 setup_nmi();
2896 enable_8259A_irq(0);
2897 }
2898 if (disable_timer_pin_1 > 0)
2899 clear_IO_APIC_pin(0, pin1);
2900 goto out;
2901 }
2902 if (intr_remapping_enabled)
2903 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2904 local_irq_disable();
2905 clear_IO_APIC_pin(apic1, pin1);
2906 if (!no_pin1)
2907 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2908 "8254 timer not connected to IO-APIC\n");
2909
2910 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2911 "(IRQ0) through the 8259A ...\n");
2912 apic_printk(APIC_QUIET, KERN_INFO
2913 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2914 /*
2915 * legacy devices should be connected to IO APIC #0
2916 */
2917 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2918 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2919 enable_8259A_irq(0);
2920 if (timer_irq_works()) {
2921 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2922 timer_through_8259 = 1;
2923 if (nmi_watchdog == NMI_IO_APIC) {
2924 disable_8259A_irq(0);
2925 setup_nmi();
2926 enable_8259A_irq(0);
2927 }
2928 goto out;
2929 }
2930 /*
2931 * Cleanup, just in case ...
2932 */
2933 local_irq_disable();
2934 disable_8259A_irq(0);
2935 clear_IO_APIC_pin(apic2, pin2);
2936 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2937 }
2938
2939 if (nmi_watchdog == NMI_IO_APIC) {
2940 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2941 "through the IO-APIC - disabling NMI Watchdog!\n");
2942 nmi_watchdog = NMI_NONE;
2943 }
2944 #ifdef CONFIG_X86_32
2945 timer_ack = 0;
2946 #endif
2947
2948 apic_printk(APIC_QUIET, KERN_INFO
2949 "...trying to set up timer as Virtual Wire IRQ...\n");
2950
2951 lapic_register_intr(0, desc);
2952 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2953 enable_8259A_irq(0);
2954
2955 if (timer_irq_works()) {
2956 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2957 goto out;
2958 }
2959 local_irq_disable();
2960 disable_8259A_irq(0);
2961 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2962 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2963
2964 apic_printk(APIC_QUIET, KERN_INFO
2965 "...trying to set up timer as ExtINT IRQ...\n");
2966
2967 init_8259A(0);
2968 make_8259A_irq(0);
2969 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2970
2971 unlock_ExtINT_logic();
2972
2973 if (timer_irq_works()) {
2974 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2975 goto out;
2976 }
2977 local_irq_disable();
2978 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2979 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2980 "report. Then try booting with the 'noapic' option.\n");
2981 out:
2982 local_irq_restore(flags);
2983 }
2984
2985 /*
2986 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2987 * to devices. However there may be an I/O APIC pin available for
2988 * this interrupt regardless. The pin may be left unconnected, but
2989 * typically it will be reused as an ExtINT cascade interrupt for
2990 * the master 8259A. In the MPS case such a pin will normally be
2991 * reported as an ExtINT interrupt in the MP table. With ACPI
2992 * there is no provision for ExtINT interrupts, and in the absence
2993 * of an override it would be treated as an ordinary ISA I/O APIC
2994 * interrupt, that is edge-triggered and unmasked by default. We
2995 * used to do this, but it caused problems on some systems because
2996 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2997 * the same ExtINT cascade interrupt to drive the local APIC of the
2998 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2999 * the I/O APIC in all cases now. No actual device should request
3000 * it anyway. --macro
3001 */
3002 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3003
3004 void __init setup_IO_APIC(void)
3005 {
3006
3007 /*
3008 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3009 */
3010
3011 io_apic_irqs = ~PIC_IRQS;
3012
3013 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3014 /*
3015 * Set up IO-APIC IRQ routing.
3016 */
3017 #ifdef CONFIG_X86_32
3018 if (!acpi_ioapic)
3019 setup_ioapic_ids_from_mpc();
3020 #endif
3021 sync_Arb_IDs();
3022 setup_IO_APIC_irqs();
3023 init_IO_APIC_traps();
3024 check_timer();
3025 }
3026
3027 /*
3028 * Called after all the initialization is done. If we didnt find any
3029 * APIC bugs then we can allow the modify fast path
3030 */
3031
3032 static int __init io_apic_bug_finalize(void)
3033 {
3034 if (sis_apic_bug == -1)
3035 sis_apic_bug = 0;
3036 return 0;
3037 }
3038
3039 late_initcall(io_apic_bug_finalize);
3040
3041 struct sysfs_ioapic_data {
3042 struct sys_device dev;
3043 struct IO_APIC_route_entry entry[0];
3044 };
3045 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3046
3047 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3048 {
3049 struct IO_APIC_route_entry *entry;
3050 struct sysfs_ioapic_data *data;
3051 int i;
3052
3053 data = container_of(dev, struct sysfs_ioapic_data, dev);
3054 entry = data->entry;
3055 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3056 *entry = ioapic_read_entry(dev->id, i);
3057
3058 return 0;
3059 }
3060
3061 static int ioapic_resume(struct sys_device *dev)
3062 {
3063 struct IO_APIC_route_entry *entry;
3064 struct sysfs_ioapic_data *data;
3065 unsigned long flags;
3066 union IO_APIC_reg_00 reg_00;
3067 int i;
3068
3069 data = container_of(dev, struct sysfs_ioapic_data, dev);
3070 entry = data->entry;
3071
3072 spin_lock_irqsave(&ioapic_lock, flags);
3073 reg_00.raw = io_apic_read(dev->id, 0);
3074 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3075 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3076 io_apic_write(dev->id, 0, reg_00.raw);
3077 }
3078 spin_unlock_irqrestore(&ioapic_lock, flags);
3079 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3080 ioapic_write_entry(dev->id, i, entry[i]);
3081
3082 return 0;
3083 }
3084
3085 static struct sysdev_class ioapic_sysdev_class = {
3086 .name = "ioapic",
3087 .suspend = ioapic_suspend,
3088 .resume = ioapic_resume,
3089 };
3090
3091 static int __init ioapic_init_sysfs(void)
3092 {
3093 struct sys_device * dev;
3094 int i, size, error;
3095
3096 error = sysdev_class_register(&ioapic_sysdev_class);
3097 if (error)
3098 return error;
3099
3100 for (i = 0; i < nr_ioapics; i++ ) {
3101 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3102 * sizeof(struct IO_APIC_route_entry);
3103 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3104 if (!mp_ioapic_data[i]) {
3105 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3106 continue;
3107 }
3108 dev = &mp_ioapic_data[i]->dev;
3109 dev->id = i;
3110 dev->cls = &ioapic_sysdev_class;
3111 error = sysdev_register(dev);
3112 if (error) {
3113 kfree(mp_ioapic_data[i]);
3114 mp_ioapic_data[i] = NULL;
3115 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3116 continue;
3117 }
3118 }
3119
3120 return 0;
3121 }
3122
3123 device_initcall(ioapic_init_sysfs);
3124
3125 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3126 /*
3127 * Dynamic irq allocate and deallocation
3128 */
3129 unsigned int create_irq_nr(unsigned int irq_want, int node)
3130 {
3131 /* Allocate an unused irq */
3132 unsigned int irq;
3133 unsigned int new;
3134 unsigned long flags;
3135 struct irq_cfg *cfg_new = NULL;
3136 struct irq_desc *desc_new = NULL;
3137
3138 irq = 0;
3139 if (irq_want < nr_irqs_gsi)
3140 irq_want = nr_irqs_gsi;
3141
3142 spin_lock_irqsave(&vector_lock, flags);
3143 for (new = irq_want; new < nr_irqs; new++) {
3144 desc_new = irq_to_desc_alloc_node(new, node);
3145 if (!desc_new) {
3146 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3147 continue;
3148 }
3149 cfg_new = desc_new->chip_data;
3150
3151 if (cfg_new->vector != 0)
3152 continue;
3153
3154 desc_new = move_irq_desc(desc_new, node);
3155
3156 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3157 irq = new;
3158 break;
3159 }
3160 spin_unlock_irqrestore(&vector_lock, flags);
3161
3162 if (irq > 0) {
3163 dynamic_irq_init(irq);
3164 /* restore it, in case dynamic_irq_init clear it */
3165 if (desc_new)
3166 desc_new->chip_data = cfg_new;
3167 }
3168 return irq;
3169 }
3170
3171 int create_irq(void)
3172 {
3173 int node = cpu_to_node(boot_cpu_id);
3174 unsigned int irq_want;
3175 int irq;
3176
3177 irq_want = nr_irqs_gsi;
3178 irq = create_irq_nr(irq_want, node);
3179
3180 if (irq == 0)
3181 irq = -1;
3182
3183 return irq;
3184 }
3185
3186 void destroy_irq(unsigned int irq)
3187 {
3188 unsigned long flags;
3189 struct irq_cfg *cfg;
3190 struct irq_desc *desc;
3191
3192 /* store it, in case dynamic_irq_cleanup clear it */
3193 desc = irq_to_desc(irq);
3194 cfg = desc->chip_data;
3195 dynamic_irq_cleanup(irq);
3196 /* connect back irq_cfg */
3197 if (desc)
3198 desc->chip_data = cfg;
3199
3200 free_irte(irq);
3201 spin_lock_irqsave(&vector_lock, flags);
3202 __clear_irq_vector(irq, cfg);
3203 spin_unlock_irqrestore(&vector_lock, flags);
3204 }
3205
3206 /*
3207 * MSI message composition
3208 */
3209 #ifdef CONFIG_PCI_MSI
3210 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3211 {
3212 struct irq_cfg *cfg;
3213 int err;
3214 unsigned dest;
3215
3216 if (disable_apic)
3217 return -ENXIO;
3218
3219 cfg = irq_cfg(irq);
3220 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3221 if (err)
3222 return err;
3223
3224 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3225
3226 if (irq_remapped(irq)) {
3227 struct irte irte;
3228 int ir_index;
3229 u16 sub_handle;
3230
3231 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3232 BUG_ON(ir_index == -1);
3233
3234 memset (&irte, 0, sizeof(irte));
3235
3236 irte.present = 1;
3237 irte.dst_mode = apic->irq_dest_mode;
3238 irte.trigger_mode = 0; /* edge */
3239 irte.dlvry_mode = apic->irq_delivery_mode;
3240 irte.vector = cfg->vector;
3241 irte.dest_id = IRTE_DEST(dest);
3242
3243 /* Set source-id of interrupt request */
3244 set_msi_sid(&irte, pdev);
3245
3246 modify_irte(irq, &irte);
3247
3248 msg->address_hi = MSI_ADDR_BASE_HI;
3249 msg->data = sub_handle;
3250 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3251 MSI_ADDR_IR_SHV |
3252 MSI_ADDR_IR_INDEX1(ir_index) |
3253 MSI_ADDR_IR_INDEX2(ir_index);
3254 } else {
3255 if (x2apic_enabled())
3256 msg->address_hi = MSI_ADDR_BASE_HI |
3257 MSI_ADDR_EXT_DEST_ID(dest);
3258 else
3259 msg->address_hi = MSI_ADDR_BASE_HI;
3260
3261 msg->address_lo =
3262 MSI_ADDR_BASE_LO |
3263 ((apic->irq_dest_mode == 0) ?
3264 MSI_ADDR_DEST_MODE_PHYSICAL:
3265 MSI_ADDR_DEST_MODE_LOGICAL) |
3266 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3267 MSI_ADDR_REDIRECTION_CPU:
3268 MSI_ADDR_REDIRECTION_LOWPRI) |
3269 MSI_ADDR_DEST_ID(dest);
3270
3271 msg->data =
3272 MSI_DATA_TRIGGER_EDGE |
3273 MSI_DATA_LEVEL_ASSERT |
3274 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3275 MSI_DATA_DELIVERY_FIXED:
3276 MSI_DATA_DELIVERY_LOWPRI) |
3277 MSI_DATA_VECTOR(cfg->vector);
3278 }
3279 return err;
3280 }
3281
3282 #ifdef CONFIG_SMP
3283 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3284 {
3285 struct irq_desc *desc = irq_to_desc(irq);
3286 struct irq_cfg *cfg;
3287 struct msi_msg msg;
3288 unsigned int dest;
3289
3290 dest = set_desc_affinity(desc, mask);
3291 if (dest == BAD_APICID)
3292 return -1;
3293
3294 cfg = desc->chip_data;
3295
3296 read_msi_msg_desc(desc, &msg);
3297
3298 msg.data &= ~MSI_DATA_VECTOR_MASK;
3299 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3300 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3301 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3302
3303 write_msi_msg_desc(desc, &msg);
3304
3305 return 0;
3306 }
3307 #ifdef CONFIG_INTR_REMAP
3308 /*
3309 * Migrate the MSI irq to another cpumask. This migration is
3310 * done in the process context using interrupt-remapping hardware.
3311 */
3312 static int
3313 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3314 {
3315 struct irq_desc *desc = irq_to_desc(irq);
3316 struct irq_cfg *cfg = desc->chip_data;
3317 unsigned int dest;
3318 struct irte irte;
3319
3320 if (get_irte(irq, &irte))
3321 return -1;
3322
3323 dest = set_desc_affinity(desc, mask);
3324 if (dest == BAD_APICID)
3325 return -1;
3326
3327 irte.vector = cfg->vector;
3328 irte.dest_id = IRTE_DEST(dest);
3329
3330 /*
3331 * atomically update the IRTE with the new destination and vector.
3332 */
3333 modify_irte(irq, &irte);
3334
3335 /*
3336 * After this point, all the interrupts will start arriving
3337 * at the new destination. So, time to cleanup the previous
3338 * vector allocation.
3339 */
3340 if (cfg->move_in_progress)
3341 send_cleanup_vector(cfg);
3342
3343 return 0;
3344 }
3345
3346 #endif
3347 #endif /* CONFIG_SMP */
3348
3349 /*
3350 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3351 * which implement the MSI or MSI-X Capability Structure.
3352 */
3353 static struct irq_chip msi_chip = {
3354 .name = "PCI-MSI",
3355 .unmask = unmask_msi_irq,
3356 .mask = mask_msi_irq,
3357 .ack = ack_apic_edge,
3358 #ifdef CONFIG_SMP
3359 .set_affinity = set_msi_irq_affinity,
3360 #endif
3361 .retrigger = ioapic_retrigger_irq,
3362 };
3363
3364 static struct irq_chip msi_ir_chip = {
3365 .name = "IR-PCI-MSI",
3366 .unmask = unmask_msi_irq,
3367 .mask = mask_msi_irq,
3368 #ifdef CONFIG_INTR_REMAP
3369 .ack = ir_ack_apic_edge,
3370 #ifdef CONFIG_SMP
3371 .set_affinity = ir_set_msi_irq_affinity,
3372 #endif
3373 #endif
3374 .retrigger = ioapic_retrigger_irq,
3375 };
3376
3377 /*
3378 * Map the PCI dev to the corresponding remapping hardware unit
3379 * and allocate 'nvec' consecutive interrupt-remapping table entries
3380 * in it.
3381 */
3382 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3383 {
3384 struct intel_iommu *iommu;
3385 int index;
3386
3387 iommu = map_dev_to_ir(dev);
3388 if (!iommu) {
3389 printk(KERN_ERR
3390 "Unable to map PCI %s to iommu\n", pci_name(dev));
3391 return -ENOENT;
3392 }
3393
3394 index = alloc_irte(iommu, irq, nvec);
3395 if (index < 0) {
3396 printk(KERN_ERR
3397 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3398 pci_name(dev));
3399 return -ENOSPC;
3400 }
3401 return index;
3402 }
3403
3404 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3405 {
3406 int ret;
3407 struct msi_msg msg;
3408
3409 ret = msi_compose_msg(dev, irq, &msg);
3410 if (ret < 0)
3411 return ret;
3412
3413 set_irq_msi(irq, msidesc);
3414 write_msi_msg(irq, &msg);
3415
3416 if (irq_remapped(irq)) {
3417 struct irq_desc *desc = irq_to_desc(irq);
3418 /*
3419 * irq migration in process context
3420 */
3421 desc->status |= IRQ_MOVE_PCNTXT;
3422 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3423 } else
3424 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3425
3426 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3427
3428 return 0;
3429 }
3430
3431 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3432 {
3433 unsigned int irq;
3434 int ret, sub_handle;
3435 struct msi_desc *msidesc;
3436 unsigned int irq_want;
3437 struct intel_iommu *iommu = NULL;
3438 int index = 0;
3439 int node;
3440
3441 /* x86 doesn't support multiple MSI yet */
3442 if (type == PCI_CAP_ID_MSI && nvec > 1)
3443 return 1;
3444
3445 node = dev_to_node(&dev->dev);
3446 irq_want = nr_irqs_gsi;
3447 sub_handle = 0;
3448 list_for_each_entry(msidesc, &dev->msi_list, list) {
3449 irq = create_irq_nr(irq_want, node);
3450 if (irq == 0)
3451 return -1;
3452 irq_want = irq + 1;
3453 if (!intr_remapping_enabled)
3454 goto no_ir;
3455
3456 if (!sub_handle) {
3457 /*
3458 * allocate the consecutive block of IRTE's
3459 * for 'nvec'
3460 */
3461 index = msi_alloc_irte(dev, irq, nvec);
3462 if (index < 0) {
3463 ret = index;
3464 goto error;
3465 }
3466 } else {
3467 iommu = map_dev_to_ir(dev);
3468 if (!iommu) {
3469 ret = -ENOENT;
3470 goto error;
3471 }
3472 /*
3473 * setup the mapping between the irq and the IRTE
3474 * base index, the sub_handle pointing to the
3475 * appropriate interrupt remap table entry.
3476 */
3477 set_irte_irq(irq, iommu, index, sub_handle);
3478 }
3479 no_ir:
3480 ret = setup_msi_irq(dev, msidesc, irq);
3481 if (ret < 0)
3482 goto error;
3483 sub_handle++;
3484 }
3485 return 0;
3486
3487 error:
3488 destroy_irq(irq);
3489 return ret;
3490 }
3491
3492 void arch_teardown_msi_irq(unsigned int irq)
3493 {
3494 destroy_irq(irq);
3495 }
3496
3497 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3498 #ifdef CONFIG_SMP
3499 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3500 {
3501 struct irq_desc *desc = irq_to_desc(irq);
3502 struct irq_cfg *cfg;
3503 struct msi_msg msg;
3504 unsigned int dest;
3505
3506 dest = set_desc_affinity(desc, mask);
3507 if (dest == BAD_APICID)
3508 return -1;
3509
3510 cfg = desc->chip_data;
3511
3512 dmar_msi_read(irq, &msg);
3513
3514 msg.data &= ~MSI_DATA_VECTOR_MASK;
3515 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3516 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3517 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3518
3519 dmar_msi_write(irq, &msg);
3520
3521 return 0;
3522 }
3523
3524 #endif /* CONFIG_SMP */
3525
3526 static struct irq_chip dmar_msi_type = {
3527 .name = "DMAR_MSI",
3528 .unmask = dmar_msi_unmask,
3529 .mask = dmar_msi_mask,
3530 .ack = ack_apic_edge,
3531 #ifdef CONFIG_SMP
3532 .set_affinity = dmar_msi_set_affinity,
3533 #endif
3534 .retrigger = ioapic_retrigger_irq,
3535 };
3536
3537 int arch_setup_dmar_msi(unsigned int irq)
3538 {
3539 int ret;
3540 struct msi_msg msg;
3541
3542 ret = msi_compose_msg(NULL, irq, &msg);
3543 if (ret < 0)
3544 return ret;
3545 dmar_msi_write(irq, &msg);
3546 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3547 "edge");
3548 return 0;
3549 }
3550 #endif
3551
3552 #ifdef CONFIG_HPET_TIMER
3553
3554 #ifdef CONFIG_SMP
3555 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3556 {
3557 struct irq_desc *desc = irq_to_desc(irq);
3558 struct irq_cfg *cfg;
3559 struct msi_msg msg;
3560 unsigned int dest;
3561
3562 dest = set_desc_affinity(desc, mask);
3563 if (dest == BAD_APICID)
3564 return -1;
3565
3566 cfg = desc->chip_data;
3567
3568 hpet_msi_read(irq, &msg);
3569
3570 msg.data &= ~MSI_DATA_VECTOR_MASK;
3571 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3572 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3573 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3574
3575 hpet_msi_write(irq, &msg);
3576
3577 return 0;
3578 }
3579
3580 #endif /* CONFIG_SMP */
3581
3582 static struct irq_chip hpet_msi_type = {
3583 .name = "HPET_MSI",
3584 .unmask = hpet_msi_unmask,
3585 .mask = hpet_msi_mask,
3586 .ack = ack_apic_edge,
3587 #ifdef CONFIG_SMP
3588 .set_affinity = hpet_msi_set_affinity,
3589 #endif
3590 .retrigger = ioapic_retrigger_irq,
3591 };
3592
3593 int arch_setup_hpet_msi(unsigned int irq)
3594 {
3595 int ret;
3596 struct msi_msg msg;
3597 struct irq_desc *desc = irq_to_desc(irq);
3598
3599 ret = msi_compose_msg(NULL, irq, &msg);
3600 if (ret < 0)
3601 return ret;
3602
3603 hpet_msi_write(irq, &msg);
3604 desc->status |= IRQ_MOVE_PCNTXT;
3605 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3606 "edge");
3607
3608 return 0;
3609 }
3610 #endif
3611
3612 #endif /* CONFIG_PCI_MSI */
3613 /*
3614 * Hypertransport interrupt support
3615 */
3616 #ifdef CONFIG_HT_IRQ
3617
3618 #ifdef CONFIG_SMP
3619
3620 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3621 {
3622 struct ht_irq_msg msg;
3623 fetch_ht_irq_msg(irq, &msg);
3624
3625 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3626 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3627
3628 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3629 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3630
3631 write_ht_irq_msg(irq, &msg);
3632 }
3633
3634 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3635 {
3636 struct irq_desc *desc = irq_to_desc(irq);
3637 struct irq_cfg *cfg;
3638 unsigned int dest;
3639
3640 dest = set_desc_affinity(desc, mask);
3641 if (dest == BAD_APICID)
3642 return -1;
3643
3644 cfg = desc->chip_data;
3645
3646 target_ht_irq(irq, dest, cfg->vector);
3647
3648 return 0;
3649 }
3650
3651 #endif
3652
3653 static struct irq_chip ht_irq_chip = {
3654 .name = "PCI-HT",
3655 .mask = mask_ht_irq,
3656 .unmask = unmask_ht_irq,
3657 .ack = ack_apic_edge,
3658 #ifdef CONFIG_SMP
3659 .set_affinity = set_ht_irq_affinity,
3660 #endif
3661 .retrigger = ioapic_retrigger_irq,
3662 };
3663
3664 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3665 {
3666 struct irq_cfg *cfg;
3667 int err;
3668
3669 if (disable_apic)
3670 return -ENXIO;
3671
3672 cfg = irq_cfg(irq);
3673 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3674 if (!err) {
3675 struct ht_irq_msg msg;
3676 unsigned dest;
3677
3678 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3679 apic->target_cpus());
3680
3681 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3682
3683 msg.address_lo =
3684 HT_IRQ_LOW_BASE |
3685 HT_IRQ_LOW_DEST_ID(dest) |
3686 HT_IRQ_LOW_VECTOR(cfg->vector) |
3687 ((apic->irq_dest_mode == 0) ?
3688 HT_IRQ_LOW_DM_PHYSICAL :
3689 HT_IRQ_LOW_DM_LOGICAL) |
3690 HT_IRQ_LOW_RQEOI_EDGE |
3691 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3692 HT_IRQ_LOW_MT_FIXED :
3693 HT_IRQ_LOW_MT_ARBITRATED) |
3694 HT_IRQ_LOW_IRQ_MASKED;
3695
3696 write_ht_irq_msg(irq, &msg);
3697
3698 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3699 handle_edge_irq, "edge");
3700
3701 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3702 }
3703 return err;
3704 }
3705 #endif /* CONFIG_HT_IRQ */
3706
3707 #ifdef CONFIG_X86_UV
3708 /*
3709 * Re-target the irq to the specified CPU and enable the specified MMR located
3710 * on the specified blade to allow the sending of MSIs to the specified CPU.
3711 */
3712 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3713 unsigned long mmr_offset)
3714 {
3715 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3716 struct irq_cfg *cfg;
3717 int mmr_pnode;
3718 unsigned long mmr_value;
3719 struct uv_IO_APIC_route_entry *entry;
3720 unsigned long flags;
3721 int err;
3722
3723 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3724
3725 cfg = irq_cfg(irq);
3726
3727 err = assign_irq_vector(irq, cfg, eligible_cpu);
3728 if (err != 0)
3729 return err;
3730
3731 spin_lock_irqsave(&vector_lock, flags);
3732 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3733 irq_name);
3734 spin_unlock_irqrestore(&vector_lock, flags);
3735
3736 mmr_value = 0;
3737 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3738 entry->vector = cfg->vector;
3739 entry->delivery_mode = apic->irq_delivery_mode;
3740 entry->dest_mode = apic->irq_dest_mode;
3741 entry->polarity = 0;
3742 entry->trigger = 0;
3743 entry->mask = 0;
3744 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3745
3746 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3747 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3748
3749 return irq;
3750 }
3751
3752 /*
3753 * Disable the specified MMR located on the specified blade so that MSIs are
3754 * longer allowed to be sent.
3755 */
3756 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3757 {
3758 unsigned long mmr_value;
3759 struct uv_IO_APIC_route_entry *entry;
3760 int mmr_pnode;
3761
3762 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3763
3764 mmr_value = 0;
3765 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3766 entry->mask = 1;
3767
3768 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3769 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3770 }
3771 #endif /* CONFIG_X86_64 */
3772
3773 int __init io_apic_get_redir_entries (int ioapic)
3774 {
3775 union IO_APIC_reg_01 reg_01;
3776 unsigned long flags;
3777
3778 spin_lock_irqsave(&ioapic_lock, flags);
3779 reg_01.raw = io_apic_read(ioapic, 1);
3780 spin_unlock_irqrestore(&ioapic_lock, flags);
3781
3782 return reg_01.bits.entries;
3783 }
3784
3785 void __init probe_nr_irqs_gsi(void)
3786 {
3787 int nr = 0;
3788
3789 nr = acpi_probe_gsi();
3790 if (nr > nr_irqs_gsi) {
3791 nr_irqs_gsi = nr;
3792 } else {
3793 /* for acpi=off or acpi is not compiled in */
3794 int idx;
3795
3796 nr = 0;
3797 for (idx = 0; idx < nr_ioapics; idx++)
3798 nr += io_apic_get_redir_entries(idx) + 1;
3799
3800 if (nr > nr_irqs_gsi)
3801 nr_irqs_gsi = nr;
3802 }
3803
3804 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3805 }
3806
3807 #ifdef CONFIG_SPARSE_IRQ
3808 int __init arch_probe_nr_irqs(void)
3809 {
3810 int nr;
3811
3812 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3813 nr_irqs = NR_VECTORS * nr_cpu_ids;
3814
3815 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3816 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3817 /*
3818 * for MSI and HT dyn irq
3819 */
3820 nr += nr_irqs_gsi * 16;
3821 #endif
3822 if (nr < nr_irqs)
3823 nr_irqs = nr;
3824
3825 return 0;
3826 }
3827 #endif
3828
3829 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3830 struct io_apic_irq_attr *irq_attr)
3831 {
3832 struct irq_desc *desc;
3833 struct irq_cfg *cfg;
3834 int node;
3835 int ioapic, pin;
3836 int trigger, polarity;
3837
3838 ioapic = irq_attr->ioapic;
3839 if (!IO_APIC_IRQ(irq)) {
3840 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3841 ioapic);
3842 return -EINVAL;
3843 }
3844
3845 if (dev)
3846 node = dev_to_node(dev);
3847 else
3848 node = cpu_to_node(boot_cpu_id);
3849
3850 desc = irq_to_desc_alloc_node(irq, node);
3851 if (!desc) {
3852 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3853 return 0;
3854 }
3855
3856 pin = irq_attr->ioapic_pin;
3857 trigger = irq_attr->trigger;
3858 polarity = irq_attr->polarity;
3859
3860 /*
3861 * IRQs < 16 are already in the irq_2_pin[] map
3862 */
3863 if (irq >= NR_IRQS_LEGACY) {
3864 cfg = desc->chip_data;
3865 add_pin_to_irq_node(cfg, node, ioapic, pin);
3866 }
3867
3868 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3869
3870 return 0;
3871 }
3872
3873 int io_apic_set_pci_routing(struct device *dev, int irq,
3874 struct io_apic_irq_attr *irq_attr)
3875 {
3876 int ioapic, pin;
3877 /*
3878 * Avoid pin reprogramming. PRTs typically include entries
3879 * with redundant pin->gsi mappings (but unique PCI devices);
3880 * we only program the IOAPIC on the first.
3881 */
3882 ioapic = irq_attr->ioapic;
3883 pin = irq_attr->ioapic_pin;
3884 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3885 pr_debug("Pin %d-%d already programmed\n",
3886 mp_ioapics[ioapic].apicid, pin);
3887 return 0;
3888 }
3889 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3890
3891 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3892 }
3893
3894 /* --------------------------------------------------------------------------
3895 ACPI-based IOAPIC Configuration
3896 -------------------------------------------------------------------------- */
3897
3898 #ifdef CONFIG_ACPI
3899
3900 #ifdef CONFIG_X86_32
3901 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3902 {
3903 union IO_APIC_reg_00 reg_00;
3904 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3905 physid_mask_t tmp;
3906 unsigned long flags;
3907 int i = 0;
3908
3909 /*
3910 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3911 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3912 * supports up to 16 on one shared APIC bus.
3913 *
3914 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3915 * advantage of new APIC bus architecture.
3916 */
3917
3918 if (physids_empty(apic_id_map))
3919 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3920
3921 spin_lock_irqsave(&ioapic_lock, flags);
3922 reg_00.raw = io_apic_read(ioapic, 0);
3923 spin_unlock_irqrestore(&ioapic_lock, flags);
3924
3925 if (apic_id >= get_physical_broadcast()) {
3926 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3927 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3928 apic_id = reg_00.bits.ID;
3929 }
3930
3931 /*
3932 * Every APIC in a system must have a unique ID or we get lots of nice
3933 * 'stuck on smp_invalidate_needed IPI wait' messages.
3934 */
3935 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3936
3937 for (i = 0; i < get_physical_broadcast(); i++) {
3938 if (!apic->check_apicid_used(apic_id_map, i))
3939 break;
3940 }
3941
3942 if (i == get_physical_broadcast())
3943 panic("Max apic_id exceeded!\n");
3944
3945 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3946 "trying %d\n", ioapic, apic_id, i);
3947
3948 apic_id = i;
3949 }
3950
3951 tmp = apic->apicid_to_cpu_present(apic_id);
3952 physids_or(apic_id_map, apic_id_map, tmp);
3953
3954 if (reg_00.bits.ID != apic_id) {
3955 reg_00.bits.ID = apic_id;
3956
3957 spin_lock_irqsave(&ioapic_lock, flags);
3958 io_apic_write(ioapic, 0, reg_00.raw);
3959 reg_00.raw = io_apic_read(ioapic, 0);
3960 spin_unlock_irqrestore(&ioapic_lock, flags);
3961
3962 /* Sanity check */
3963 if (reg_00.bits.ID != apic_id) {
3964 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3965 return -1;
3966 }
3967 }
3968
3969 apic_printk(APIC_VERBOSE, KERN_INFO
3970 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3971
3972 return apic_id;
3973 }
3974 #endif
3975
3976 int __init io_apic_get_version(int ioapic)
3977 {
3978 union IO_APIC_reg_01 reg_01;
3979 unsigned long flags;
3980
3981 spin_lock_irqsave(&ioapic_lock, flags);
3982 reg_01.raw = io_apic_read(ioapic, 1);
3983 spin_unlock_irqrestore(&ioapic_lock, flags);
3984
3985 return reg_01.bits.version;
3986 }
3987
3988 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3989 {
3990 int i;
3991
3992 if (skip_ioapic_setup)
3993 return -1;
3994
3995 for (i = 0; i < mp_irq_entries; i++)
3996 if (mp_irqs[i].irqtype == mp_INT &&
3997 mp_irqs[i].srcbusirq == bus_irq)
3998 break;
3999 if (i >= mp_irq_entries)
4000 return -1;
4001
4002 *trigger = irq_trigger(i);
4003 *polarity = irq_polarity(i);
4004 return 0;
4005 }
4006
4007 #endif /* CONFIG_ACPI */
4008
4009 /*
4010 * This function currently is only a helper for the i386 smp boot process where
4011 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4012 * so mask in all cases should simply be apic->target_cpus()
4013 */
4014 #ifdef CONFIG_SMP
4015 void __init setup_ioapic_dest(void)
4016 {
4017 int pin, ioapic = 0, irq, irq_entry;
4018 struct irq_desc *desc;
4019 const struct cpumask *mask;
4020
4021 if (skip_ioapic_setup == 1)
4022 return;
4023
4024 #ifdef CONFIG_ACPI
4025 if (!acpi_disabled && acpi_ioapic) {
4026 ioapic = mp_find_ioapic(0);
4027 if (ioapic < 0)
4028 ioapic = 0;
4029 }
4030 #endif
4031
4032 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4033 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4034 if (irq_entry == -1)
4035 continue;
4036 irq = pin_2_irq(irq_entry, ioapic, pin);
4037
4038 desc = irq_to_desc(irq);
4039
4040 /*
4041 * Honour affinities which have been set in early boot
4042 */
4043 if (desc->status &
4044 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4045 mask = desc->affinity;
4046 else
4047 mask = apic->target_cpus();
4048
4049 if (intr_remapping_enabled)
4050 set_ir_ioapic_affinity_irq_desc(desc, mask);
4051 else
4052 set_ioapic_affinity_irq_desc(desc, mask);
4053 }
4054
4055 }
4056 #endif
4057
4058 #define IOAPIC_RESOURCE_NAME_SIZE 11
4059
4060 static struct resource *ioapic_resources;
4061
4062 static struct resource * __init ioapic_setup_resources(void)
4063 {
4064 unsigned long n;
4065 struct resource *res;
4066 char *mem;
4067 int i;
4068
4069 if (nr_ioapics <= 0)
4070 return NULL;
4071
4072 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4073 n *= nr_ioapics;
4074
4075 mem = alloc_bootmem(n);
4076 res = (void *)mem;
4077
4078 if (mem != NULL) {
4079 mem += sizeof(struct resource) * nr_ioapics;
4080
4081 for (i = 0; i < nr_ioapics; i++) {
4082 res[i].name = mem;
4083 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4084 sprintf(mem, "IOAPIC %u", i);
4085 mem += IOAPIC_RESOURCE_NAME_SIZE;
4086 }
4087 }
4088
4089 ioapic_resources = res;
4090
4091 return res;
4092 }
4093
4094 void __init ioapic_init_mappings(void)
4095 {
4096 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4097 struct resource *ioapic_res;
4098 int i;
4099
4100 ioapic_res = ioapic_setup_resources();
4101 for (i = 0; i < nr_ioapics; i++) {
4102 if (smp_found_config) {
4103 ioapic_phys = mp_ioapics[i].apicaddr;
4104 #ifdef CONFIG_X86_32
4105 if (!ioapic_phys) {
4106 printk(KERN_ERR
4107 "WARNING: bogus zero IO-APIC "
4108 "address found in MPTABLE, "
4109 "disabling IO/APIC support!\n");
4110 smp_found_config = 0;
4111 skip_ioapic_setup = 1;
4112 goto fake_ioapic_page;
4113 }
4114 #endif
4115 } else {
4116 #ifdef CONFIG_X86_32
4117 fake_ioapic_page:
4118 #endif
4119 ioapic_phys = (unsigned long)
4120 alloc_bootmem_pages(PAGE_SIZE);
4121 ioapic_phys = __pa(ioapic_phys);
4122 }
4123 set_fixmap_nocache(idx, ioapic_phys);
4124 apic_printk(APIC_VERBOSE,
4125 "mapped IOAPIC to %08lx (%08lx)\n",
4126 __fix_to_virt(idx), ioapic_phys);
4127 idx++;
4128
4129 if (ioapic_res != NULL) {
4130 ioapic_res->start = ioapic_phys;
4131 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4132 ioapic_res++;
4133 }
4134 }
4135 }
4136
4137 static int __init ioapic_insert_resources(void)
4138 {
4139 int i;
4140 struct resource *r = ioapic_resources;
4141
4142 if (!r) {
4143 if (nr_ioapics > 0) {
4144 printk(KERN_ERR
4145 "IO APIC resources couldn't be allocated.\n");
4146 return -1;
4147 }
4148 return 0;
4149 }
4150
4151 for (i = 0; i < nr_ioapics; i++) {
4152 insert_resource(&iomem_resource, r);
4153 r++;
4154 }
4155
4156 return 0;
4157 }
4158
4159 /* Insert the IO APIC resources after PCI initialization has occured to handle
4160 * IO APICS that are mapped in on a BAR in PCI space. */
4161 late_initcall(ioapic_insert_resources);
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