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[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28 #include <linux/reboot.h>
29 #include <linux/memory.h>
30
31 #include <asm/uv/uv_mmrs.h>
32 #include <asm/uv/uv_hub.h>
33 #include <asm/current.h>
34 #include <asm/pgtable.h>
35 #include <asm/uv/bios.h>
36 #include <asm/uv/uv.h>
37 #include <asm/apic.h>
38 #include <asm/e820/api.h>
39 #include <asm/ipi.h>
40 #include <asm/smp.h>
41 #include <asm/x86_init.h>
42 #include <asm/nmi.h>
43
44 DEFINE_PER_CPU(int, x2apic_extra_bits);
45
46 static enum uv_system_type uv_system_type;
47 static bool uv_hubless_system;
48 static u64 gru_start_paddr, gru_end_paddr;
49 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
50 static u64 gru_dist_lmask, gru_dist_umask;
51 static union uvh_apicid uvh_apicid;
52
53 /* Information derived from CPUID: */
54 static struct {
55 unsigned int apicid_shift;
56 unsigned int apicid_mask;
57 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
58 unsigned int pnode_mask;
59 unsigned int gpa_shift;
60 unsigned int gnode_shift;
61 } uv_cpuid;
62
63 int uv_min_hub_revision_id;
64 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
65
66 unsigned int uv_apicid_hibits;
67 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
68
69 static struct apic apic_x2apic_uv_x;
70 static struct uv_hub_info_s uv_hub_info_node0;
71
72 /* Set this to use hardware error handler instead of kernel panic: */
73 static int disable_uv_undefined_panic = 1;
74
75 unsigned long uv_undefined(char *str)
76 {
77 if (likely(!disable_uv_undefined_panic))
78 panic("UV: error: undefined MMR: %s\n", str);
79 else
80 pr_crit("UV: error: undefined MMR: %s\n", str);
81
82 /* Cause a machine fault: */
83 return ~0ul;
84 }
85 EXPORT_SYMBOL(uv_undefined);
86
87 static unsigned long __init uv_early_read_mmr(unsigned long addr)
88 {
89 unsigned long val, *mmr;
90
91 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
92 val = *mmr;
93 early_iounmap(mmr, sizeof(*mmr));
94
95 return val;
96 }
97
98 static inline bool is_GRU_range(u64 start, u64 end)
99 {
100 if (gru_dist_base) {
101 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */
102 u64 sl = start & gru_dist_lmask; /* Base offset bits */
103 u64 eu = end & gru_dist_umask;
104 u64 el = end & gru_dist_lmask;
105
106 /* Must reside completely within a single GRU range: */
107 return (sl == gru_dist_base && el == gru_dist_base &&
108 su >= gru_first_node_paddr &&
109 su <= gru_last_node_paddr &&
110 eu == su);
111 } else {
112 return start >= gru_start_paddr && end <= gru_end_paddr;
113 }
114 }
115
116 static bool uv_is_untracked_pat_range(u64 start, u64 end)
117 {
118 return is_ISA_range(start, end) || is_GRU_range(start, end);
119 }
120
121 static int __init early_get_pnodeid(void)
122 {
123 union uvh_node_id_u node_id;
124 union uvh_rh_gam_config_mmr_u m_n_config;
125 int pnode;
126
127 /* Currently, all blades have same revision number */
128 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
129 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
130 uv_min_hub_revision_id = node_id.s.revision;
131
132 switch (node_id.s.part_number) {
133 case UV2_HUB_PART_NUMBER:
134 case UV2_HUB_PART_NUMBER_X:
135 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
136 break;
137 case UV3_HUB_PART_NUMBER:
138 case UV3_HUB_PART_NUMBER_X:
139 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
140 break;
141 case UV4_HUB_PART_NUMBER:
142 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
143 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
144 break;
145 }
146
147 uv_hub_info->hub_revision = uv_min_hub_revision_id;
148 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
149 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
150 uv_cpuid.gpa_shift = 46; /* Default unless changed */
151
152 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
153 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
154 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
155 return pnode;
156 }
157
158 static void __init uv_tsc_check_sync(void)
159 {
160 u64 mmr;
161 int sync_state;
162 int mmr_shift;
163 char *state;
164 bool valid;
165
166 /* Accommodate different UV arch BIOSes */
167 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
168 mmr_shift =
169 is_uv1_hub() ? 0 :
170 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
171 if (mmr_shift)
172 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
173 else
174 sync_state = 0;
175
176 switch (sync_state) {
177 case UVH_TSC_SYNC_VALID:
178 state = "in sync";
179 valid = true;
180 break;
181
182 case UVH_TSC_SYNC_INVALID:
183 state = "unstable";
184 valid = false;
185 break;
186 default:
187 state = "unknown: assuming valid";
188 valid = true;
189 break;
190 }
191 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
192
193 /* Mark flag that says TSC != 0 is valid for socket 0 */
194 if (valid)
195 mark_tsc_async_resets("UV BIOS");
196 else
197 mark_tsc_unstable("UV BIOS");
198 }
199
200 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
201
202 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
203 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
204 #define SMT_TYPE 1
205 #define CORE_TYPE 2
206 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
207 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
208
209 static void set_x2apic_bits(void)
210 {
211 unsigned int eax, ebx, ecx, edx, sub_index;
212 unsigned int sid_shift;
213
214 cpuid(0, &eax, &ebx, &ecx, &edx);
215 if (eax < 0xb) {
216 pr_info("UV: CPU does not have CPUID.11\n");
217 return;
218 }
219
220 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
221 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
222 pr_info("UV: CPUID.11 not implemented\n");
223 return;
224 }
225
226 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
227 sub_index = 1;
228 do {
229 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
230 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
231 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
232 break;
233 }
234 sub_index++;
235 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
236
237 uv_cpuid.apicid_shift = 0;
238 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
239 uv_cpuid.socketid_shift = sid_shift;
240 }
241
242 static void __init early_get_apic_socketid_shift(void)
243 {
244 if (is_uv2_hub() || is_uv3_hub())
245 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
246
247 set_x2apic_bits();
248
249 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
250 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
251 }
252
253 /*
254 * Add an extra bit as dictated by bios to the destination apicid of
255 * interrupts potentially passing through the UV HUB. This prevents
256 * a deadlock between interrupts and IO port operations.
257 */
258 static void __init uv_set_apicid_hibit(void)
259 {
260 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
261
262 if (is_uv1_hub()) {
263 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
264 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
265 }
266 }
267
268 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
269 {
270 int pnodeid;
271 int uv_apic;
272
273 if (strncmp(oem_id, "SGI", 3) != 0) {
274 if (strncmp(oem_id, "NSGI", 4) == 0) {
275 uv_hubless_system = true;
276 pr_info("UV: OEM IDs %s/%s, HUBLESS\n",
277 oem_id, oem_table_id);
278 }
279 return 0;
280 }
281
282 if (numa_off) {
283 pr_err("UV: NUMA is off, disabling UV support\n");
284 return 0;
285 }
286
287 /* Set up early hub type field in uv_hub_info for Node 0 */
288 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
289
290 /*
291 * Determine UV arch type.
292 * SGI: UV100/1000
293 * SGI2: UV2000/3000
294 * SGI3: UV300 (truncated to 4 chars because of different varieties)
295 * SGI4: UV400 (truncated to 4 chars because of different varieties)
296 */
297 uv_hub_info->hub_revision =
298 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
299 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
300 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
301 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
302
303 if (uv_hub_info->hub_revision == 0)
304 goto badbios;
305
306 pnodeid = early_get_pnodeid();
307 early_get_apic_socketid_shift();
308
309 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
310 x86_platform.nmi_init = uv_nmi_init;
311
312 if (!strcmp(oem_table_id, "UVX")) {
313 /* This is the most common hardware variant: */
314 uv_system_type = UV_X2APIC;
315 uv_apic = 0;
316
317 } else if (!strcmp(oem_table_id, "UVH")) {
318 /* Only UV1 systems: */
319 uv_system_type = UV_NON_UNIQUE_APIC;
320 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
321 uv_set_apicid_hibit();
322 uv_apic = 1;
323
324 } else if (!strcmp(oem_table_id, "UVL")) {
325 /* Only used for very small systems: */
326 uv_system_type = UV_LEGACY_APIC;
327 uv_apic = 0;
328
329 } else {
330 goto badbios;
331 }
332
333 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
334 uv_tsc_check_sync();
335
336 return uv_apic;
337
338 badbios:
339 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
340 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
341 BUG();
342 }
343
344 enum uv_system_type get_uv_system_type(void)
345 {
346 return uv_system_type;
347 }
348
349 int is_uv_system(void)
350 {
351 return uv_system_type != UV_NONE;
352 }
353 EXPORT_SYMBOL_GPL(is_uv_system);
354
355 int is_uv_hubless(void)
356 {
357 return uv_hubless_system;
358 }
359 EXPORT_SYMBOL_GPL(is_uv_hubless);
360
361 void **__uv_hub_info_list;
362 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
363
364 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
365 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
366
367 short uv_possible_blades;
368 EXPORT_SYMBOL_GPL(uv_possible_blades);
369
370 unsigned long sn_rtc_cycles_per_second;
371 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
372
373 /* The following values are used for the per node hub info struct */
374 static __initdata unsigned short *_node_to_pnode;
375 static __initdata unsigned short _min_socket, _max_socket;
376 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
377 static __initdata struct uv_gam_range_entry *uv_gre_table;
378 static __initdata struct uv_gam_parameters *uv_gp_table;
379 static __initdata unsigned short *_socket_to_node;
380 static __initdata unsigned short *_socket_to_pnode;
381 static __initdata unsigned short *_pnode_to_socket;
382
383 static __initdata struct uv_gam_range_s *_gr_table;
384
385 #define SOCK_EMPTY ((unsigned short)~0)
386
387 extern int uv_hub_info_version(void)
388 {
389 return UV_HUB_INFO_VERSION;
390 }
391 EXPORT_SYMBOL(uv_hub_info_version);
392
393 /* Default UV memory block size is 2GB */
394 static unsigned long mem_block_size = (2UL << 30);
395
396 static __init int adj_blksize(u32 lgre)
397 {
398 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
399 unsigned long size;
400
401 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
402 if (IS_ALIGNED(base, size))
403 break;
404
405 if (size >= mem_block_size)
406 return 0;
407
408 mem_block_size = size;
409 return 1;
410 }
411
412 static __init void set_block_size(void)
413 {
414 unsigned int order = ffs(mem_block_size);
415
416 if (order) {
417 /* adjust for ffs return of 1..64 */
418 set_memory_block_size_order(order - 1);
419 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
420 } else {
421 /* bad or zero value, default to 1UL << 31 (2GB) */
422 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
423 set_memory_block_size_order(31);
424 }
425 }
426
427 /* Build GAM range lookup table: */
428 static __init void build_uv_gr_table(void)
429 {
430 struct uv_gam_range_entry *gre = uv_gre_table;
431 struct uv_gam_range_s *grt;
432 unsigned long last_limit = 0, ram_limit = 0;
433 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
434
435 if (!gre)
436 return;
437
438 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
439 grt = kzalloc(bytes, GFP_KERNEL);
440 BUG_ON(!grt);
441 _gr_table = grt;
442
443 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
444 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
445 if (!ram_limit) {
446 /* Mark hole between RAM/non-RAM: */
447 ram_limit = last_limit;
448 last_limit = gre->limit;
449 lsid++;
450 continue;
451 }
452 last_limit = gre->limit;
453 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
454 continue;
455 }
456 if (_max_socket < gre->sockid) {
457 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
458 continue;
459 }
460 sid = gre->sockid - _min_socket;
461 if (lsid < sid) {
462 /* New range: */
463 grt = &_gr_table[indx];
464 grt->base = lindx;
465 grt->nasid = gre->nasid;
466 grt->limit = last_limit = gre->limit;
467 lsid = sid;
468 lindx = indx++;
469 continue;
470 }
471 /* Update range: */
472 if (lsid == sid && !ram_limit) {
473 /* .. if contiguous: */
474 if (grt->limit == last_limit) {
475 grt->limit = last_limit = gre->limit;
476 continue;
477 }
478 }
479 /* Non-contiguous RAM range: */
480 if (!ram_limit) {
481 grt++;
482 grt->base = lindx;
483 grt->nasid = gre->nasid;
484 grt->limit = last_limit = gre->limit;
485 continue;
486 }
487 /* Non-contiguous/non-RAM: */
488 grt++;
489 /* base is this entry */
490 grt->base = grt - _gr_table;
491 grt->nasid = gre->nasid;
492 grt->limit = last_limit = gre->limit;
493 lsid++;
494 }
495
496 /* Shorten table if possible */
497 grt++;
498 i = grt - _gr_table;
499 if (i < _gr_table_len) {
500 void *ret;
501
502 bytes = i * sizeof(struct uv_gam_range_s);
503 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
504 if (ret) {
505 _gr_table = ret;
506 _gr_table_len = i;
507 }
508 }
509
510 /* Display resultant GAM range table: */
511 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
512 unsigned long start, end;
513 int gb = grt->base;
514
515 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
516 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
517
518 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
519 }
520 }
521
522 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
523 {
524 unsigned long val;
525 int pnode;
526
527 pnode = uv_apicid_to_pnode(phys_apicid);
528 phys_apicid |= uv_apicid_hibits;
529
530 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
531 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
532 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
533 APIC_DM_INIT;
534
535 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
536
537 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
538 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
539 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
540 APIC_DM_STARTUP;
541
542 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
543
544 return 0;
545 }
546
547 static void uv_send_IPI_one(int cpu, int vector)
548 {
549 unsigned long apicid;
550 int pnode;
551
552 apicid = per_cpu(x86_cpu_to_apicid, cpu);
553 pnode = uv_apicid_to_pnode(apicid);
554 uv_hub_send_ipi(pnode, apicid, vector);
555 }
556
557 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
558 {
559 unsigned int cpu;
560
561 for_each_cpu(cpu, mask)
562 uv_send_IPI_one(cpu, vector);
563 }
564
565 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
566 {
567 unsigned int this_cpu = smp_processor_id();
568 unsigned int cpu;
569
570 for_each_cpu(cpu, mask) {
571 if (cpu != this_cpu)
572 uv_send_IPI_one(cpu, vector);
573 }
574 }
575
576 static void uv_send_IPI_allbutself(int vector)
577 {
578 unsigned int this_cpu = smp_processor_id();
579 unsigned int cpu;
580
581 for_each_online_cpu(cpu) {
582 if (cpu != this_cpu)
583 uv_send_IPI_one(cpu, vector);
584 }
585 }
586
587 static void uv_send_IPI_all(int vector)
588 {
589 uv_send_IPI_mask(cpu_online_mask, vector);
590 }
591
592 static int uv_apic_id_valid(u32 apicid)
593 {
594 return 1;
595 }
596
597 static int uv_apic_id_registered(void)
598 {
599 return 1;
600 }
601
602 static void uv_init_apic_ldr(void)
603 {
604 }
605
606 static u32 apic_uv_calc_apicid(unsigned int cpu)
607 {
608 return apic_default_calc_apicid(cpu) | uv_apicid_hibits;
609 }
610
611 static unsigned int x2apic_get_apic_id(unsigned long x)
612 {
613 unsigned int id;
614
615 WARN_ON(preemptible() && num_online_cpus() > 1);
616 id = x | __this_cpu_read(x2apic_extra_bits);
617
618 return id;
619 }
620
621 static u32 set_apic_id(unsigned int id)
622 {
623 /* CHECKME: Do we need to mask out the xapic extra bits? */
624 return id;
625 }
626
627 static unsigned int uv_read_apic_id(void)
628 {
629 return x2apic_get_apic_id(apic_read(APIC_ID));
630 }
631
632 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
633 {
634 return uv_read_apic_id() >> index_msb;
635 }
636
637 static void uv_send_IPI_self(int vector)
638 {
639 apic_write(APIC_SELF_IPI, vector);
640 }
641
642 static int uv_probe(void)
643 {
644 return apic == &apic_x2apic_uv_x;
645 }
646
647 static struct apic apic_x2apic_uv_x __ro_after_init = {
648
649 .name = "UV large system",
650 .probe = uv_probe,
651 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
652 .apic_id_valid = uv_apic_id_valid,
653 .apic_id_registered = uv_apic_id_registered,
654
655 .irq_delivery_mode = dest_Fixed,
656 .irq_dest_mode = 0, /* Physical */
657
658 .disable_esr = 0,
659 .dest_logical = APIC_DEST_LOGICAL,
660 .check_apicid_used = NULL,
661
662 .init_apic_ldr = uv_init_apic_ldr,
663
664 .ioapic_phys_id_map = NULL,
665 .setup_apic_routing = NULL,
666 .cpu_present_to_apicid = default_cpu_present_to_apicid,
667 .apicid_to_cpu_present = NULL,
668 .check_phys_apicid_present = default_check_phys_apicid_present,
669 .phys_pkg_id = uv_phys_pkg_id,
670
671 .get_apic_id = x2apic_get_apic_id,
672 .set_apic_id = set_apic_id,
673
674 .calc_dest_apicid = apic_uv_calc_apicid,
675
676 .send_IPI = uv_send_IPI_one,
677 .send_IPI_mask = uv_send_IPI_mask,
678 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
679 .send_IPI_allbutself = uv_send_IPI_allbutself,
680 .send_IPI_all = uv_send_IPI_all,
681 .send_IPI_self = uv_send_IPI_self,
682
683 .wakeup_secondary_cpu = uv_wakeup_secondary,
684 .inquire_remote_apic = NULL,
685
686 .read = native_apic_msr_read,
687 .write = native_apic_msr_write,
688 .eoi_write = native_apic_msr_eoi_write,
689 .icr_read = native_x2apic_icr_read,
690 .icr_write = native_x2apic_icr_write,
691 .wait_icr_idle = native_x2apic_wait_icr_idle,
692 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
693 };
694
695 static void set_x2apic_extra_bits(int pnode)
696 {
697 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
698 }
699
700 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
701 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
702
703 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
704 {
705 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
706 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
707 unsigned long m_redirect;
708 unsigned long m_overlay;
709 int i;
710
711 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
712 switch (i) {
713 case 0:
714 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
715 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
716 break;
717 case 1:
718 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
719 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
720 break;
721 case 2:
722 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
723 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
724 break;
725 }
726 alias.v = uv_read_local_mmr(m_overlay);
727 if (alias.s.enable && alias.s.base == 0) {
728 *size = (1UL << alias.s.m_alias);
729 redirect.v = uv_read_local_mmr(m_redirect);
730 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
731 return;
732 }
733 }
734 *base = *size = 0;
735 }
736
737 enum map_type {map_wb, map_uc};
738
739 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
740 {
741 unsigned long bytes, paddr;
742
743 paddr = base << pshift;
744 bytes = (1UL << bshift) * (max_pnode + 1);
745 if (!paddr) {
746 pr_info("UV: Map %s_HI base address NULL\n", id);
747 return;
748 }
749 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
750 if (map_type == map_uc)
751 init_extra_mapping_uc(paddr, bytes);
752 else
753 init_extra_mapping_wb(paddr, bytes);
754 }
755
756 static __init void map_gru_distributed(unsigned long c)
757 {
758 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
759 u64 paddr;
760 unsigned long bytes;
761 int nid;
762
763 gru.v = c;
764
765 /* Only base bits 42:28 relevant in dist mode */
766 gru_dist_base = gru.v & 0x000007fff0000000UL;
767 if (!gru_dist_base) {
768 pr_info("UV: Map GRU_DIST base address NULL\n");
769 return;
770 }
771
772 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
773 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
774 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
775 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
776
777 for_each_online_node(nid) {
778 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
779 gru_dist_base;
780 init_extra_mapping_wb(paddr, bytes);
781 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
782 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
783 }
784
785 /* Save upper (63:M) bits of address only for is_GRU_range */
786 gru_first_node_paddr &= gru_dist_umask;
787 gru_last_node_paddr &= gru_dist_umask;
788
789 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
790 }
791
792 static __init void map_gru_high(int max_pnode)
793 {
794 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
795 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
796 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
797 unsigned long base;
798
799 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
800 if (!gru.s.enable) {
801 pr_info("UV: GRU disabled\n");
802 return;
803 }
804
805 if (is_uv3_hub() && gru.s3.mode) {
806 map_gru_distributed(gru.v);
807 return;
808 }
809
810 base = (gru.v & mask) >> shift;
811 map_high("GRU", base, shift, shift, max_pnode, map_wb);
812 gru_start_paddr = ((u64)base << shift);
813 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
814 }
815
816 static __init void map_mmr_high(int max_pnode)
817 {
818 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
819 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
820
821 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
822 if (mmr.s.enable)
823 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
824 else
825 pr_info("UV: MMR disabled\n");
826 }
827
828 /*
829 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
830 * and REDIRECT MMR regs are exactly the same on UV3.
831 */
832 struct mmioh_config {
833 unsigned long overlay;
834 unsigned long redirect;
835 char *id;
836 };
837
838 static __initdata struct mmioh_config mmiohs[] = {
839 {
840 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
841 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
842 "MMIOH0"
843 },
844 {
845 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
846 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
847 "MMIOH1"
848 },
849 };
850
851 /* UV3 & UV4 have identical MMIOH overlay configs */
852 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
853 {
854 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
855 unsigned long mmr;
856 unsigned long base;
857 int i, n, shift, m_io, max_io;
858 int nasid, lnasid, fi, li;
859 char *id;
860
861 id = mmiohs[index].id;
862 overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
863
864 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", id, overlay.v, overlay.s3.base, overlay.s3.m_io);
865 if (!overlay.s3.enable) {
866 pr_info("UV: %s disabled\n", id);
867 return;
868 }
869
870 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
871 base = (unsigned long)overlay.s3.base;
872 m_io = overlay.s3.m_io;
873 mmr = mmiohs[index].redirect;
874 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
875 /* Convert to NASID: */
876 min_pnode *= 2;
877 max_pnode *= 2;
878 max_io = lnasid = fi = li = -1;
879
880 for (i = 0; i < n; i++) {
881 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
882
883 redirect.v = uv_read_local_mmr(mmr + i * 8);
884 nasid = redirect.s3.nasid;
885 /* Invalid NASID: */
886 if (nasid < min_pnode || max_pnode < nasid)
887 nasid = -1;
888
889 if (nasid == lnasid) {
890 li = i;
891 /* Last entry check: */
892 if (i != n-1)
893 continue;
894 }
895
896 /* Check if we have a cached (or last) redirect to print: */
897 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
898 unsigned long addr1, addr2;
899 int f, l;
900
901 if (lnasid == -1) {
902 f = l = i;
903 lnasid = nasid;
904 } else {
905 f = fi;
906 l = li;
907 }
908 addr1 = (base << shift) + f * (1ULL << m_io);
909 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
910 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
911 if (max_io < l)
912 max_io = l;
913 }
914 fi = li = i;
915 lnasid = nasid;
916 }
917
918 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
919
920 if (max_io >= 0)
921 map_high(id, base, shift, m_io, max_io, map_uc);
922 }
923
924 static __init void map_mmioh_high(int min_pnode, int max_pnode)
925 {
926 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
927 unsigned long mmr, base;
928 int shift, enable, m_io, n_io;
929
930 if (is_uv3_hub() || is_uv4_hub()) {
931 /* Map both MMIOH regions: */
932 map_mmioh_high_uv3(0, min_pnode, max_pnode);
933 map_mmioh_high_uv3(1, min_pnode, max_pnode);
934 return;
935 }
936
937 if (is_uv1_hub()) {
938 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
939 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
940 mmioh.v = uv_read_local_mmr(mmr);
941 enable = !!mmioh.s1.enable;
942 base = mmioh.s1.base;
943 m_io = mmioh.s1.m_io;
944 n_io = mmioh.s1.n_io;
945 } else if (is_uv2_hub()) {
946 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
947 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
948 mmioh.v = uv_read_local_mmr(mmr);
949 enable = !!mmioh.s2.enable;
950 base = mmioh.s2.base;
951 m_io = mmioh.s2.m_io;
952 n_io = mmioh.s2.n_io;
953 } else {
954 return;
955 }
956
957 if (enable) {
958 max_pnode &= (1 << n_io) - 1;
959 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
960 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
961 } else {
962 pr_info("UV: MMIOH disabled\n");
963 }
964 }
965
966 static __init void map_low_mmrs(void)
967 {
968 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
969 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
970 }
971
972 static __init void uv_rtc_init(void)
973 {
974 long status;
975 u64 ticks_per_sec;
976
977 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
978
979 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
980 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
981
982 /* BIOS gives wrong value for clock frequency, so guess: */
983 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
984 } else {
985 sn_rtc_cycles_per_second = ticks_per_sec;
986 }
987 }
988
989 /*
990 * percpu heartbeat timer
991 */
992 static void uv_heartbeat(struct timer_list *timer)
993 {
994 unsigned char bits = uv_scir_info->state;
995
996 /* Flip heartbeat bit: */
997 bits ^= SCIR_CPU_HEARTBEAT;
998
999 /* Is this CPU idle? */
1000 if (idle_cpu(raw_smp_processor_id()))
1001 bits &= ~SCIR_CPU_ACTIVITY;
1002 else
1003 bits |= SCIR_CPU_ACTIVITY;
1004
1005 /* Update system controller interface reg: */
1006 uv_set_scir_bits(bits);
1007
1008 /* Enable next timer period: */
1009 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
1010 }
1011
1012 static int uv_heartbeat_enable(unsigned int cpu)
1013 {
1014 while (!uv_cpu_scir_info(cpu)->enabled) {
1015 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
1016
1017 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
1018 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
1019 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
1020 add_timer_on(timer, cpu);
1021 uv_cpu_scir_info(cpu)->enabled = 1;
1022
1023 /* Also ensure that boot CPU is enabled: */
1024 cpu = 0;
1025 }
1026 return 0;
1027 }
1028
1029 #ifdef CONFIG_HOTPLUG_CPU
1030 static int uv_heartbeat_disable(unsigned int cpu)
1031 {
1032 if (uv_cpu_scir_info(cpu)->enabled) {
1033 uv_cpu_scir_info(cpu)->enabled = 0;
1034 del_timer(&uv_cpu_scir_info(cpu)->timer);
1035 }
1036 uv_set_cpu_scir_bits(cpu, 0xff);
1037 return 0;
1038 }
1039
1040 static __init void uv_scir_register_cpu_notifier(void)
1041 {
1042 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
1043 uv_heartbeat_enable, uv_heartbeat_disable);
1044 }
1045
1046 #else /* !CONFIG_HOTPLUG_CPU */
1047
1048 static __init void uv_scir_register_cpu_notifier(void)
1049 {
1050 }
1051
1052 static __init int uv_init_heartbeat(void)
1053 {
1054 int cpu;
1055
1056 if (is_uv_system()) {
1057 for_each_online_cpu(cpu)
1058 uv_heartbeat_enable(cpu);
1059 }
1060
1061 return 0;
1062 }
1063
1064 late_initcall(uv_init_heartbeat);
1065
1066 #endif /* !CONFIG_HOTPLUG_CPU */
1067
1068 /* Direct Legacy VGA I/O traffic to designated IOH */
1069 int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1070 {
1071 int domain, bus, rc;
1072
1073 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1074 return 0;
1075
1076 if ((command_bits & PCI_COMMAND_IO) == 0)
1077 return 0;
1078
1079 domain = pci_domain_nr(pdev->bus);
1080 bus = pdev->bus->number;
1081
1082 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1083
1084 return rc;
1085 }
1086
1087 /*
1088 * Called on each CPU to initialize the per_cpu UV data area.
1089 * FIXME: hotplug not supported yet
1090 */
1091 void uv_cpu_init(void)
1092 {
1093 /* CPU 0 initialization will be done via uv_system_init. */
1094 if (smp_processor_id() == 0)
1095 return;
1096
1097 uv_hub_info->nr_online_cpus++;
1098
1099 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1100 set_x2apic_extra_bits(uv_hub_info->pnode);
1101 }
1102
1103 struct mn {
1104 unsigned char m_val;
1105 unsigned char n_val;
1106 unsigned char m_shift;
1107 unsigned char n_lshift;
1108 };
1109
1110 static void get_mn(struct mn *mnp)
1111 {
1112 union uvh_rh_gam_config_mmr_u m_n_config;
1113 union uv3h_gr0_gam_gr_config_u m_gr_config;
1114
1115 /* Make sure the whole structure is well initialized: */
1116 memset(mnp, 0, sizeof(*mnp));
1117
1118 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1119 mnp->n_val = m_n_config.s.n_skt;
1120
1121 if (is_uv4_hub()) {
1122 mnp->m_val = 0;
1123 mnp->n_lshift = 0;
1124 } else if (is_uv3_hub()) {
1125 mnp->m_val = m_n_config.s3.m_skt;
1126 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1127 mnp->n_lshift = m_gr_config.s3.m_skt;
1128 } else if (is_uv2_hub()) {
1129 mnp->m_val = m_n_config.s2.m_skt;
1130 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1131 } else if (is_uv1_hub()) {
1132 mnp->m_val = m_n_config.s1.m_skt;
1133 mnp->n_lshift = mnp->m_val;
1134 }
1135 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1136 }
1137
1138 void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1139 {
1140 union uvh_node_id_u node_id;
1141 struct mn mn;
1142
1143 get_mn(&mn);
1144 hi->gpa_mask = mn.m_val ?
1145 (1UL << (mn.m_val + mn.n_val)) - 1 :
1146 (1UL << uv_cpuid.gpa_shift) - 1;
1147
1148 hi->m_val = mn.m_val;
1149 hi->n_val = mn.n_val;
1150 hi->m_shift = mn.m_shift;
1151 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1152 hi->hub_revision = uv_hub_info->hub_revision;
1153 hi->pnode_mask = uv_cpuid.pnode_mask;
1154 hi->min_pnode = _min_pnode;
1155 hi->min_socket = _min_socket;
1156 hi->pnode_to_socket = _pnode_to_socket;
1157 hi->socket_to_node = _socket_to_node;
1158 hi->socket_to_pnode = _socket_to_pnode;
1159 hi->gr_table_len = _gr_table_len;
1160 hi->gr_table = _gr_table;
1161
1162 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1163 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1164 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1165 if (mn.m_val)
1166 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1167
1168 if (uv_gp_table) {
1169 hi->global_mmr_base = uv_gp_table->mmr_base;
1170 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1171 hi->global_gru_base = uv_gp_table->gru_base;
1172 hi->global_gru_shift = uv_gp_table->gru_shift;
1173 hi->gpa_shift = uv_gp_table->gpa_shift;
1174 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1175 } else {
1176 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1177 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1178 }
1179
1180 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1181
1182 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1183
1184 /* Show system specific info: */
1185 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1186 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1187 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1188 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1189 }
1190
1191 static void __init decode_gam_params(unsigned long ptr)
1192 {
1193 uv_gp_table = (struct uv_gam_parameters *)ptr;
1194
1195 pr_info("UV: GAM Params...\n");
1196 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1197 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1198 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1199 uv_gp_table->gpa_shift);
1200 }
1201
1202 static void __init decode_gam_rng_tbl(unsigned long ptr)
1203 {
1204 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1205 unsigned long lgre = 0;
1206 int index = 0;
1207 int sock_min = 999999, pnode_min = 99999;
1208 int sock_max = -1, pnode_max = -1;
1209
1210 uv_gre_table = gre;
1211 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1212 unsigned long size = ((unsigned long)(gre->limit - lgre)
1213 << UV_GAM_RANGE_SHFT);
1214 int order = 0;
1215 char suffix[] = " KMGTPE";
1216 int flag = ' ';
1217
1218 while (size > 9999 && order < sizeof(suffix)) {
1219 size /= 1024;
1220 order++;
1221 }
1222
1223 /* adjust max block size to current range start */
1224 if (gre->type == 1 || gre->type == 2)
1225 if (adj_blksize(lgre))
1226 flag = '*';
1227
1228 if (!index) {
1229 pr_info("UV: GAM Range Table...\n");
1230 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1231 }
1232 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1233 index++,
1234 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1235 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1236 flag, size, suffix[order],
1237 gre->type, gre->nasid, gre->sockid, gre->pnode);
1238
1239 /* update to next range start */
1240 lgre = gre->limit;
1241 if (sock_min > gre->sockid)
1242 sock_min = gre->sockid;
1243 if (sock_max < gre->sockid)
1244 sock_max = gre->sockid;
1245 if (pnode_min > gre->pnode)
1246 pnode_min = gre->pnode;
1247 if (pnode_max < gre->pnode)
1248 pnode_max = gre->pnode;
1249 }
1250 _min_socket = sock_min;
1251 _max_socket = sock_max;
1252 _min_pnode = pnode_min;
1253 _max_pnode = pnode_max;
1254 _gr_table_len = index;
1255
1256 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1257 }
1258
1259 static int __init decode_uv_systab(void)
1260 {
1261 struct uv_systab *st;
1262 int i;
1263
1264 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1265 return 0; /* No extended UVsystab required */
1266
1267 st = uv_systab;
1268 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1269 int rev = st ? st->revision : 0;
1270
1271 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1272 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1273 uv_system_type = UV_NONE;
1274
1275 return -EINVAL;
1276 }
1277
1278 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1279 unsigned long ptr = st->entry[i].offset;
1280
1281 if (!ptr)
1282 continue;
1283
1284 ptr = ptr + (unsigned long)st;
1285
1286 switch (st->entry[i].type) {
1287 case UV_SYSTAB_TYPE_GAM_PARAMS:
1288 decode_gam_params(ptr);
1289 break;
1290
1291 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1292 decode_gam_rng_tbl(ptr);
1293 break;
1294 }
1295 }
1296 return 0;
1297 }
1298
1299 /*
1300 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1301 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1302 * .. being replaced by GAM Range Table
1303 */
1304 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1305 {
1306 int i, uv_pb = 0;
1307
1308 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1309 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1310 unsigned long np;
1311
1312 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1313 if (np)
1314 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1315
1316 uv_pb += hweight64(np);
1317 }
1318 if (uv_possible_blades != uv_pb)
1319 uv_possible_blades = uv_pb;
1320 }
1321
1322 static void __init build_socket_tables(void)
1323 {
1324 struct uv_gam_range_entry *gre = uv_gre_table;
1325 int num, nump;
1326 int cpu, i, lnid;
1327 int minsock = _min_socket;
1328 int maxsock = _max_socket;
1329 int minpnode = _min_pnode;
1330 int maxpnode = _max_pnode;
1331 size_t bytes;
1332
1333 if (!gre) {
1334 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1335 pr_info("UV: No UVsystab socket table, ignoring\n");
1336 return;
1337 }
1338 pr_crit("UV: Error: UVsystab address translations not available!\n");
1339 BUG();
1340 }
1341
1342 /* Build socket id -> node id, pnode */
1343 num = maxsock - minsock + 1;
1344 bytes = num * sizeof(_socket_to_node[0]);
1345 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1346 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1347
1348 nump = maxpnode - minpnode + 1;
1349 bytes = nump * sizeof(_pnode_to_socket[0]);
1350 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1351 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1352
1353 for (i = 0; i < num; i++)
1354 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1355
1356 for (i = 0; i < nump; i++)
1357 _pnode_to_socket[i] = SOCK_EMPTY;
1358
1359 /* Fill in pnode/node/addr conversion list values: */
1360 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1361 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1362 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1363 continue;
1364 i = gre->sockid - minsock;
1365 /* Duplicate: */
1366 if (_socket_to_pnode[i] != SOCK_EMPTY)
1367 continue;
1368 _socket_to_pnode[i] = gre->pnode;
1369
1370 i = gre->pnode - minpnode;
1371 _pnode_to_socket[i] = gre->sockid;
1372
1373 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1374 gre->sockid, gre->type, gre->nasid,
1375 _socket_to_pnode[gre->sockid - minsock],
1376 _pnode_to_socket[gre->pnode - minpnode]);
1377 }
1378
1379 /* Set socket -> node values: */
1380 lnid = -1;
1381 for_each_present_cpu(cpu) {
1382 int nid = cpu_to_node(cpu);
1383 int apicid, sockid;
1384
1385 if (lnid == nid)
1386 continue;
1387 lnid = nid;
1388 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1389 sockid = apicid >> uv_cpuid.socketid_shift;
1390 _socket_to_node[sockid - minsock] = nid;
1391 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1392 sockid, apicid, nid);
1393 }
1394
1395 /* Set up physical blade to pnode translation from GAM Range Table: */
1396 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1397 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1398 BUG_ON(!_node_to_pnode);
1399
1400 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1401 unsigned short sockid;
1402
1403 for (sockid = minsock; sockid <= maxsock; sockid++) {
1404 if (lnid == _socket_to_node[sockid - minsock]) {
1405 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1406 break;
1407 }
1408 }
1409 if (sockid > maxsock) {
1410 pr_err("UV: socket for node %d not found!\n", lnid);
1411 BUG();
1412 }
1413 }
1414
1415 /*
1416 * If socket id == pnode or socket id == node for all nodes,
1417 * system runs faster by removing corresponding conversion table.
1418 */
1419 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1420 if (minsock == 0) {
1421 for (i = 0; i < num; i++)
1422 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1423 break;
1424 if (i >= num) {
1425 kfree(_socket_to_node);
1426 _socket_to_node = NULL;
1427 pr_info("UV: 1:1 socket_to_node table removed\n");
1428 }
1429 }
1430 if (minsock == minpnode) {
1431 for (i = 0; i < num; i++)
1432 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1433 _socket_to_pnode[i] != i + minpnode)
1434 break;
1435 if (i >= num) {
1436 kfree(_socket_to_pnode);
1437 _socket_to_pnode = NULL;
1438 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1439 }
1440 }
1441 }
1442
1443 static void __init uv_system_init_hub(void)
1444 {
1445 struct uv_hub_info_s hub_info = {0};
1446 int bytes, cpu, nodeid;
1447 unsigned short min_pnode = 9999, max_pnode = 0;
1448 char *hub = is_uv4_hub() ? "UV400" :
1449 is_uv3_hub() ? "UV300" :
1450 is_uv2_hub() ? "UV2000/3000" :
1451 is_uv1_hub() ? "UV100/1000" : NULL;
1452
1453 if (!hub) {
1454 pr_err("UV: Unknown/unsupported UV hub\n");
1455 return;
1456 }
1457 pr_info("UV: Found %s hub\n", hub);
1458
1459 map_low_mmrs();
1460
1461 /* Get uv_systab for decoding: */
1462 uv_bios_init();
1463
1464 /* If there's an UVsystab problem then abort UV init: */
1465 if (decode_uv_systab() < 0)
1466 return;
1467
1468 build_socket_tables();
1469 build_uv_gr_table();
1470 set_block_size();
1471 uv_init_hub_info(&hub_info);
1472 uv_possible_blades = num_possible_nodes();
1473 if (!_node_to_pnode)
1474 boot_init_possible_blades(&hub_info);
1475
1476 /* uv_num_possible_blades() is really the hub count: */
1477 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1478
1479 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1480 hub_info.coherency_domain_number = sn_coherency_id;
1481 uv_rtc_init();
1482
1483 bytes = sizeof(void *) * uv_num_possible_blades();
1484 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1485 BUG_ON(!__uv_hub_info_list);
1486
1487 bytes = sizeof(struct uv_hub_info_s);
1488 for_each_node(nodeid) {
1489 struct uv_hub_info_s *new_hub;
1490
1491 if (__uv_hub_info_list[nodeid]) {
1492 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1493 BUG();
1494 }
1495
1496 /* Allocate new per hub info list */
1497 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1498 BUG_ON(!new_hub);
1499 __uv_hub_info_list[nodeid] = new_hub;
1500 new_hub = uv_hub_info_list(nodeid);
1501 BUG_ON(!new_hub);
1502 *new_hub = hub_info;
1503
1504 /* Use information from GAM table if available: */
1505 if (_node_to_pnode)
1506 new_hub->pnode = _node_to_pnode[nodeid];
1507 else /* Or fill in during CPU loop: */
1508 new_hub->pnode = 0xffff;
1509
1510 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1511 new_hub->memory_nid = -1;
1512 new_hub->nr_possible_cpus = 0;
1513 new_hub->nr_online_cpus = 0;
1514 }
1515
1516 /* Initialize per CPU info: */
1517 for_each_possible_cpu(cpu) {
1518 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1519 int numa_node_id;
1520 unsigned short pnode;
1521
1522 nodeid = cpu_to_node(cpu);
1523 numa_node_id = numa_cpu_node(cpu);
1524 pnode = uv_apicid_to_pnode(apicid);
1525
1526 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1527 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1528 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1529 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1530
1531 /* Init memoryless node: */
1532 if (nodeid != numa_node_id &&
1533 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1534 uv_hub_info_list(numa_node_id)->pnode = pnode;
1535 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1536 uv_cpu_hub_info(cpu)->pnode = pnode;
1537
1538 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1539 }
1540
1541 for_each_node(nodeid) {
1542 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1543
1544 /* Add pnode info for pre-GAM list nodes without CPUs: */
1545 if (pnode == 0xffff) {
1546 unsigned long paddr;
1547
1548 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1549 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1550 uv_hub_info_list(nodeid)->pnode = pnode;
1551 }
1552 min_pnode = min(pnode, min_pnode);
1553 max_pnode = max(pnode, max_pnode);
1554 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1555 nodeid,
1556 uv_hub_info_list(nodeid)->pnode,
1557 uv_hub_info_list(nodeid)->nr_possible_cpus);
1558 }
1559
1560 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1561 map_gru_high(max_pnode);
1562 map_mmr_high(max_pnode);
1563 map_mmioh_high(min_pnode, max_pnode);
1564
1565 uv_nmi_setup();
1566 uv_cpu_init();
1567 uv_scir_register_cpu_notifier();
1568 proc_mkdir("sgi_uv", NULL);
1569
1570 /* Register Legacy VGA I/O redirection handler: */
1571 pci_register_set_vga_state(uv_set_vga_state);
1572
1573 /*
1574 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1575 * EFI is not enabled in the kdump kernel:
1576 */
1577 if (is_kdump_kernel())
1578 reboot_type = BOOT_ACPI;
1579 }
1580
1581 /*
1582 * There is a small amount of UV specific code needed to initialize a
1583 * UV system that does not have a "UV HUB" (referred to as "hubless").
1584 */
1585 void __init uv_system_init(void)
1586 {
1587 if (likely(!is_uv_system() && !is_uv_hubless()))
1588 return;
1589
1590 if (is_uv_system())
1591 uv_system_init_hub();
1592 else
1593 uv_nmi_setup_hubless();
1594 }
1595
1596 apic_driver(apic_x2apic_uv_x);
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