2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
34 #include <linux/smp.h>
35 #include <linux/nmi.h>
36 #include <linux/timex.h>
38 #include <asm/atomic.h>
40 #include <asm/mpspec.h>
42 #include <asm/arch_hooks.h>
44 #include <asm/pgalloc.h>
45 #include <asm/i8253.h>
47 #include <asm/proto.h>
49 #include <asm/i8259.h>
52 #include <mach_apic.h>
53 #include <mach_apicdef.h>
59 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
60 # error SPURIOUS_APIC_VECTOR definition error
65 * Knob to control our willingness to enable the local APIC.
69 static int force_enable_local_apic
;
71 * APIC command line parameters
73 static int __init
parse_lapic(char *arg
)
75 force_enable_local_apic
= 1;
78 early_param("lapic", parse_lapic
);
79 /* Local APIC was disabled by the BIOS and enabled by the kernel */
80 static int enabled_via_apicbase
;
85 static int apic_calibrate_pmtmr __initdata
;
86 static __init
int setup_apicpmtimer(char *s
)
88 apic_calibrate_pmtmr
= 1;
92 __setup("apicpmtimer", setup_apicpmtimer
);
101 /* x2apic enabled before OS handover */
102 static int x2apic_preenabled
;
103 static int disable_x2apic
;
104 static __init
int setup_nox2apic(char *str
)
107 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
110 early_param("nox2apic", setup_nox2apic
);
113 unsigned long mp_lapic_addr
;
115 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
116 static int disable_apic_timer __cpuinitdata
;
117 /* Local APIC timer works in C2 */
118 int local_apic_timer_c2_ok
;
119 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
121 int first_system_vector
= 0xfe;
124 * Debug level, exported for io_apic.c
126 unsigned int apic_verbosity
;
130 /* Have we found an MP table */
131 int smp_found_config
;
133 static struct resource lapic_resource
= {
134 .name
= "Local APIC",
135 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
138 static unsigned int calibration_result
;
140 static int lapic_next_event(unsigned long delta
,
141 struct clock_event_device
*evt
);
142 static void lapic_timer_setup(enum clock_event_mode mode
,
143 struct clock_event_device
*evt
);
144 static void lapic_timer_broadcast(const struct cpumask
*mask
);
145 static void apic_pm_activate(void);
148 * The local apic timer can be used for any function which is CPU local.
150 static struct clock_event_device lapic_clockevent
= {
152 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
155 .set_mode
= lapic_timer_setup
,
156 .set_next_event
= lapic_next_event
,
157 .broadcast
= lapic_timer_broadcast
,
161 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
163 static unsigned long apic_phys
;
166 * Get the LAPIC version
168 static inline int lapic_get_version(void)
170 return GET_APIC_VERSION(apic_read(APIC_LVR
));
174 * Check, if the APIC is integrated or a separate chip
176 static inline int lapic_is_integrated(void)
181 return APIC_INTEGRATED(lapic_get_version());
186 * Check, whether this is a modern or a first generation APIC
188 static int modern_apic(void)
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
192 boot_cpu_data
.x86
>= 0xf)
194 return lapic_get_version() >= 0x14;
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
202 void xapic_wait_icr_idle(void)
204 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
208 u32
safe_xapic_wait_icr_idle(void)
215 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
219 } while (timeout
++ < 1000);
224 void xapic_icr_write(u32 low
, u32 id
)
226 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
227 apic_write(APIC_ICR
, low
);
230 static u64
xapic_icr_read(void)
234 icr2
= apic_read(APIC_ICR2
);
235 icr1
= apic_read(APIC_ICR
);
237 return icr1
| ((u64
)icr2
<< 32);
240 static struct apic_ops xapic_ops
= {
241 .read
= native_apic_mem_read
,
242 .write
= native_apic_mem_write
,
243 .icr_read
= xapic_icr_read
,
244 .icr_write
= xapic_icr_write
,
245 .wait_icr_idle
= xapic_wait_icr_idle
,
246 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
249 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
250 EXPORT_SYMBOL_GPL(apic_ops
);
253 static void x2apic_wait_icr_idle(void)
255 /* no need to wait for icr idle in x2apic */
259 static u32
safe_x2apic_wait_icr_idle(void)
261 /* no need to wait for icr idle in x2apic */
265 void x2apic_icr_write(u32 low
, u32 id
)
267 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
270 static u64
x2apic_icr_read(void)
274 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
278 static struct apic_ops x2apic_ops
= {
279 .read
= native_apic_msr_read
,
280 .write
= native_apic_msr_write
,
281 .icr_read
= x2apic_icr_read
,
282 .icr_write
= x2apic_icr_write
,
283 .wait_icr_idle
= x2apic_wait_icr_idle
,
284 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
291 void __cpuinit
enable_NMI_through_LVT0(void)
295 /* unmask and set to NMI */
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v
|= APIC_LVT_LEVEL_TRIGGER
;
302 apic_write(APIC_LVT0
, v
);
307 * get_physical_broadcast - Get number of physical broadcast IDs
309 int get_physical_broadcast(void)
311 return modern_apic() ? 0xff : 0xf;
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
318 int lapic_get_maxlvt(void)
322 v
= apic_read(APIC_LVR
);
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
327 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
335 #define APIC_DIVISOR 16
338 * This function sets up the local APIC timer, with a timeout of
339 * 'clocks' APIC bus clock. During calibration we actually call
340 * this function twice on the boot CPU, once with a bogus timeout
341 * value, second time for real. The other (noncalibrating) CPUs
342 * call this function only once, with the real, calibrated value.
344 * We do reads before writes even if unnecessary, to get around the
345 * P5 APIC double write bug.
347 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
349 unsigned int lvtt_value
, tmp_value
;
351 lvtt_value
= LOCAL_TIMER_VECTOR
;
353 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
354 if (!lapic_is_integrated())
355 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
358 lvtt_value
|= APIC_LVT_MASKED
;
360 apic_write(APIC_LVTT
, lvtt_value
);
365 tmp_value
= apic_read(APIC_TDCR
);
366 apic_write(APIC_TDCR
,
367 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
371 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
375 * Setup extended LVT, AMD specific (K8, family 10h)
377 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
378 * MCE interrupts are supported. Thus MCE offset must be set to 0.
380 * If mask=1, the LVT entry does not generate interrupts while mask=0
381 * enables the vector. See also the BKDGs.
384 #define APIC_EILVT_LVTOFF_MCE 0
385 #define APIC_EILVT_LVTOFF_IBS 1
387 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
389 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
390 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
395 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
397 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
398 return APIC_EILVT_LVTOFF_MCE
;
401 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
403 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
404 return APIC_EILVT_LVTOFF_IBS
;
406 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
409 * Program the next event, relative to now
411 static int lapic_next_event(unsigned long delta
,
412 struct clock_event_device
*evt
)
414 apic_write(APIC_TMICT
, delta
);
419 * Setup the lapic timer in periodic or oneshot mode
421 static void lapic_timer_setup(enum clock_event_mode mode
,
422 struct clock_event_device
*evt
)
427 /* Lapic used as dummy for broadcast ? */
428 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
431 local_irq_save(flags
);
434 case CLOCK_EVT_MODE_PERIODIC
:
435 case CLOCK_EVT_MODE_ONESHOT
:
436 __setup_APIC_LVTT(calibration_result
,
437 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
439 case CLOCK_EVT_MODE_UNUSED
:
440 case CLOCK_EVT_MODE_SHUTDOWN
:
441 v
= apic_read(APIC_LVTT
);
442 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
443 apic_write(APIC_LVTT
, v
);
444 apic_write(APIC_TMICT
, 0xffffffff);
446 case CLOCK_EVT_MODE_RESUME
:
447 /* Nothing to do here */
451 local_irq_restore(flags
);
455 * Local APIC timer broadcast function
457 static void lapic_timer_broadcast(const struct cpumask
*mask
)
460 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
465 * Setup the local APIC timer for this CPU. Copy the initilized values
466 * of the boot CPU and register the clock event in the framework.
468 static void __cpuinit
setup_APIC_timer(void)
470 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
472 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
473 levt
->cpumask
= cpumask_of(smp_processor_id());
475 clockevents_register_device(levt
);
479 * In this functions we calibrate APIC bus clocks to the external timer.
481 * We want to do the calibration only once since we want to have local timer
482 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
485 * This was previously done by reading the PIT/HPET and waiting for a wrap
486 * around to find out, that a tick has elapsed. I have a box, where the PIT
487 * readout is broken, so it never gets out of the wait loop again. This was
488 * also reported by others.
490 * Monitoring the jiffies value is inaccurate and the clockevents
491 * infrastructure allows us to do a simple substitution of the interrupt
494 * The calibration routine also uses the pm_timer when possible, as the PIT
495 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
496 * back to normal later in the boot process).
499 #define LAPIC_CAL_LOOPS (HZ/10)
501 static __initdata
int lapic_cal_loops
= -1;
502 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
503 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
504 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
505 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
508 * Temporary interrupt handler.
510 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
512 unsigned long long tsc
= 0;
513 long tapic
= apic_read(APIC_TMCCT
);
514 unsigned long pm
= acpi_pm_read_early();
519 switch (lapic_cal_loops
++) {
521 lapic_cal_t1
= tapic
;
522 lapic_cal_tsc1
= tsc
;
524 lapic_cal_j1
= jiffies
;
527 case LAPIC_CAL_LOOPS
:
528 lapic_cal_t2
= tapic
;
529 lapic_cal_tsc2
= tsc
;
530 if (pm
< lapic_cal_pm1
)
531 pm
+= ACPI_PM_OVRRUN
;
533 lapic_cal_j2
= jiffies
;
539 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
541 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
542 const long pm_thresh
= pm_100ms
/ 100;
546 #ifndef CONFIG_X86_PM_TIMER
550 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
552 /* Check, if the PM timer is available */
556 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
558 if (deltapm
> (pm_100ms
- pm_thresh
) &&
559 deltapm
< (pm_100ms
+ pm_thresh
)) {
560 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
564 res
= (((u64
)deltapm
) * mult
) >> 22;
565 do_div(res
, 1000000);
566 pr_warning("APIC calibration not consistent "
567 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
569 /* Correct the lapic counter value */
570 res
= (((u64
)(*delta
)) * pm_100ms
);
571 do_div(res
, deltapm
);
572 pr_info("APIC delta adjusted to PM-Timer: "
573 "%lu (%ld)\n", (unsigned long)res
, *delta
);
576 /* Correct the tsc counter value */
578 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
579 do_div(res
, deltapm
);
580 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
581 "PM-Timer: %lu (%ld) \n",
582 (unsigned long)res
, *deltatsc
);
583 *deltatsc
= (long)res
;
589 static int __init
calibrate_APIC_clock(void)
591 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
592 void (*real_handler
)(struct clock_event_device
*dev
);
593 unsigned long deltaj
;
594 long delta
, deltatsc
;
595 int pm_referenced
= 0;
599 /* Replace the global interrupt handler */
600 real_handler
= global_clock_event
->event_handler
;
601 global_clock_event
->event_handler
= lapic_cal_handler
;
604 * Setup the APIC counter to maximum. There is no way the lapic
605 * can underflow in the 100ms detection time frame
607 __setup_APIC_LVTT(0xffffffff, 0, 0);
609 /* Let the interrupts run */
612 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
617 /* Restore the real event handler */
618 global_clock_event
->event_handler
= real_handler
;
620 /* Build delta t1-t2 as apic timer counts down */
621 delta
= lapic_cal_t1
- lapic_cal_t2
;
622 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
624 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
626 /* we trust the PM based calibration if possible */
627 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
630 /* Calculate the scaled math multiplication factor */
631 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
632 lapic_clockevent
.shift
);
633 lapic_clockevent
.max_delta_ns
=
634 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
635 lapic_clockevent
.min_delta_ns
=
636 clockevent_delta2ns(0xF, &lapic_clockevent
);
638 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
640 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
641 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
642 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
646 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
648 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
649 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
652 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
654 calibration_result
/ (1000000 / HZ
),
655 calibration_result
% (1000000 / HZ
));
658 * Do a sanity check on the APIC calibration result
660 if (calibration_result
< (1000000 / HZ
)) {
662 pr_warning("APIC frequency too slow, disabling apic timer\n");
666 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
669 * PM timer calibration failed or not turned on
670 * so lets try APIC timer based calibration
672 if (!pm_referenced
) {
673 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
676 * Setup the apic timer manually
678 levt
->event_handler
= lapic_cal_handler
;
679 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
680 lapic_cal_loops
= -1;
682 /* Let the interrupts run */
685 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
688 /* Stop the lapic timer */
689 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
692 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
693 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
695 /* Check, if the jiffies result is consistent */
696 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
697 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
699 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
703 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
704 pr_warning("APIC timer disabled due to verification failure\n");
712 * Setup the boot APIC
714 * Calibrate and verify the result.
716 void __init
setup_boot_APIC_clock(void)
719 * The local apic timer can be disabled via the kernel
720 * commandline or from the CPU detection code. Register the lapic
721 * timer as a dummy clock event source on SMP systems, so the
722 * broadcast mechanism is used. On UP systems simply ignore it.
724 if (disable_apic_timer
) {
725 pr_info("Disabling APIC timer\n");
726 /* No broadcast on UP ! */
727 if (num_possible_cpus() > 1) {
728 lapic_clockevent
.mult
= 1;
734 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
735 "calibrating APIC timer ...\n");
737 if (calibrate_APIC_clock()) {
738 /* No broadcast on UP ! */
739 if (num_possible_cpus() > 1)
745 * If nmi_watchdog is set to IO_APIC, we need the
746 * PIT/HPET going. Otherwise register lapic as a dummy
749 if (nmi_watchdog
!= NMI_IO_APIC
)
750 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
752 pr_warning("APIC timer registered as dummy,"
753 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
755 /* Setup the lapic or request the broadcast */
759 void __cpuinit
setup_secondary_APIC_clock(void)
765 * The guts of the apic timer interrupt
767 static void local_apic_timer_interrupt(void)
769 int cpu
= smp_processor_id();
770 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
773 * Normally we should not be here till LAPIC has been initialized but
774 * in some cases like kdump, its possible that there is a pending LAPIC
775 * timer interrupt from previous kernel's context and is delivered in
776 * new kernel the moment interrupts are enabled.
778 * Interrupts are enabled early and LAPIC is setup much later, hence
779 * its possible that when we get here evt->event_handler is NULL.
780 * Check for event_handler being NULL and discard the interrupt as
783 if (!evt
->event_handler
) {
784 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
786 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
791 * the NMI deadlock-detector uses this.
793 inc_irq_stat(apic_timer_irqs
);
795 evt
->event_handler(evt
);
799 * Local APIC timer interrupt. This is the most natural way for doing
800 * local interrupts, but local timer interrupts can be emulated by
801 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
803 * [ if a single-CPU system runs an SMP kernel then we call the local
804 * interrupt as well. Thus we cannot inline the local irq ... ]
806 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
808 struct pt_regs
*old_regs
= set_irq_regs(regs
);
811 * NOTE! We'd better ACK the irq immediately,
812 * because timer handling can be slow.
816 * update_process_times() expects us to have done irq_enter().
817 * Besides, if we don't timer interrupts ignore the global
818 * interrupt lock, which is the WrongThing (tm) to do.
822 local_apic_timer_interrupt();
825 set_irq_regs(old_regs
);
828 int setup_profiling_timer(unsigned int multiplier
)
834 * Local APIC start and shutdown
838 * clear_local_APIC - shutdown the local APIC
840 * This is called, when a CPU is disabled and before rebooting, so the state of
841 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
842 * leftovers during boot.
844 void clear_local_APIC(void)
849 /* APIC hasn't been mapped yet */
853 maxlvt
= lapic_get_maxlvt();
855 * Masking an LVT entry can trigger a local APIC error
856 * if the vector is zero. Mask LVTERR first to prevent this.
859 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
860 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
863 * Careful: we have to set masks only first to deassert
864 * any level-triggered sources.
866 v
= apic_read(APIC_LVTT
);
867 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
868 v
= apic_read(APIC_LVT0
);
869 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
870 v
= apic_read(APIC_LVT1
);
871 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
873 v
= apic_read(APIC_LVTPC
);
874 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
877 /* lets not touch this if we didn't frob it */
878 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
880 v
= apic_read(APIC_LVTTHMR
);
881 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
885 * Clean APIC state for other OSs:
887 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
888 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
889 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
891 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
893 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
895 /* Integrated APIC (!82489DX) ? */
896 if (lapic_is_integrated()) {
898 /* Clear ESR due to Pentium errata 3AP and 11AP */
899 apic_write(APIC_ESR
, 0);
905 * disable_local_APIC - clear and disable the local APIC
907 void disable_local_APIC(void)
911 /* APIC hasn't been mapped yet */
918 * Disable APIC (implies clearing of registers
921 value
= apic_read(APIC_SPIV
);
922 value
&= ~APIC_SPIV_APIC_ENABLED
;
923 apic_write(APIC_SPIV
, value
);
927 * When LAPIC was disabled by the BIOS and enabled by the kernel,
928 * restore the disabled state.
930 if (enabled_via_apicbase
) {
933 rdmsr(MSR_IA32_APICBASE
, l
, h
);
934 l
&= ~MSR_IA32_APICBASE_ENABLE
;
935 wrmsr(MSR_IA32_APICBASE
, l
, h
);
941 * If Linux enabled the LAPIC against the BIOS default disable it down before
942 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
943 * not power-off. Additionally clear all LVT entries before disable_local_APIC
944 * for the case where Linux didn't enable the LAPIC.
946 void lapic_shutdown(void)
953 local_irq_save(flags
);
956 if (!enabled_via_apicbase
)
960 disable_local_APIC();
963 local_irq_restore(flags
);
967 * This is to verify that we're looking at a real local APIC.
968 * Check these against your board if the CPUs aren't getting
969 * started for no apparent reason.
971 int __init
verify_local_APIC(void)
973 unsigned int reg0
, reg1
;
976 * The version register is read-only in a real APIC.
978 reg0
= apic_read(APIC_LVR
);
979 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
980 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
981 reg1
= apic_read(APIC_LVR
);
982 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
985 * The two version reads above should print the same
986 * numbers. If the second one is different, then we
987 * poke at a non-APIC.
993 * Check if the version looks reasonably.
995 reg1
= GET_APIC_VERSION(reg0
);
996 if (reg1
== 0x00 || reg1
== 0xff)
998 reg1
= lapic_get_maxlvt();
999 if (reg1
< 0x02 || reg1
== 0xff)
1003 * The ID register is read/write in a real APIC.
1005 reg0
= apic_read(APIC_ID
);
1006 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1007 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
1008 reg1
= apic_read(APIC_ID
);
1009 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1010 apic_write(APIC_ID
, reg0
);
1011 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1015 * The next two are just to see if we have sane values.
1016 * They're only really relevant if we're in Virtual Wire
1017 * compatibility mode, but most boxes are anymore.
1019 reg0
= apic_read(APIC_LVT0
);
1020 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1021 reg1
= apic_read(APIC_LVT1
);
1022 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1028 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1030 void __init
sync_Arb_IDs(void)
1033 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1036 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1042 apic_wait_icr_idle();
1044 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1045 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1046 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1050 * An initial setup of the virtual wire mode.
1052 void __init
init_bsp_APIC(void)
1057 * Don't do the setup now if we have a SMP BIOS as the
1058 * through-I/O-APIC virtual wire mode might be active.
1060 if (smp_found_config
|| !cpu_has_apic
)
1064 * Do not trust the local APIC being empty at bootup.
1071 value
= apic_read(APIC_SPIV
);
1072 value
&= ~APIC_VECTOR_MASK
;
1073 value
|= APIC_SPIV_APIC_ENABLED
;
1075 #ifdef CONFIG_X86_32
1076 /* This bit is reserved on P4/Xeon and should be cleared */
1077 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1078 (boot_cpu_data
.x86
== 15))
1079 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1082 value
|= APIC_SPIV_FOCUS_DISABLED
;
1083 value
|= SPURIOUS_APIC_VECTOR
;
1084 apic_write(APIC_SPIV
, value
);
1087 * Set up the virtual wire mode.
1089 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1090 value
= APIC_DM_NMI
;
1091 if (!lapic_is_integrated()) /* 82489DX */
1092 value
|= APIC_LVT_LEVEL_TRIGGER
;
1093 apic_write(APIC_LVT1
, value
);
1096 static void __cpuinit
lapic_setup_esr(void)
1098 unsigned int oldvalue
, value
, maxlvt
;
1100 if (!lapic_is_integrated()) {
1101 pr_info("No ESR for 82489DX.\n");
1107 * Something untraceable is creating bad interrupts on
1108 * secondary quads ... for the moment, just leave the
1109 * ESR disabled - we can't do anything useful with the
1110 * errors anyway - mbligh
1112 pr_info("Leaving ESR disabled.\n");
1116 maxlvt
= lapic_get_maxlvt();
1117 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1118 apic_write(APIC_ESR
, 0);
1119 oldvalue
= apic_read(APIC_ESR
);
1121 /* enables sending errors */
1122 value
= ERROR_APIC_VECTOR
;
1123 apic_write(APIC_LVTERR
, value
);
1126 * spec says clear errors after enabling vector.
1129 apic_write(APIC_ESR
, 0);
1130 value
= apic_read(APIC_ESR
);
1131 if (value
!= oldvalue
)
1132 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1133 "vector: 0x%08x after: 0x%08x\n",
1139 * setup_local_APIC - setup the local APIC
1141 void __cpuinit
setup_local_APIC(void)
1146 #ifdef CONFIG_X86_32
1147 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1148 if (lapic_is_integrated() && esr_disable
) {
1149 apic_write(APIC_ESR
, 0);
1150 apic_write(APIC_ESR
, 0);
1151 apic_write(APIC_ESR
, 0);
1152 apic_write(APIC_ESR
, 0);
1159 * Double-check whether this APIC is really registered.
1160 * This is meaningless in clustered apic mode, so we skip it.
1162 if (!apic_id_registered())
1166 * Intel recommends to set DFR, LDR and TPR before enabling
1167 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1168 * document number 292116). So here it goes...
1173 * Set Task Priority to 'accept all'. We never change this
1176 value
= apic_read(APIC_TASKPRI
);
1177 value
&= ~APIC_TPRI_MASK
;
1178 apic_write(APIC_TASKPRI
, value
);
1181 * After a crash, we no longer service the interrupts and a pending
1182 * interrupt from previous kernel might still have ISR bit set.
1184 * Most probably by now CPU has serviced that pending interrupt and
1185 * it might not have done the ack_APIC_irq() because it thought,
1186 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1187 * does not clear the ISR bit and cpu thinks it has already serivced
1188 * the interrupt. Hence a vector might get locked. It was noticed
1189 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1191 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1192 value
= apic_read(APIC_ISR
+ i
*0x10);
1193 for (j
= 31; j
>= 0; j
--) {
1200 * Now that we are all set up, enable the APIC
1202 value
= apic_read(APIC_SPIV
);
1203 value
&= ~APIC_VECTOR_MASK
;
1207 value
|= APIC_SPIV_APIC_ENABLED
;
1209 #ifdef CONFIG_X86_32
1211 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1212 * certain networking cards. If high frequency interrupts are
1213 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1214 * entry is masked/unmasked at a high rate as well then sooner or
1215 * later IOAPIC line gets 'stuck', no more interrupts are received
1216 * from the device. If focus CPU is disabled then the hang goes
1219 * [ This bug can be reproduced easily with a level-triggered
1220 * PCI Ne2000 networking cards and PII/PIII processors, dual
1224 * Actually disabling the focus CPU check just makes the hang less
1225 * frequent as it makes the interrupt distributon model be more
1226 * like LRU than MRU (the short-term load is more even across CPUs).
1227 * See also the comment in end_level_ioapic_irq(). --macro
1231 * - enable focus processor (bit==0)
1232 * - 64bit mode always use processor focus
1233 * so no need to set it
1235 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1239 * Set spurious IRQ vector
1241 value
|= SPURIOUS_APIC_VECTOR
;
1242 apic_write(APIC_SPIV
, value
);
1245 * Set up LVT0, LVT1:
1247 * set up through-local-APIC on the BP's LINT0. This is not
1248 * strictly necessary in pure symmetric-IO mode, but sometimes
1249 * we delegate interrupts to the 8259A.
1252 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1254 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1255 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1256 value
= APIC_DM_EXTINT
;
1257 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1258 smp_processor_id());
1260 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1261 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1262 smp_processor_id());
1264 apic_write(APIC_LVT0
, value
);
1267 * only the BP should see the LINT1 NMI signal, obviously.
1269 if (!smp_processor_id())
1270 value
= APIC_DM_NMI
;
1272 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1273 if (!lapic_is_integrated()) /* 82489DX */
1274 value
|= APIC_LVT_LEVEL_TRIGGER
;
1275 apic_write(APIC_LVT1
, value
);
1280 void __cpuinit
end_local_APIC_setup(void)
1284 #ifdef CONFIG_X86_32
1287 /* Disable the local apic timer */
1288 value
= apic_read(APIC_LVTT
);
1289 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1290 apic_write(APIC_LVTT
, value
);
1294 setup_apic_nmi_watchdog(NULL
);
1299 void check_x2apic(void)
1303 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1305 if (msr
& X2APIC_ENABLE
) {
1306 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1307 x2apic_preenabled
= x2apic
= 1;
1308 apic_ops
= &x2apic_ops
;
1312 void enable_x2apic(void)
1316 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1317 if (!(msr
& X2APIC_ENABLE
)) {
1318 pr_info("Enabling x2apic\n");
1319 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1323 void __init
enable_IR_x2apic(void)
1325 #ifdef CONFIG_INTR_REMAP
1327 unsigned long flags
;
1329 if (!cpu_has_x2apic
)
1332 if (!x2apic_preenabled
&& disable_x2apic
) {
1333 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1334 "because of nox2apic\n");
1338 if (x2apic_preenabled
&& disable_x2apic
)
1339 panic("Bios already enabled x2apic, can't enforce nox2apic");
1341 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1342 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1343 "because of skipping io-apic setup\n");
1347 ret
= dmar_table_init();
1349 pr_info("dmar_table_init() failed with %d:\n", ret
);
1351 if (x2apic_preenabled
)
1352 panic("x2apic enabled by bios. But IR enabling failed");
1354 pr_info("Not enabling x2apic,Intr-remapping\n");
1358 local_irq_save(flags
);
1361 ret
= save_mask_IO_APIC_setup();
1363 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1367 ret
= enable_intr_remapping(1);
1369 if (ret
&& x2apic_preenabled
) {
1370 local_irq_restore(flags
);
1371 panic("x2apic enabled by bios. But IR enabling failed");
1379 apic_ops
= &x2apic_ops
;
1386 * IR enabling failed
1388 restore_IO_APIC_setup();
1390 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1394 local_irq_restore(flags
);
1397 if (!x2apic_preenabled
)
1398 pr_info("Enabled x2apic and interrupt-remapping\n");
1400 pr_info("Enabled Interrupt-remapping\n");
1402 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1404 if (!cpu_has_x2apic
)
1407 if (x2apic_preenabled
)
1408 panic("x2apic enabled prior OS handover,"
1409 " enable CONFIG_INTR_REMAP");
1411 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1417 #endif /* HAVE_X2APIC */
1419 #ifdef CONFIG_X86_64
1421 * Detect and enable local APICs on non-SMP boards.
1422 * Original code written by Keir Fraser.
1423 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1424 * not correctly set up (usually the APIC timer won't work etc.)
1426 static int __init
detect_init_APIC(void)
1428 if (!cpu_has_apic
) {
1429 pr_info("No local APIC present\n");
1433 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1434 boot_cpu_physical_apicid
= 0;
1439 * Detect and initialize APIC
1441 static int __init
detect_init_APIC(void)
1445 /* Disabled by kernel option? */
1449 switch (boot_cpu_data
.x86_vendor
) {
1450 case X86_VENDOR_AMD
:
1451 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1452 (boot_cpu_data
.x86
== 15))
1455 case X86_VENDOR_INTEL
:
1456 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1457 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1464 if (!cpu_has_apic
) {
1466 * Over-ride BIOS and try to enable the local APIC only if
1467 * "lapic" specified.
1469 if (!force_enable_local_apic
) {
1470 pr_info("Local APIC disabled by BIOS -- "
1471 "you can enable it with \"lapic\"\n");
1475 * Some BIOSes disable the local APIC in the APIC_BASE
1476 * MSR. This can only be done in software for Intel P6 or later
1477 * and AMD K7 (Model > 1) or later.
1479 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1480 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1481 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1482 l
&= ~MSR_IA32_APICBASE_BASE
;
1483 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1484 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1485 enabled_via_apicbase
= 1;
1489 * The APIC feature bit should now be enabled
1492 features
= cpuid_edx(1);
1493 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1494 pr_warning("Could not enable APIC!\n");
1497 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1498 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1500 /* The BIOS may have set up the APIC at some other address */
1501 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1502 if (l
& MSR_IA32_APICBASE_ENABLE
)
1503 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1505 pr_info("Found and enabled local APIC!\n");
1512 pr_info("No local APIC present or hardware disabled\n");
1517 #ifdef CONFIG_X86_64
1518 void __init
early_init_lapic_mapping(void)
1520 unsigned long phys_addr
;
1523 * If no local APIC can be found then go out
1524 * : it means there is no mpatable and MADT
1526 if (!smp_found_config
)
1529 phys_addr
= mp_lapic_addr
;
1531 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1532 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1533 APIC_BASE
, phys_addr
);
1536 * Fetch the APIC ID of the BSP in case we have a
1537 * default configuration (or the MP table is broken).
1539 boot_cpu_physical_apicid
= read_apic_id();
1544 * init_apic_mappings - initialize APIC mappings
1546 void __init
init_apic_mappings(void)
1550 boot_cpu_physical_apicid
= read_apic_id();
1556 * If no local APIC can be found then set up a fake all
1557 * zeroes page to simulate the local APIC and another
1558 * one for the IO-APIC.
1560 if (!smp_found_config
&& detect_init_APIC()) {
1561 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1562 apic_phys
= __pa(apic_phys
);
1564 apic_phys
= mp_lapic_addr
;
1566 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1567 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1568 APIC_BASE
, apic_phys
);
1571 * Fetch the APIC ID of the BSP in case we have a
1572 * default configuration (or the MP table is broken).
1574 if (boot_cpu_physical_apicid
== -1U)
1575 boot_cpu_physical_apicid
= read_apic_id();
1579 * This initializes the IO-APIC and APIC hardware if this is
1582 int apic_version
[MAX_APICS
];
1584 int __init
APIC_init_uniprocessor(void)
1586 #ifdef CONFIG_X86_64
1588 pr_info("Apic disabled\n");
1591 if (!cpu_has_apic
) {
1593 pr_info("Apic disabled by BIOS\n");
1597 if (!smp_found_config
&& !cpu_has_apic
)
1601 * Complain if the BIOS pretends there is one.
1603 if (!cpu_has_apic
&&
1604 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1605 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1606 boot_cpu_physical_apicid
);
1607 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1615 #ifdef CONFIG_X86_64
1616 setup_apic_routing();
1619 verify_local_APIC();
1622 #ifdef CONFIG_X86_64
1623 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1626 * Hack: In case of kdump, after a crash, kernel might be booting
1627 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1628 * might be zero if read from MP tables. Get it from LAPIC.
1630 # ifdef CONFIG_CRASH_DUMP
1631 boot_cpu_physical_apicid
= read_apic_id();
1634 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1637 #ifdef CONFIG_X86_64
1639 * Now enable IO-APICs, actually call clear_IO_APIC
1640 * We need clear_IO_APIC before enabling vector on BP
1642 if (!skip_ioapic_setup
&& nr_ioapics
)
1646 #ifdef CONFIG_X86_IO_APIC
1647 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1649 localise_nmi_watchdog();
1650 end_local_APIC_setup();
1652 #ifdef CONFIG_X86_IO_APIC
1653 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1655 # ifdef CONFIG_X86_64
1661 #ifdef CONFIG_X86_64
1662 setup_boot_APIC_clock();
1663 check_nmi_watchdog();
1672 * Local APIC interrupts
1676 * This interrupt should _never_ happen with our APIC/SMP architecture
1678 void smp_spurious_interrupt(struct pt_regs
*regs
)
1685 * Check if this really is a spurious interrupt and ACK it
1686 * if it is a vectored one. Just in case...
1687 * Spurious interrupts should not be ACKed.
1689 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1690 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1693 inc_irq_stat(irq_spurious_count
);
1695 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1696 pr_info("spurious APIC interrupt on CPU#%d, "
1697 "should never happen.\n", smp_processor_id());
1702 * This interrupt should never happen with our APIC/SMP architecture
1704 void smp_error_interrupt(struct pt_regs
*regs
)
1710 /* First tickle the hardware, only then report what went on. -- REW */
1711 v
= apic_read(APIC_ESR
);
1712 apic_write(APIC_ESR
, 0);
1713 v1
= apic_read(APIC_ESR
);
1715 atomic_inc(&irq_err_count
);
1718 * Here is what the APIC error bits mean:
1720 * 1: Receive CS error
1721 * 2: Send accept error
1722 * 3: Receive accept error
1724 * 5: Send illegal vector
1725 * 6: Received illegal vector
1726 * 7: Illegal register address
1728 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1729 smp_processor_id(), v
, v1
);
1734 * connect_bsp_APIC - attach the APIC to the interrupt system
1736 void __init
connect_bsp_APIC(void)
1738 #ifdef CONFIG_X86_32
1741 * Do not trust the local APIC being empty at bootup.
1745 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1746 * local APIC to INT and NMI lines.
1748 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1749 "enabling APIC mode.\n");
1758 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1759 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1761 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1764 void disconnect_bsp_APIC(int virt_wire_setup
)
1768 #ifdef CONFIG_X86_32
1771 * Put the board back into PIC mode (has an effect only on
1772 * certain older boards). Note that APIC interrupts, including
1773 * IPIs, won't work beyond this point! The only exception are
1776 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1777 "entering PIC mode.\n");
1784 /* Go back to Virtual Wire compatibility mode */
1786 /* For the spurious interrupt use vector F, and enable it */
1787 value
= apic_read(APIC_SPIV
);
1788 value
&= ~APIC_VECTOR_MASK
;
1789 value
|= APIC_SPIV_APIC_ENABLED
;
1791 apic_write(APIC_SPIV
, value
);
1793 if (!virt_wire_setup
) {
1795 * For LVT0 make it edge triggered, active high,
1796 * external and enabled
1798 value
= apic_read(APIC_LVT0
);
1799 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1800 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1801 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1802 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1803 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1804 apic_write(APIC_LVT0
, value
);
1807 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1811 * For LVT1 make it edge triggered, active high,
1814 value
= apic_read(APIC_LVT1
);
1815 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1816 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1817 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1818 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1819 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1820 apic_write(APIC_LVT1
, value
);
1823 void __cpuinit
generic_processor_info(int apicid
, int version
)
1830 if (version
== 0x0) {
1831 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1832 "fixing up to 0x10. (tell your hw vendor)\n",
1836 apic_version
[apicid
] = version
;
1838 if (num_processors
>= nr_cpu_ids
) {
1839 int max
= nr_cpu_ids
;
1840 int thiscpu
= max
+ disabled_cpus
;
1843 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1844 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1851 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1853 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1855 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1856 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1858 physid_set(apicid
, phys_cpu_present_map
);
1859 if (apicid
== boot_cpu_physical_apicid
) {
1861 * x86_bios_cpu_apicid is required to have processors listed
1862 * in same order as logical cpu numbers. Hence the first
1863 * entry is BSP, and so on.
1867 if (apicid
> max_physical_apicid
)
1868 max_physical_apicid
= apicid
;
1870 #ifdef CONFIG_X86_32
1872 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1873 * but we need to work other dependencies like SMP_SUSPEND etc
1874 * before this can be done without some confusion.
1875 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1876 * - Ashok Raj <ashok.raj@intel.com>
1878 if (max_physical_apicid
>= 8) {
1879 switch (boot_cpu_data
.x86_vendor
) {
1880 case X86_VENDOR_INTEL
:
1881 if (!APIC_XAPIC(version
)) {
1885 /* If P4 and above fall through */
1886 case X86_VENDOR_AMD
:
1892 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1893 /* are we being called early in kernel startup? */
1894 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1895 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1896 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1898 cpu_to_apicid
[cpu
] = apicid
;
1899 bios_cpu_apicid
[cpu
] = apicid
;
1901 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1902 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1906 set_cpu_possible(cpu
, true);
1907 set_cpu_present(cpu
, true);
1910 #ifdef CONFIG_X86_64
1911 int hard_smp_processor_id(void)
1913 return read_apic_id();
1924 * 'active' is true if the local APIC was enabled by us and
1925 * not the BIOS; this signifies that we are also responsible
1926 * for disabling it before entering apm/acpi suspend
1929 /* r/w apic fields */
1930 unsigned int apic_id
;
1931 unsigned int apic_taskpri
;
1932 unsigned int apic_ldr
;
1933 unsigned int apic_dfr
;
1934 unsigned int apic_spiv
;
1935 unsigned int apic_lvtt
;
1936 unsigned int apic_lvtpc
;
1937 unsigned int apic_lvt0
;
1938 unsigned int apic_lvt1
;
1939 unsigned int apic_lvterr
;
1940 unsigned int apic_tmict
;
1941 unsigned int apic_tdcr
;
1942 unsigned int apic_thmr
;
1945 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1947 unsigned long flags
;
1950 if (!apic_pm_state
.active
)
1953 maxlvt
= lapic_get_maxlvt();
1955 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1956 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1957 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1958 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1959 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1960 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1962 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1963 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1964 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1965 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1966 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1967 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1968 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1970 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1973 local_irq_save(flags
);
1974 disable_local_APIC();
1975 local_irq_restore(flags
);
1979 static int lapic_resume(struct sys_device
*dev
)
1982 unsigned long flags
;
1985 if (!apic_pm_state
.active
)
1988 maxlvt
= lapic_get_maxlvt();
1990 local_irq_save(flags
);
1999 * Make sure the APICBASE points to the right address
2001 * FIXME! This will be wrong if we ever support suspend on
2002 * SMP! We'll need to do this as part of the CPU restore!
2004 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2005 l
&= ~MSR_IA32_APICBASE_BASE
;
2006 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2007 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2010 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2011 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2012 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2013 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2014 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2015 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2016 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2017 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2018 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2020 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2023 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2024 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2025 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2026 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2027 apic_write(APIC_ESR
, 0);
2028 apic_read(APIC_ESR
);
2029 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2030 apic_write(APIC_ESR
, 0);
2031 apic_read(APIC_ESR
);
2033 local_irq_restore(flags
);
2039 * This device has no shutdown method - fully functioning local APICs
2040 * are needed on every CPU up until machine_halt/restart/poweroff.
2043 static struct sysdev_class lapic_sysclass
= {
2045 .resume
= lapic_resume
,
2046 .suspend
= lapic_suspend
,
2049 static struct sys_device device_lapic
= {
2051 .cls
= &lapic_sysclass
,
2054 static void __cpuinit
apic_pm_activate(void)
2056 apic_pm_state
.active
= 1;
2059 static int __init
init_lapic_sysfs(void)
2065 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2067 error
= sysdev_class_register(&lapic_sysclass
);
2069 error
= sysdev_register(&device_lapic
);
2072 device_initcall(init_lapic_sysfs
);
2074 #else /* CONFIG_PM */
2076 static void apic_pm_activate(void) { }
2078 #endif /* CONFIG_PM */
2080 #ifdef CONFIG_X86_64
2082 * apic_is_clustered_box() -- Check if we can expect good TSC
2084 * Thus far, the major user of this is IBM's Summit2 series:
2086 * Clustered boxes may have unsynced TSC problems if they are
2087 * multi-chassis. Use available data to take a good guess.
2088 * If in doubt, go HPET.
2090 __cpuinit
int apic_is_clustered_box(void)
2092 int i
, clusters
, zeros
;
2094 u16
*bios_cpu_apicid
;
2095 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2098 * there is not this kind of box with AMD CPU yet.
2099 * Some AMD box with quadcore cpu and 8 sockets apicid
2100 * will be [4, 0x23] or [8, 0x27] could be thought to
2101 * vsmp box still need checking...
2103 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2106 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2107 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2109 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2110 /* are we being called early in kernel startup? */
2111 if (bios_cpu_apicid
) {
2112 id
= bios_cpu_apicid
[i
];
2113 } else if (i
< nr_cpu_ids
) {
2115 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2121 if (id
!= BAD_APICID
)
2122 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2125 /* Problem: Partially populated chassis may not have CPUs in some of
2126 * the APIC clusters they have been allocated. Only present CPUs have
2127 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2128 * Since clusters are allocated sequentially, count zeros only if
2129 * they are bounded by ones.
2133 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2134 if (test_bit(i
, clustermap
)) {
2135 clusters
+= 1 + zeros
;
2141 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2142 * not guaranteed to be synced between boards
2144 if (is_vsmp_box() && clusters
> 1)
2148 * If clusters > 2, then should be multi-chassis.
2149 * May have to revisit this when multi-core + hyperthreaded CPUs come
2150 * out, but AFAIK this will work even for them.
2152 return (clusters
> 2);
2157 * APIC command line parameters
2159 static int __init
setup_disableapic(char *arg
)
2162 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2165 early_param("disableapic", setup_disableapic
);
2167 /* same as disableapic, for compatibility */
2168 static int __init
setup_nolapic(char *arg
)
2170 return setup_disableapic(arg
);
2172 early_param("nolapic", setup_nolapic
);
2174 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2176 local_apic_timer_c2_ok
= 1;
2179 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2181 static int __init
parse_disable_apic_timer(char *arg
)
2183 disable_apic_timer
= 1;
2186 early_param("noapictimer", parse_disable_apic_timer
);
2188 static int __init
parse_nolapic_timer(char *arg
)
2190 disable_apic_timer
= 1;
2193 early_param("nolapic_timer", parse_nolapic_timer
);
2195 static int __init
apic_set_verbosity(char *arg
)
2198 #ifdef CONFIG_X86_64
2199 skip_ioapic_setup
= 0;
2205 if (strcmp("debug", arg
) == 0)
2206 apic_verbosity
= APIC_DEBUG
;
2207 else if (strcmp("verbose", arg
) == 0)
2208 apic_verbosity
= APIC_VERBOSE
;
2210 pr_warning("APIC Verbosity level %s not recognised"
2211 " use apic=verbose or apic=debug\n", arg
);
2217 early_param("apic", apic_set_verbosity
);
2219 static int __init
lapic_insert_resource(void)
2224 /* Put local APIC into the resource map. */
2225 lapic_resource
.start
= apic_phys
;
2226 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2227 insert_resource(&iomem_resource
, &lapic_resource
);
2233 * need call insert after e820_reserve_resources()
2234 * that is using request_resource
2236 late_initcall(lapic_insert_resource
);