2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
44 #include <mach_apic.h>
46 static int disable_apic_timer __cpuinitdata
;
47 static int apic_calibrate_pmtmr __initdata
;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok
;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
55 * Debug level, exported for io_apic.c
59 /* Have we found an MP table */
62 static struct resource lapic_resource
= {
64 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
67 static unsigned int calibration_result
;
69 static int lapic_next_event(unsigned long delta
,
70 struct clock_event_device
*evt
);
71 static void lapic_timer_setup(enum clock_event_mode mode
,
72 struct clock_event_device
*evt
);
73 static void lapic_timer_broadcast(cpumask_t mask
);
74 static void apic_pm_activate(void);
76 static struct clock_event_device lapic_clockevent
= {
78 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
79 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
81 .set_mode
= lapic_timer_setup
,
82 .set_next_event
= lapic_next_event
,
83 .broadcast
= lapic_timer_broadcast
,
87 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
89 static unsigned long apic_phys
;
91 unsigned long mp_lapic_addr
;
93 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
95 * Get the LAPIC version
97 static inline int lapic_get_version(void)
99 return GET_APIC_VERSION(apic_read(APIC_LVR
));
103 * Check, if the APIC is integrated or a seperate chip
105 static inline int lapic_is_integrated(void)
111 * Check, whether this is a modern or a first generation APIC
113 static int modern_apic(void)
115 /* AMD systems use old APIC versions, so check the CPU */
116 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
117 boot_cpu_data
.x86
>= 0xf)
119 return lapic_get_version() >= 0x14;
122 void apic_wait_icr_idle(void)
124 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
128 u32
safe_apic_wait_icr_idle(void)
135 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
139 } while (timeout
++ < 1000);
145 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
147 void __cpuinit
enable_NMI_through_LVT0(void)
151 /* unmask and set to NMI */
153 apic_write(APIC_LVT0
, v
);
157 * lapic_get_maxlvt - get the maximum number of local vector table entries
159 int lapic_get_maxlvt(void)
161 unsigned int v
, maxlvt
;
163 v
= apic_read(APIC_LVR
);
164 maxlvt
= GET_APIC_MAXLVT(v
);
169 * This function sets up the local APIC timer, with a timeout of
170 * 'clocks' APIC bus clock. During calibration we actually call
171 * this function twice on the boot CPU, once with a bogus timeout
172 * value, second time for real. The other (noncalibrating) CPUs
173 * call this function only once, with the real, calibrated value.
175 * We do reads before writes even if unnecessary, to get around the
176 * P5 APIC double write bug.
179 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
181 unsigned int lvtt_value
, tmp_value
;
183 lvtt_value
= LOCAL_TIMER_VECTOR
;
185 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
187 lvtt_value
|= APIC_LVT_MASKED
;
189 apic_write(APIC_LVTT
, lvtt_value
);
194 tmp_value
= apic_read(APIC_TDCR
);
195 apic_write(APIC_TDCR
, (tmp_value
196 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
200 apic_write(APIC_TMICT
, clocks
);
204 * Setup extended LVT, AMD specific (K8, family 10h)
206 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
207 * MCE interrupts are supported. Thus MCE offset must be set to 0.
210 #define APIC_EILVT_LVTOFF_MCE 0
211 #define APIC_EILVT_LVTOFF_IBS 1
213 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
215 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
216 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
221 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
223 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
224 return APIC_EILVT_LVTOFF_MCE
;
227 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
229 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
230 return APIC_EILVT_LVTOFF_IBS
;
234 * Program the next event, relative to now
236 static int lapic_next_event(unsigned long delta
,
237 struct clock_event_device
*evt
)
239 apic_write(APIC_TMICT
, delta
);
244 * Setup the lapic timer in periodic or oneshot mode
246 static void lapic_timer_setup(enum clock_event_mode mode
,
247 struct clock_event_device
*evt
)
252 /* Lapic used as dummy for broadcast ? */
253 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
256 local_irq_save(flags
);
259 case CLOCK_EVT_MODE_PERIODIC
:
260 case CLOCK_EVT_MODE_ONESHOT
:
261 __setup_APIC_LVTT(calibration_result
,
262 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
264 case CLOCK_EVT_MODE_UNUSED
:
265 case CLOCK_EVT_MODE_SHUTDOWN
:
266 v
= apic_read(APIC_LVTT
);
267 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
268 apic_write(APIC_LVTT
, v
);
270 case CLOCK_EVT_MODE_RESUME
:
271 /* Nothing to do here */
275 local_irq_restore(flags
);
279 * Local APIC timer broadcast function
281 static void lapic_timer_broadcast(cpumask_t mask
)
284 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
289 * Setup the local APIC timer for this CPU. Copy the initilized values
290 * of the boot CPU and register the clock event in the framework.
292 static void setup_APIC_timer(void)
294 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
296 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
297 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
299 clockevents_register_device(levt
);
303 * In this function we calibrate APIC bus clocks to the external
304 * timer. Unfortunately we cannot use jiffies and the timer irq
305 * to calibrate, since some later bootup code depends on getting
306 * the first irq? Ugh.
308 * We want to do the calibration only once since we
309 * want to have local timer irqs syncron. CPUs connected
310 * by the same APIC bus have the very same bus frequency.
311 * And we want to have irqs off anyways, no accidental
315 #define TICK_COUNT 100000000
317 static void __init
calibrate_APIC_clock(void)
319 unsigned apic
, apic_start
;
320 unsigned long tsc
, tsc_start
;
326 * Put whatever arbitrary (but long enough) timeout
327 * value into the APIC clock, we just want to get the
328 * counter running for calibration.
330 * No interrupt enable !
332 __setup_APIC_LVTT(250000000, 0, 0);
334 apic_start
= apic_read(APIC_TMCCT
);
335 #ifdef CONFIG_X86_PM_TIMER
336 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
337 pmtimer_wait(5000); /* 5ms wait */
338 apic
= apic_read(APIC_TMCCT
);
339 result
= (apic_start
- apic
) * 1000L / 5;
346 apic
= apic_read(APIC_TMCCT
);
348 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
349 (apic_start
- apic
) < TICK_COUNT
);
351 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
357 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
359 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
360 result
/ 1000 / 1000, result
/ 1000 % 1000);
362 /* Calculate the scaled math multiplication factor */
363 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
364 lapic_clockevent
.shift
);
365 lapic_clockevent
.max_delta_ns
=
366 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
367 lapic_clockevent
.min_delta_ns
=
368 clockevent_delta2ns(0xF, &lapic_clockevent
);
370 calibration_result
= result
/ HZ
;
374 * Setup the boot APIC
376 * Calibrate and verify the result.
378 void __init
setup_boot_APIC_clock(void)
381 * The local apic timer can be disabled via the kernel commandline.
382 * Register the lapic timer as a dummy clock event source on SMP
383 * systems, so the broadcast mechanism is used. On UP systems simply
386 if (disable_apic_timer
) {
387 printk(KERN_INFO
"Disabling APIC timer\n");
388 /* No broadcast on UP ! */
389 if (num_possible_cpus() > 1) {
390 lapic_clockevent
.mult
= 1;
396 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
397 calibrate_APIC_clock();
400 * Do a sanity check on the APIC calibration result
402 if (calibration_result
< (1000000 / HZ
)) {
404 "APIC frequency too slow, disabling apic timer\n");
405 /* No broadcast on UP ! */
406 if (num_possible_cpus() > 1)
412 * If nmi_watchdog is set to IO_APIC, we need the
413 * PIT/HPET going. Otherwise register lapic as a dummy
416 if (nmi_watchdog
!= NMI_IO_APIC
)
417 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
419 printk(KERN_WARNING
"APIC timer registered as dummy,"
420 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
425 void __cpuinit
setup_secondary_APIC_clock(void)
431 * The guts of the apic timer interrupt
433 static void local_apic_timer_interrupt(void)
435 int cpu
= smp_processor_id();
436 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
439 * Normally we should not be here till LAPIC has been initialized but
440 * in some cases like kdump, its possible that there is a pending LAPIC
441 * timer interrupt from previous kernel's context and is delivered in
442 * new kernel the moment interrupts are enabled.
444 * Interrupts are enabled early and LAPIC is setup much later, hence
445 * its possible that when we get here evt->event_handler is NULL.
446 * Check for event_handler being NULL and discard the interrupt as
449 if (!evt
->event_handler
) {
451 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
453 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
458 * the NMI deadlock-detector uses this.
460 add_pda(apic_timer_irqs
, 1);
462 evt
->event_handler(evt
);
466 * Local APIC timer interrupt. This is the most natural way for doing
467 * local interrupts, but local timer interrupts can be emulated by
468 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
470 * [ if a single-CPU system runs an SMP kernel then we call the local
471 * interrupt as well. Thus we cannot inline the local irq ... ]
473 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
475 struct pt_regs
*old_regs
= set_irq_regs(regs
);
478 * NOTE! We'd better ACK the irq immediately,
479 * because timer handling can be slow.
483 * update_process_times() expects us to have done irq_enter().
484 * Besides, if we don't timer interrupts ignore the global
485 * interrupt lock, which is the WrongThing (tm) to do.
489 local_apic_timer_interrupt();
491 set_irq_regs(old_regs
);
494 int setup_profiling_timer(unsigned int multiplier
)
501 * Local APIC start and shutdown
505 * clear_local_APIC - shutdown the local APIC
507 * This is called, when a CPU is disabled and before rebooting, so the state of
508 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
509 * leftovers during boot.
511 void clear_local_APIC(void)
516 /* APIC hasn't been mapped yet */
520 maxlvt
= lapic_get_maxlvt();
522 * Masking an LVT entry can trigger a local APIC error
523 * if the vector is zero. Mask LVTERR first to prevent this.
526 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
527 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
530 * Careful: we have to set masks only first to deassert
531 * any level-triggered sources.
533 v
= apic_read(APIC_LVTT
);
534 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
535 v
= apic_read(APIC_LVT0
);
536 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
537 v
= apic_read(APIC_LVT1
);
538 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
540 v
= apic_read(APIC_LVTPC
);
541 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
545 * Clean APIC state for other OSs:
547 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
548 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
549 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
551 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
553 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
554 apic_write(APIC_ESR
, 0);
559 * disable_local_APIC - clear and disable the local APIC
561 void disable_local_APIC(void)
568 * Disable APIC (implies clearing of registers
571 value
= apic_read(APIC_SPIV
);
572 value
&= ~APIC_SPIV_APIC_ENABLED
;
573 apic_write(APIC_SPIV
, value
);
576 void lapic_shutdown(void)
583 local_irq_save(flags
);
585 disable_local_APIC();
587 local_irq_restore(flags
);
591 * This is to verify that we're looking at a real local APIC.
592 * Check these against your board if the CPUs aren't getting
593 * started for no apparent reason.
595 int __init
verify_local_APIC(void)
597 unsigned int reg0
, reg1
;
600 * The version register is read-only in a real APIC.
602 reg0
= apic_read(APIC_LVR
);
603 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
604 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
605 reg1
= apic_read(APIC_LVR
);
606 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
609 * The two version reads above should print the same
610 * numbers. If the second one is different, then we
611 * poke at a non-APIC.
617 * Check if the version looks reasonably.
619 reg1
= GET_APIC_VERSION(reg0
);
620 if (reg1
== 0x00 || reg1
== 0xff)
622 reg1
= lapic_get_maxlvt();
623 if (reg1
< 0x02 || reg1
== 0xff)
627 * The ID register is read/write in a real APIC.
629 reg0
= read_apic_id();
630 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
631 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
632 reg1
= read_apic_id();
633 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
634 apic_write(APIC_ID
, reg0
);
635 if (reg1
!= (reg0
^ APIC_ID_MASK
))
639 * The next two are just to see if we have sane values.
640 * They're only really relevant if we're in Virtual Wire
641 * compatibility mode, but most boxes are anymore.
643 reg0
= apic_read(APIC_LVT0
);
644 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
645 reg1
= apic_read(APIC_LVT1
);
646 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
652 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
654 void __init
sync_Arb_IDs(void)
656 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
663 apic_wait_icr_idle();
665 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
666 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
671 * An initial setup of the virtual wire mode.
673 void __init
init_bsp_APIC(void)
678 * Don't do the setup now if we have a SMP BIOS as the
679 * through-I/O-APIC virtual wire mode might be active.
681 if (smp_found_config
|| !cpu_has_apic
)
684 value
= apic_read(APIC_LVR
);
687 * Do not trust the local APIC being empty at bootup.
694 value
= apic_read(APIC_SPIV
);
695 value
&= ~APIC_VECTOR_MASK
;
696 value
|= APIC_SPIV_APIC_ENABLED
;
697 value
|= APIC_SPIV_FOCUS_DISABLED
;
698 value
|= SPURIOUS_APIC_VECTOR
;
699 apic_write(APIC_SPIV
, value
);
702 * Set up the virtual wire mode.
704 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
706 apic_write(APIC_LVT1
, value
);
710 * setup_local_APIC - setup the local APIC
712 void __cpuinit
setup_local_APIC(void)
718 value
= apic_read(APIC_LVR
);
720 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
723 * Double-check whether this APIC is really registered.
724 * This is meaningless in clustered apic mode, so we skip it.
726 if (!apic_id_registered())
730 * Intel recommends to set DFR, LDR and TPR before enabling
731 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
732 * document number 292116). So here it goes...
737 * Set Task Priority to 'accept all'. We never change this
740 value
= apic_read(APIC_TASKPRI
);
741 value
&= ~APIC_TPRI_MASK
;
742 apic_write(APIC_TASKPRI
, value
);
745 * After a crash, we no longer service the interrupts and a pending
746 * interrupt from previous kernel might still have ISR bit set.
748 * Most probably by now CPU has serviced that pending interrupt and
749 * it might not have done the ack_APIC_irq() because it thought,
750 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
751 * does not clear the ISR bit and cpu thinks it has already serivced
752 * the interrupt. Hence a vector might get locked. It was noticed
753 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
755 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
756 value
= apic_read(APIC_ISR
+ i
*0x10);
757 for (j
= 31; j
>= 0; j
--) {
764 * Now that we are all set up, enable the APIC
766 value
= apic_read(APIC_SPIV
);
767 value
&= ~APIC_VECTOR_MASK
;
771 value
|= APIC_SPIV_APIC_ENABLED
;
773 /* We always use processor focus */
776 * Set spurious IRQ vector
778 value
|= SPURIOUS_APIC_VECTOR
;
779 apic_write(APIC_SPIV
, value
);
784 * set up through-local-APIC on the BP's LINT0. This is not
785 * strictly necessary in pure symmetric-IO mode, but sometimes
786 * we delegate interrupts to the 8259A.
789 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
791 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
792 if (!smp_processor_id() && !value
) {
793 value
= APIC_DM_EXTINT
;
794 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
797 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
798 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
801 apic_write(APIC_LVT0
, value
);
804 * only the BP should see the LINT1 NMI signal, obviously.
806 if (!smp_processor_id())
809 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
810 apic_write(APIC_LVT1
, value
);
814 static void __cpuinit
lapic_setup_esr(void)
816 unsigned maxlvt
= lapic_get_maxlvt();
818 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
820 * spec says clear errors after enabling vector.
823 apic_write(APIC_ESR
, 0);
826 void __cpuinit
end_local_APIC_setup(void)
829 setup_apic_nmi_watchdog(NULL
);
834 * Detect and enable local APICs on non-SMP boards.
835 * Original code written by Keir Fraser.
836 * On AMD64 we trust the BIOS - if it says no APIC it is likely
837 * not correctly set up (usually the APIC timer won't work etc.)
839 static int __init
detect_init_APIC(void)
842 printk(KERN_INFO
"No local APIC present\n");
846 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
847 boot_cpu_physical_apicid
= 0;
851 void __init
early_init_lapic_mapping(void)
853 unsigned long phys_addr
;
856 * If no local APIC can be found then go out
857 * : it means there is no mpatable and MADT
859 if (!smp_found_config
)
862 phys_addr
= mp_lapic_addr
;
864 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
865 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
866 APIC_BASE
, phys_addr
);
869 * Fetch the APIC ID of the BSP in case we have a
870 * default configuration (or the MP table is broken).
872 boot_cpu_physical_apicid
= GET_APIC_ID(read_apic_id());
876 * init_apic_mappings - initialize APIC mappings
878 void __init
init_apic_mappings(void)
881 * If no local APIC can be found then set up a fake all
882 * zeroes page to simulate the local APIC and another
883 * one for the IO-APIC.
885 if (!smp_found_config
&& detect_init_APIC()) {
886 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
887 apic_phys
= __pa(apic_phys
);
889 apic_phys
= mp_lapic_addr
;
891 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
892 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
893 APIC_BASE
, apic_phys
);
896 * Fetch the APIC ID of the BSP in case we have a
897 * default configuration (or the MP table is broken).
899 boot_cpu_physical_apicid
= GET_APIC_ID(read_apic_id());
903 * This initializes the IO-APIC and APIC hardware if this is
906 int __init
APIC_init_uniprocessor(void)
909 printk(KERN_INFO
"Apic disabled\n");
914 printk(KERN_INFO
"Apic disabled by BIOS\n");
922 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
923 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
928 * Now enable IO-APICs, actually call clear_IO_APIC
929 * We need clear_IO_APIC before enabling vector on BP
931 if (!skip_ioapic_setup
&& nr_ioapics
)
934 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
935 localise_nmi_watchdog();
936 end_local_APIC_setup();
938 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
942 setup_boot_APIC_clock();
943 check_nmi_watchdog();
948 * Local APIC interrupts
952 * This interrupt should _never_ happen with our APIC/SMP architecture
954 asmlinkage
void smp_spurious_interrupt(void)
960 * Check if this really is a spurious interrupt and ACK it
961 * if it is a vectored one. Just in case...
962 * Spurious interrupts should not be ACKed.
964 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
965 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
968 add_pda(irq_spurious_count
, 1);
973 * This interrupt should never happen with our APIC/SMP architecture
975 asmlinkage
void smp_error_interrupt(void)
981 /* First tickle the hardware, only then report what went on. -- REW */
982 v
= apic_read(APIC_ESR
);
983 apic_write(APIC_ESR
, 0);
984 v1
= apic_read(APIC_ESR
);
986 atomic_inc(&irq_err_count
);
988 /* Here is what the APIC error bits mean:
992 3: Receive accept error
994 5: Send illegal vector
995 6: Received illegal vector
996 7: Illegal register address
998 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
999 smp_processor_id(), v
, v1
);
1004 * * connect_bsp_APIC - attach the APIC to the interrupt system
1006 void __init
connect_bsp_APIC(void)
1011 void disconnect_bsp_APIC(int virt_wire_setup
)
1013 /* Go back to Virtual Wire compatibility mode */
1014 unsigned long value
;
1016 /* For the spurious interrupt use vector F, and enable it */
1017 value
= apic_read(APIC_SPIV
);
1018 value
&= ~APIC_VECTOR_MASK
;
1019 value
|= APIC_SPIV_APIC_ENABLED
;
1021 apic_write(APIC_SPIV
, value
);
1023 if (!virt_wire_setup
) {
1025 * For LVT0 make it edge triggered, active high,
1026 * external and enabled
1028 value
= apic_read(APIC_LVT0
);
1029 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1030 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1031 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1032 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1033 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1034 apic_write(APIC_LVT0
, value
);
1037 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1040 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1041 value
= apic_read(APIC_LVT1
);
1042 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1043 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1044 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1045 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1046 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1047 apic_write(APIC_LVT1
, value
);
1050 void __cpuinit
generic_processor_info(int apicid
, int version
)
1055 if (num_processors
>= NR_CPUS
) {
1056 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1057 " Processor ignored.\n", NR_CPUS
);
1061 if (num_processors
>= maxcpus
) {
1062 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1063 " Processor ignored.\n", maxcpus
);
1068 cpus_complement(tmp_map
, cpu_present_map
);
1069 cpu
= first_cpu(tmp_map
);
1071 physid_set(apicid
, phys_cpu_present_map
);
1072 if (apicid
== boot_cpu_physical_apicid
) {
1074 * x86_bios_cpu_apicid is required to have processors listed
1075 * in same order as logical cpu numbers. Hence the first
1076 * entry is BSP, and so on.
1080 if (apicid
> max_physical_apicid
)
1081 max_physical_apicid
= apicid
;
1083 /* are we being called early in kernel startup? */
1084 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1085 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1086 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1088 cpu_to_apicid
[cpu
] = apicid
;
1089 bios_cpu_apicid
[cpu
] = apicid
;
1091 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1092 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1095 cpu_set(cpu
, cpu_possible_map
);
1096 cpu_set(cpu
, cpu_present_map
);
1105 /* 'active' is true if the local APIC was enabled by us and
1106 not the BIOS; this signifies that we are also responsible
1107 for disabling it before entering apm/acpi suspend */
1109 /* r/w apic fields */
1110 unsigned int apic_id
;
1111 unsigned int apic_taskpri
;
1112 unsigned int apic_ldr
;
1113 unsigned int apic_dfr
;
1114 unsigned int apic_spiv
;
1115 unsigned int apic_lvtt
;
1116 unsigned int apic_lvtpc
;
1117 unsigned int apic_lvt0
;
1118 unsigned int apic_lvt1
;
1119 unsigned int apic_lvterr
;
1120 unsigned int apic_tmict
;
1121 unsigned int apic_tdcr
;
1122 unsigned int apic_thmr
;
1125 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1127 unsigned long flags
;
1130 if (!apic_pm_state
.active
)
1133 maxlvt
= lapic_get_maxlvt();
1135 apic_pm_state
.apic_id
= read_apic_id();
1136 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1137 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1138 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1139 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1140 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1142 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1143 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1144 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1145 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1146 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1147 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1148 #ifdef CONFIG_X86_MCE_INTEL
1150 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1152 local_irq_save(flags
);
1153 disable_local_APIC();
1154 local_irq_restore(flags
);
1158 static int lapic_resume(struct sys_device
*dev
)
1161 unsigned long flags
;
1164 if (!apic_pm_state
.active
)
1167 maxlvt
= lapic_get_maxlvt();
1169 local_irq_save(flags
);
1170 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1171 l
&= ~MSR_IA32_APICBASE_BASE
;
1172 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1173 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1174 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1175 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1176 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1177 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1178 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1179 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1180 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1181 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1182 #ifdef CONFIG_X86_MCE_INTEL
1184 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1187 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1188 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1189 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1190 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1191 apic_write(APIC_ESR
, 0);
1192 apic_read(APIC_ESR
);
1193 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1194 apic_write(APIC_ESR
, 0);
1195 apic_read(APIC_ESR
);
1196 local_irq_restore(flags
);
1200 static struct sysdev_class lapic_sysclass
= {
1202 .resume
= lapic_resume
,
1203 .suspend
= lapic_suspend
,
1206 static struct sys_device device_lapic
= {
1208 .cls
= &lapic_sysclass
,
1211 static void __cpuinit
apic_pm_activate(void)
1213 apic_pm_state
.active
= 1;
1216 static int __init
init_lapic_sysfs(void)
1222 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1224 error
= sysdev_class_register(&lapic_sysclass
);
1226 error
= sysdev_register(&device_lapic
);
1229 device_initcall(init_lapic_sysfs
);
1231 #else /* CONFIG_PM */
1233 static void apic_pm_activate(void) { }
1235 #endif /* CONFIG_PM */
1238 * apic_is_clustered_box() -- Check if we can expect good TSC
1240 * Thus far, the major user of this is IBM's Summit2 series:
1242 * Clustered boxes may have unsynced TSC problems if they are
1243 * multi-chassis. Use available data to take a good guess.
1244 * If in doubt, go HPET.
1246 __cpuinit
int apic_is_clustered_box(void)
1248 int i
, clusters
, zeros
;
1250 u16
*bios_cpu_apicid
;
1251 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1254 * there is not this kind of box with AMD CPU yet.
1255 * Some AMD box with quadcore cpu and 8 sockets apicid
1256 * will be [4, 0x23] or [8, 0x27] could be thought to
1257 * vsmp box still need checking...
1259 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1262 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1263 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1265 for (i
= 0; i
< NR_CPUS
; i
++) {
1266 /* are we being called early in kernel startup? */
1267 if (bios_cpu_apicid
) {
1268 id
= bios_cpu_apicid
[i
];
1270 else if (i
< nr_cpu_ids
) {
1272 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1279 if (id
!= BAD_APICID
)
1280 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1283 /* Problem: Partially populated chassis may not have CPUs in some of
1284 * the APIC clusters they have been allocated. Only present CPUs have
1285 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1286 * Since clusters are allocated sequentially, count zeros only if
1287 * they are bounded by ones.
1291 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1292 if (test_bit(i
, clustermap
)) {
1293 clusters
+= 1 + zeros
;
1299 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1300 * not guaranteed to be synced between boards
1302 if (is_vsmp_box() && clusters
> 1)
1306 * If clusters > 2, then should be multi-chassis.
1307 * May have to revisit this when multi-core + hyperthreaded CPUs come
1308 * out, but AFAIK this will work even for them.
1310 return (clusters
> 2);
1314 * APIC command line parameters
1316 static int __init
apic_set_verbosity(char *str
)
1319 skip_ioapic_setup
= 0;
1323 if (strcmp("debug", str
) == 0)
1324 apic_verbosity
= APIC_DEBUG
;
1325 else if (strcmp("verbose", str
) == 0)
1326 apic_verbosity
= APIC_VERBOSE
;
1328 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1329 " use apic=verbose or apic=debug\n", str
);
1335 early_param("apic", apic_set_verbosity
);
1337 static __init
int setup_disableapic(char *str
)
1340 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1343 early_param("disableapic", setup_disableapic
);
1345 /* same as disableapic, for compatibility */
1346 static __init
int setup_nolapic(char *str
)
1348 return setup_disableapic(str
);
1350 early_param("nolapic", setup_nolapic
);
1352 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1354 local_apic_timer_c2_ok
= 1;
1357 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1359 static __init
int setup_noapictimer(char *str
)
1361 if (str
[0] != ' ' && str
[0] != 0)
1363 disable_apic_timer
= 1;
1366 __setup("noapictimer", setup_noapictimer
);
1368 static __init
int setup_apicpmtimer(char *s
)
1370 apic_calibrate_pmtmr
= 1;
1374 __setup("apicpmtimer", setup_apicpmtimer
);
1376 static int __init
lapic_insert_resource(void)
1381 /* Put local APIC into the resource map. */
1382 lapic_resource
.start
= apic_phys
;
1383 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1384 insert_resource(&iomem_resource
, &lapic_resource
);
1390 * need call insert after e820_reserve_resources()
1391 * that is using request_resource
1393 late_initcall(lapic_insert_resource
);