1 #include <linux/init.h>
2 #include <linux/bitops.h>
6 #include <asm/processor.h>
9 #include <asm/pci-direct.h>
12 # include <asm/numa_64.h>
13 # include <asm/mmconfig.h>
14 # include <asm/cacheflush.h>
21 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
22 * misexecution of code under Linux. Owners of such processors should
23 * contact AMD for precise details and a CPU swap.
25 * See http://www.multimania.com/poulot/k6bug.html
26 * http://www.amd.com/K6/k6docs/revgd.html
28 * The following test is erm.. interesting. AMD neglected to up
29 * the chip setting when fixing the bug but they also tweaked some
30 * performance at the same time..
33 extern void vide(void);
34 __asm__(".align 4\nvide: ret");
36 static void __cpuinit
init_amd_k5(struct cpuinfo_x86
*c
)
39 * General Systems BIOSen alias the cpu frequency registers
40 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
41 * drivers subsequently pokes it, and changes the CPU speed.
42 * Workaround : Remove the unneeded alias.
44 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
45 #define CBAR_ENB (0x80000000)
46 #define CBAR_KEY (0X000000CB)
47 if (c
->x86_model
== 9 || c
->x86_model
== 10) {
48 if (inl(CBAR
) & CBAR_ENB
)
49 outl(0 | CBAR_KEY
, CBAR
);
54 static void __cpuinit
init_amd_k6(struct cpuinfo_x86
*c
)
57 int mbytes
= num_physpages
>> (20-PAGE_SHIFT
);
59 if (c
->x86_model
< 6) {
60 /* Based on AMD doc 20734R - June 2000 */
61 if (c
->x86_model
== 0) {
62 clear_cpu_cap(c
, X86_FEATURE_APIC
);
63 set_cpu_cap(c
, X86_FEATURE_PGE
);
68 if (c
->x86_model
== 6 && c
->x86_mask
== 1) {
69 const int K6_BUG_LOOP
= 1000000;
74 printk(KERN_INFO
"AMD K6 stepping B detected - ");
77 * It looks like AMD fixed the 2.6.2 bug and improved indirect
78 * calls at the same time.
89 if (d
> 20*K6_BUG_LOOP
)
91 "system stability may be impaired when more than 32 MB are used.\n");
93 printk(KERN_CONT
"probably OK (after B9730xxxx).\n");
94 printk(KERN_INFO
"Please see http://membres.lycos.fr/poulot/k6bug.html\n");
97 /* K6 with old style WHCR */
98 if (c
->x86_model
< 8 ||
99 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
100 /* We can only write allocate on the low 508Mb */
104 rdmsr(MSR_K6_WHCR
, l
, h
);
105 if ((l
&0x0000FFFF) == 0) {
107 l
= (1<<0)|((mbytes
/4)<<1);
108 local_irq_save(flags
);
110 wrmsr(MSR_K6_WHCR
, l
, h
);
111 local_irq_restore(flags
);
112 printk(KERN_INFO
"Enabling old style K6 write allocation for %d Mb\n",
118 if ((c
->x86_model
== 8 && c
->x86_mask
> 7) ||
119 c
->x86_model
== 9 || c
->x86_model
== 13) {
120 /* The more serious chips .. */
125 rdmsr(MSR_K6_WHCR
, l
, h
);
126 if ((l
&0xFFFF0000) == 0) {
128 l
= ((mbytes
>>2)<<22)|(1<<16);
129 local_irq_save(flags
);
131 wrmsr(MSR_K6_WHCR
, l
, h
);
132 local_irq_restore(flags
);
133 printk(KERN_INFO
"Enabling new style K6 write allocation for %d Mb\n",
140 if (c
->x86_model
== 10) {
141 /* AMD Geode LX is model 10 */
142 /* placeholder for any needed mods */
147 static void __cpuinit
amd_k7_smp_check(struct cpuinfo_x86
*c
)
150 /* calling is from identify_secondary_cpu() ? */
151 if (c
->cpu_index
== boot_cpu_id
)
155 * Certain Athlons might work (for various values of 'work') in SMP
156 * but they are not certified as MP capable.
158 /* Athlon 660/661 is valid. */
159 if ((c
->x86_model
== 6) && ((c
->x86_mask
== 0) ||
163 /* Duron 670 is valid */
164 if ((c
->x86_model
== 7) && (c
->x86_mask
== 0))
168 * Athlon 662, Duron 671, and Athlon >model 7 have capability
169 * bit. It's worth noting that the A5 stepping (662) of some
170 * Athlon XP's have the MP bit set.
171 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
174 if (((c
->x86_model
== 6) && (c
->x86_mask
>= 2)) ||
175 ((c
->x86_model
== 7) && (c
->x86_mask
>= 1)) ||
180 /* If we get here, not a certified SMP capable AMD system. */
183 * Don't taint if we are running SMP kernel on a single non-MP
186 WARN_ONCE(1, "WARNING: This combination of AMD"
187 " processors is not suitable for SMP.\n");
188 if (!test_taint(TAINT_UNSAFE_SMP
))
189 add_taint(TAINT_UNSAFE_SMP
);
196 static void __cpuinit
init_amd_k7(struct cpuinfo_x86
*c
)
201 * Bit 15 of Athlon specific MSR 15, needs to be 0
202 * to enable SSE on Palomino/Morgan/Barton CPU's.
203 * If the BIOS didn't enable it already, enable it here.
205 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
206 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
207 printk(KERN_INFO
"Enabling disabled K7/SSE Support.\n");
208 rdmsr(MSR_K7_HWCR
, l
, h
);
210 wrmsr(MSR_K7_HWCR
, l
, h
);
211 set_cpu_cap(c
, X86_FEATURE_XMM
);
216 * It's been determined by AMD that Athlons since model 8 stepping 1
217 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
218 * As per AMD technical note 27212 0.2
220 if ((c
->x86_model
== 8 && c
->x86_mask
>= 1) || (c
->x86_model
> 8)) {
221 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
222 if ((l
& 0xfff00000) != 0x20000000) {
224 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
225 l
, ((l
& 0x000fffff)|0x20000000));
226 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
230 set_cpu_cap(c
, X86_FEATURE_K7
);
236 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
237 static int __cpuinit
nearby_node(int apicid
)
241 for (i
= apicid
- 1; i
>= 0; i
--) {
242 node
= apicid_to_node
[i
];
243 if (node
!= NUMA_NO_NODE
&& node_online(node
))
246 for (i
= apicid
+ 1; i
< MAX_LOCAL_APIC
; i
++) {
247 node
= apicid_to_node
[i
];
248 if (node
!= NUMA_NO_NODE
&& node_online(node
))
251 return first_node(node_online_map
); /* Shouldn't happen */
256 * Fixup core topology information for
257 * (1) AMD multi-node processors
258 * Assumption: Number of cores in each internal node is the same.
259 * (2) AMD processors supporting compute units
262 static void __cpuinit
amd_get_topology(struct cpuinfo_x86
*c
)
266 int cpu
= smp_processor_id();
268 /* get information required for multi-node processors */
269 if (cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
270 u32 eax
, ebx
, ecx
, edx
;
272 cpuid(0x8000001e, &eax
, &ebx
, &ecx
, &edx
);
273 nodes
= ((ecx
>> 8) & 7) + 1;
276 /* get compute unit information */
277 smp_num_siblings
= ((ebx
>> 8) & 3) + 1;
278 c
->compute_unit_id
= ebx
& 0xff;
279 } else if (cpu_has(c
, X86_FEATURE_NODEID_MSR
)) {
282 rdmsrl(MSR_FAM10H_NODE_ID
, value
);
283 nodes
= ((value
>> 3) & 7) + 1;
288 /* fixup multi-node processor information */
292 set_cpu_cap(c
, X86_FEATURE_AMD_DCM
);
293 cores_per_node
= c
->x86_max_cores
/ nodes
;
295 /* store NodeID, use llc_shared_map to store sibling info */
296 per_cpu(cpu_llc_id
, cpu
) = node_id
;
298 /* core id to be in range from 0 to (cores_per_node - 1) */
299 c
->cpu_core_id
= c
->cpu_core_id
% cores_per_node
;
305 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
306 * Assumes number of cores is a power of two.
308 static void __cpuinit
amd_detect_cmp(struct cpuinfo_x86
*c
)
312 int cpu
= smp_processor_id();
314 bits
= c
->x86_coreid_bits
;
315 /* Low order bits define the core id (index of core in socket) */
316 c
->cpu_core_id
= c
->initial_apicid
& ((1 << bits
)-1);
317 /* Convert the initial APIC ID into the socket ID */
318 c
->phys_proc_id
= c
->initial_apicid
>> bits
;
319 /* use socket ID also for last level cache */
320 per_cpu(cpu_llc_id
, cpu
) = c
->phys_proc_id
;
325 int amd_get_nb_id(int cpu
)
329 id
= per_cpu(cpu_llc_id
, cpu
);
333 EXPORT_SYMBOL_GPL(amd_get_nb_id
);
335 static void __cpuinit
srat_detect_node(struct cpuinfo_x86
*c
)
337 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
338 int cpu
= smp_processor_id();
340 unsigned apicid
= c
->apicid
;
342 node
= per_cpu(cpu_llc_id
, cpu
);
344 if (apicid_to_node
[apicid
] != NUMA_NO_NODE
)
345 node
= apicid_to_node
[apicid
];
346 if (!node_online(node
)) {
347 /* Two possibilities here:
348 - The CPU is missing memory and no node was created.
349 In that case try picking one from a nearby CPU
350 - The APIC IDs differ from the HyperTransport node IDs
351 which the K8 northbridge parsing fills in.
352 Assume they are all increased by a constant offset,
353 but in the same order as the HT nodeids.
354 If that doesn't result in a usable node fall back to the
355 path for the previous case. */
357 int ht_nodeid
= c
->initial_apicid
;
359 if (ht_nodeid
>= 0 &&
360 apicid_to_node
[ht_nodeid
] != NUMA_NO_NODE
)
361 node
= apicid_to_node
[ht_nodeid
];
362 /* Pick a nearby node */
363 if (!node_online(node
))
364 node
= nearby_node(apicid
);
366 numa_set_node(cpu
, node
);
370 static void __cpuinit
early_init_amd_mc(struct cpuinfo_x86
*c
)
375 /* Multi core CPU? */
376 if (c
->extended_cpuid_level
< 0x80000008)
379 ecx
= cpuid_ecx(0x80000008);
381 c
->x86_max_cores
= (ecx
& 0xff) + 1;
383 /* CPU telling us the core id bits shift? */
384 bits
= (ecx
>> 12) & 0xF;
386 /* Otherwise recompute */
388 while ((1 << bits
) < c
->x86_max_cores
)
392 c
->x86_coreid_bits
= bits
;
396 static void __cpuinit
early_init_amd(struct cpuinfo_x86
*c
)
398 early_init_amd_mc(c
);
401 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
402 * with P/T states and does not stop in deep C-states
404 if (c
->x86_power
& (1 << 8)) {
405 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
406 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
410 set_cpu_cap(c
, X86_FEATURE_SYSCALL32
);
412 /* Set MTRR capability flag if appropriate */
414 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
415 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
416 set_cpu_cap(c
, X86_FEATURE_K6_MTRR
);
418 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
419 /* check CPU config space for extended APIC ID */
420 if (cpu_has_apic
&& c
->x86
>= 0xf) {
422 val
= read_pci_config(0, 24, 0, 0x68);
423 if ((val
& ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
424 set_cpu_cap(c
, X86_FEATURE_EXTD_APICID
);
428 /* We need to do the following only once */
429 if (c
!= &boot_cpu_data
)
432 if (cpu_has(c
, X86_FEATURE_CONSTANT_TSC
)) {
435 (c
->x86
== 0x10 && c
->x86_model
>= 0x2)) {
438 rdmsrl(MSR_K7_HWCR
, val
);
439 if (!(val
& BIT(24)))
440 printk(KERN_WARNING FW_BUG
"TSC doesn't count "
441 "with P0 frequency!\n");
446 static void __cpuinit
init_amd(struct cpuinfo_x86
*c
)
449 unsigned long long value
;
452 * Disable TLB flush filter by setting HWCR.FFDIS on K8
453 * bit 6 of msr C001_0015
455 * Errata 63 for SH-B3 steppings
456 * Errata 122 for all steppings (F+ have it disabled by default)
459 rdmsrl(MSR_K7_HWCR
, value
);
461 wrmsrl(MSR_K7_HWCR
, value
);
468 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
469 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
471 clear_cpu_cap(c
, 0*32+31);
474 /* On C+ stepping K8 rep microcode works well for copy/memset */
478 level
= cpuid_eax(1);
479 if ((level
>= 0x0f48 && level
< 0x0f50) || level
>= 0x0f58)
480 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
483 * Some BIOSes incorrectly force this feature, but only K8
484 * revision D (model = 0x14) and later actually support it.
485 * (AMD Erratum #110, docId: 25759).
487 if (c
->x86_model
< 0x14 && cpu_has(c
, X86_FEATURE_LAHF_LM
)) {
490 clear_cpu_cap(c
, X86_FEATURE_LAHF_LM
);
491 if (!rdmsrl_amd_safe(0xc001100d, &val
)) {
492 val
&= ~(1ULL << 32);
493 wrmsrl_amd_safe(0xc001100d, val
);
499 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
501 /* get apicid instead of initial apic id from cpuid */
502 c
->apicid
= hard_smp_processor_id();
506 * FIXME: We should handle the K5 here. Set up the write
507 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
518 case 6: /* An Athlon/Duron */
523 /* K6s reports MCEs but don't actually have all the MSRs */
525 clear_cpu_cap(c
, X86_FEATURE_MCE
);
528 /* Enable workaround for FXSAVE leak */
530 set_cpu_cap(c
, X86_FEATURE_FXSAVE_LEAK
);
532 if (!c
->x86_model_id
[0]) {
535 /* Should distinguish Models here, but this is only
536 a fallback anyways. */
537 strcpy(c
->x86_model_id
, "Hammer");
542 cpu_detect_cache_sizes(c
);
544 /* Multi core CPU? */
545 if (c
->extended_cpuid_level
>= 0x80000008) {
554 if (c
->extended_cpuid_level
>= 0x80000006) {
555 if (cpuid_edx(0x80000006) & 0xf000)
556 num_cache_leaves
= 4;
558 num_cache_leaves
= 3;
562 set_cpu_cap(c
, X86_FEATURE_K8
);
565 /* MFENCE stops RDTSC speculation */
566 set_cpu_cap(c
, X86_FEATURE_MFENCE_RDTSC
);
570 if (c
->x86
== 0x10) {
571 /* do this for boot cpu */
572 if (c
== &boot_cpu_data
)
573 check_enable_amd_mmconf_dmi();
575 fam10h_check_enable_mmcfg();
578 if (c
== &boot_cpu_data
&& c
->x86
>= 0xf) {
579 unsigned long long tseg
;
582 * Split up direct mapping around the TSEG SMM area.
583 * Don't do it for gbpages because there seems very little
584 * benefit in doing so.
586 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR
, &tseg
)) {
587 printk(KERN_DEBUG
"tseg: %010llx\n", tseg
);
588 if ((tseg
>>PMD_SHIFT
) <
589 (max_low_pfn_mapped
>>(PMD_SHIFT
-PAGE_SHIFT
)) ||
591 (max_pfn_mapped
>>(PMD_SHIFT
-PAGE_SHIFT
)) &&
592 (tseg
>>PMD_SHIFT
) >= (1ULL<<(32 - PMD_SHIFT
))))
593 set_memory_4k((unsigned long)__va(tseg
), 1);
600 static unsigned int __cpuinit
amd_size_cache(struct cpuinfo_x86
*c
,
603 /* AMD errata T13 (order #21922) */
606 if (c
->x86_model
== 3 && c
->x86_mask
== 0)
608 /* Tbird rev A1/A2 */
609 if (c
->x86_model
== 4 &&
610 (c
->x86_mask
== 0 || c
->x86_mask
== 1))
617 static const struct cpu_dev __cpuinitconst amd_cpu_dev
= {
619 .c_ident
= { "AuthenticAMD" },
622 { .vendor
= X86_VENDOR_AMD
, .family
= 4, .model_names
=
633 .c_size_cache
= amd_size_cache
,
635 .c_early_init
= early_init_amd
,
637 .c_x86_vendor
= X86_VENDOR_AMD
,
640 cpu_dev_register(amd_cpu_dev
);
643 * AMD errata checking
645 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
646 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
647 * have an OSVW id assigned, which it takes as first argument. Both take a
648 * variable number of family-specific model-stepping ranges created by
649 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
650 * int[] in arch/x86/include/asm/processor.h.
654 * const int amd_erratum_319[] =
655 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
656 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
657 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
660 const int amd_erratum_400
[] =
661 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
662 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
663 EXPORT_SYMBOL_GPL(amd_erratum_400
);
665 const int amd_erratum_383
[] =
666 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
667 EXPORT_SYMBOL_GPL(amd_erratum_383
);
669 bool cpu_has_amd_erratum(const int *erratum
)
671 struct cpuinfo_x86
*cpu
= ¤t_cpu_data
;
672 int osvw_id
= *erratum
++;
677 * If called early enough that current_cpu_data hasn't been initialized
678 * yet, fall back to boot_cpu_data.
681 cpu
= &boot_cpu_data
;
683 if (cpu
->x86_vendor
!= X86_VENDOR_AMD
)
686 if (osvw_id
>= 0 && osvw_id
< 65536 &&
687 cpu_has(cpu
, X86_FEATURE_OSVW
)) {
690 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH
, osvw_len
);
691 if (osvw_id
< osvw_len
) {
694 rdmsrl(MSR_AMD64_OSVW_STATUS
+ (osvw_id
>> 6),
696 return osvw_bits
& (1ULL << (osvw_id
& 0x3f));
700 /* OSVW unavailable or ID unknown, match family-model-stepping range */
701 ms
= (cpu
->x86_model
<< 4) | cpu
->x86_mask
;
702 while ((range
= *erratum
++))
703 if ((cpu
->x86
== AMD_MODEL_RANGE_FAMILY(range
)) &&
704 (ms
>= AMD_MODEL_RANGE_START(range
)) &&
705 (ms
<= AMD_MODEL_RANGE_END(range
)))
711 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum
);