1 #include <linux/export.h>
2 #include <linux/init.h>
3 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <asm/processor.h>
12 #include <asm/pci-direct.h>
15 # include <asm/numa_64.h>
16 # include <asm/mmconfig.h>
17 # include <asm/cacheflush.h>
22 static inline int rdmsrl_amd_safe(unsigned msr
, unsigned long long *p
)
24 struct cpuinfo_x86
*c
= &cpu_data(smp_processor_id());
28 WARN_ONCE((c
->x86
!= 0xf), "%s should only be used on K8!\n", __func__
);
33 err
= rdmsr_safe_regs(gprs
);
35 *p
= gprs
[0] | ((u64
)gprs
[2] << 32);
40 static inline int wrmsrl_amd_safe(unsigned msr
, unsigned long long val
)
42 struct cpuinfo_x86
*c
= &cpu_data(smp_processor_id());
45 WARN_ONCE((c
->x86
!= 0xf), "%s should only be used on K8!\n", __func__
);
52 return wrmsr_safe_regs(gprs
);
57 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
58 * misexecution of code under Linux. Owners of such processors should
59 * contact AMD for precise details and a CPU swap.
61 * See http://www.multimania.com/poulot/k6bug.html
62 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
63 * (Publication # 21266 Issue Date: August 1998)
65 * The following test is erm.. interesting. AMD neglected to up
66 * the chip setting when fixing the bug but they also tweaked some
67 * performance at the same time..
70 extern void vide(void);
71 __asm__(".align 4\nvide: ret");
73 static void __cpuinit
init_amd_k5(struct cpuinfo_x86
*c
)
76 * General Systems BIOSen alias the cpu frequency registers
77 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
78 * drivers subsequently pokes it, and changes the CPU speed.
79 * Workaround : Remove the unneeded alias.
81 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
82 #define CBAR_ENB (0x80000000)
83 #define CBAR_KEY (0X000000CB)
84 if (c
->x86_model
== 9 || c
->x86_model
== 10) {
85 if (inl(CBAR
) & CBAR_ENB
)
86 outl(0 | CBAR_KEY
, CBAR
);
91 static void __cpuinit
init_amd_k6(struct cpuinfo_x86
*c
)
94 int mbytes
= num_physpages
>> (20-PAGE_SHIFT
);
96 if (c
->x86_model
< 6) {
97 /* Based on AMD doc 20734R - June 2000 */
98 if (c
->x86_model
== 0) {
99 clear_cpu_cap(c
, X86_FEATURE_APIC
);
100 set_cpu_cap(c
, X86_FEATURE_PGE
);
105 if (c
->x86_model
== 6 && c
->x86_mask
== 1) {
106 const int K6_BUG_LOOP
= 1000000;
108 void (*f_vide
)(void);
111 printk(KERN_INFO
"AMD K6 stepping B detected - ");
114 * It looks like AMD fixed the 2.6.2 bug and improved indirect
115 * calls at the same time.
126 if (d
> 20*K6_BUG_LOOP
)
128 "system stability may be impaired when more than 32 MB are used.\n");
130 printk(KERN_CONT
"probably OK (after B9730xxxx).\n");
133 /* K6 with old style WHCR */
134 if (c
->x86_model
< 8 ||
135 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
136 /* We can only write allocate on the low 508Mb */
140 rdmsr(MSR_K6_WHCR
, l
, h
);
141 if ((l
&0x0000FFFF) == 0) {
143 l
= (1<<0)|((mbytes
/4)<<1);
144 local_irq_save(flags
);
146 wrmsr(MSR_K6_WHCR
, l
, h
);
147 local_irq_restore(flags
);
148 printk(KERN_INFO
"Enabling old style K6 write allocation for %d Mb\n",
154 if ((c
->x86_model
== 8 && c
->x86_mask
> 7) ||
155 c
->x86_model
== 9 || c
->x86_model
== 13) {
156 /* The more serious chips .. */
161 rdmsr(MSR_K6_WHCR
, l
, h
);
162 if ((l
&0xFFFF0000) == 0) {
164 l
= ((mbytes
>>2)<<22)|(1<<16);
165 local_irq_save(flags
);
167 wrmsr(MSR_K6_WHCR
, l
, h
);
168 local_irq_restore(flags
);
169 printk(KERN_INFO
"Enabling new style K6 write allocation for %d Mb\n",
176 if (c
->x86_model
== 10) {
177 /* AMD Geode LX is model 10 */
178 /* placeholder for any needed mods */
183 static void __cpuinit
amd_k7_smp_check(struct cpuinfo_x86
*c
)
185 /* calling is from identify_secondary_cpu() ? */
190 * Certain Athlons might work (for various values of 'work') in SMP
191 * but they are not certified as MP capable.
193 /* Athlon 660/661 is valid. */
194 if ((c
->x86_model
== 6) && ((c
->x86_mask
== 0) ||
198 /* Duron 670 is valid */
199 if ((c
->x86_model
== 7) && (c
->x86_mask
== 0))
203 * Athlon 662, Duron 671, and Athlon >model 7 have capability
204 * bit. It's worth noting that the A5 stepping (662) of some
205 * Athlon XP's have the MP bit set.
206 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
209 if (((c
->x86_model
== 6) && (c
->x86_mask
>= 2)) ||
210 ((c
->x86_model
== 7) && (c
->x86_mask
>= 1)) ||
215 /* If we get here, not a certified SMP capable AMD system. */
218 * Don't taint if we are running SMP kernel on a single non-MP
221 WARN_ONCE(1, "WARNING: This combination of AMD"
222 " processors is not suitable for SMP.\n");
223 if (!test_taint(TAINT_UNSAFE_SMP
))
224 add_taint(TAINT_UNSAFE_SMP
);
230 static void __cpuinit
init_amd_k7(struct cpuinfo_x86
*c
)
235 * Bit 15 of Athlon specific MSR 15, needs to be 0
236 * to enable SSE on Palomino/Morgan/Barton CPU's.
237 * If the BIOS didn't enable it already, enable it here.
239 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
240 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
241 printk(KERN_INFO
"Enabling disabled K7/SSE Support.\n");
242 rdmsr(MSR_K7_HWCR
, l
, h
);
244 wrmsr(MSR_K7_HWCR
, l
, h
);
245 set_cpu_cap(c
, X86_FEATURE_XMM
);
250 * It's been determined by AMD that Athlons since model 8 stepping 1
251 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
252 * As per AMD technical note 27212 0.2
254 if ((c
->x86_model
== 8 && c
->x86_mask
>= 1) || (c
->x86_model
> 8)) {
255 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
256 if ((l
& 0xfff00000) != 0x20000000) {
258 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
259 l
, ((l
& 0x000fffff)|0x20000000));
260 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
264 set_cpu_cap(c
, X86_FEATURE_K7
);
272 * To workaround broken NUMA config. Read the comment in
273 * srat_detect_node().
275 static int __cpuinit
nearby_node(int apicid
)
279 for (i
= apicid
- 1; i
>= 0; i
--) {
280 node
= __apicid_to_node
[i
];
281 if (node
!= NUMA_NO_NODE
&& node_online(node
))
284 for (i
= apicid
+ 1; i
< MAX_LOCAL_APIC
; i
++) {
285 node
= __apicid_to_node
[i
];
286 if (node
!= NUMA_NO_NODE
&& node_online(node
))
289 return first_node(node_online_map
); /* Shouldn't happen */
294 * Fixup core topology information for
295 * (1) AMD multi-node processors
296 * Assumption: Number of cores in each internal node is the same.
297 * (2) AMD processors supporting compute units
300 static void __cpuinit
amd_get_topology(struct cpuinfo_x86
*c
)
302 u32 nodes
, cores_per_cu
= 1;
304 int cpu
= smp_processor_id();
306 /* get information required for multi-node processors */
307 if (cpu_has_topoext
) {
308 u32 eax
, ebx
, ecx
, edx
;
310 cpuid(0x8000001e, &eax
, &ebx
, &ecx
, &edx
);
311 nodes
= ((ecx
>> 8) & 7) + 1;
314 /* get compute unit information */
315 smp_num_siblings
= ((ebx
>> 8) & 3) + 1;
316 c
->compute_unit_id
= ebx
& 0xff;
317 cores_per_cu
+= ((ebx
>> 8) & 3);
318 } else if (cpu_has(c
, X86_FEATURE_NODEID_MSR
)) {
321 rdmsrl(MSR_FAM10H_NODE_ID
, value
);
322 nodes
= ((value
>> 3) & 7) + 1;
327 /* fixup multi-node processor information */
332 set_cpu_cap(c
, X86_FEATURE_AMD_DCM
);
333 cores_per_node
= c
->x86_max_cores
/ nodes
;
334 cus_per_node
= cores_per_node
/ cores_per_cu
;
336 /* store NodeID, use llc_shared_map to store sibling info */
337 per_cpu(cpu_llc_id
, cpu
) = node_id
;
339 /* core id has to be in the [0 .. cores_per_node - 1] range */
340 c
->cpu_core_id
%= cores_per_node
;
341 c
->compute_unit_id
%= cus_per_node
;
347 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
348 * Assumes number of cores is a power of two.
350 static void __cpuinit
amd_detect_cmp(struct cpuinfo_x86
*c
)
354 int cpu
= smp_processor_id();
356 bits
= c
->x86_coreid_bits
;
357 /* Low order bits define the core id (index of core in socket) */
358 c
->cpu_core_id
= c
->initial_apicid
& ((1 << bits
)-1);
359 /* Convert the initial APIC ID into the socket ID */
360 c
->phys_proc_id
= c
->initial_apicid
>> bits
;
361 /* use socket ID also for last level cache */
362 per_cpu(cpu_llc_id
, cpu
) = c
->phys_proc_id
;
367 u16
amd_get_nb_id(int cpu
)
371 id
= per_cpu(cpu_llc_id
, cpu
);
375 EXPORT_SYMBOL_GPL(amd_get_nb_id
);
377 static void __cpuinit
srat_detect_node(struct cpuinfo_x86
*c
)
380 int cpu
= smp_processor_id();
382 unsigned apicid
= c
->apicid
;
384 node
= numa_cpu_node(cpu
);
385 if (node
== NUMA_NO_NODE
)
386 node
= per_cpu(cpu_llc_id
, cpu
);
389 * On multi-fabric platform (e.g. Numascale NumaChip) a
390 * platform-specific handler needs to be called to fixup some
393 if (x86_cpuinit
.fixup_cpu_id
)
394 x86_cpuinit
.fixup_cpu_id(c
, node
);
396 if (!node_online(node
)) {
398 * Two possibilities here:
400 * - The CPU is missing memory and no node was created. In
401 * that case try picking one from a nearby CPU.
403 * - The APIC IDs differ from the HyperTransport node IDs
404 * which the K8 northbridge parsing fills in. Assume
405 * they are all increased by a constant offset, but in
406 * the same order as the HT nodeids. If that doesn't
407 * result in a usable node fall back to the path for the
410 * This workaround operates directly on the mapping between
411 * APIC ID and NUMA node, assuming certain relationship
412 * between APIC ID, HT node ID and NUMA topology. As going
413 * through CPU mapping may alter the outcome, directly
414 * access __apicid_to_node[].
416 int ht_nodeid
= c
->initial_apicid
;
418 if (ht_nodeid
>= 0 &&
419 __apicid_to_node
[ht_nodeid
] != NUMA_NO_NODE
)
420 node
= __apicid_to_node
[ht_nodeid
];
421 /* Pick a nearby node */
422 if (!node_online(node
))
423 node
= nearby_node(apicid
);
425 numa_set_node(cpu
, node
);
429 static void __cpuinit
early_init_amd_mc(struct cpuinfo_x86
*c
)
434 /* Multi core CPU? */
435 if (c
->extended_cpuid_level
< 0x80000008)
438 ecx
= cpuid_ecx(0x80000008);
440 c
->x86_max_cores
= (ecx
& 0xff) + 1;
442 /* CPU telling us the core id bits shift? */
443 bits
= (ecx
>> 12) & 0xF;
445 /* Otherwise recompute */
447 while ((1 << bits
) < c
->x86_max_cores
)
451 c
->x86_coreid_bits
= bits
;
455 static void __cpuinit
bsp_init_amd(struct cpuinfo_x86
*c
)
457 if (cpu_has(c
, X86_FEATURE_CONSTANT_TSC
)) {
460 (c
->x86
== 0x10 && c
->x86_model
>= 0x2)) {
463 rdmsrl(MSR_K7_HWCR
, val
);
464 if (!(val
& BIT(24)))
465 printk(KERN_WARNING FW_BUG
"TSC doesn't count "
466 "with P0 frequency!\n");
470 if (c
->x86
== 0x15) {
471 unsigned long upperbit
;
474 cpuid
= cpuid_edx(0x80000005);
475 assoc
= cpuid
>> 16 & 0xff;
476 upperbit
= ((cpuid
>> 24) << 10) / assoc
;
478 va_align
.mask
= (upperbit
- 1) & PAGE_MASK
;
479 va_align
.flags
= ALIGN_VA_32
| ALIGN_VA_64
;
483 static void __cpuinit
early_init_amd(struct cpuinfo_x86
*c
)
485 early_init_amd_mc(c
);
488 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
489 * with P/T states and does not stop in deep C-states
491 if (c
->x86_power
& (1 << 8)) {
492 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
493 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
494 if (!check_tsc_unstable())
495 sched_clock_stable
= 1;
499 set_cpu_cap(c
, X86_FEATURE_SYSCALL32
);
501 /* Set MTRR capability flag if appropriate */
503 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
504 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
505 set_cpu_cap(c
, X86_FEATURE_K6_MTRR
);
507 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
508 /* check CPU config space for extended APIC ID */
509 if (cpu_has_apic
&& c
->x86
>= 0xf) {
511 val
= read_pci_config(0, 24, 0, 0x68);
512 if ((val
& ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
513 set_cpu_cap(c
, X86_FEATURE_EXTD_APICID
);
518 static void __cpuinit
init_amd(struct cpuinfo_x86
*c
)
521 unsigned long long value
;
525 * Disable TLB flush filter by setting HWCR.FFDIS on K8
526 * bit 6 of msr C001_0015
528 * Errata 63 for SH-B3 steppings
529 * Errata 122 for all steppings (F+ have it disabled by default)
532 rdmsrl(MSR_K7_HWCR
, value
);
534 wrmsrl(MSR_K7_HWCR
, value
);
541 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
542 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
544 clear_cpu_cap(c
, 0*32+31);
547 /* On C+ stepping K8 rep microcode works well for copy/memset */
551 level
= cpuid_eax(1);
552 if ((level
>= 0x0f48 && level
< 0x0f50) || level
>= 0x0f58)
553 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
556 * Some BIOSes incorrectly force this feature, but only K8
557 * revision D (model = 0x14) and later actually support it.
558 * (AMD Erratum #110, docId: 25759).
560 if (c
->x86_model
< 0x14 && cpu_has(c
, X86_FEATURE_LAHF_LM
)) {
561 clear_cpu_cap(c
, X86_FEATURE_LAHF_LM
);
562 if (!rdmsrl_amd_safe(0xc001100d, &value
)) {
563 value
&= ~(1ULL << 32);
564 wrmsrl_amd_safe(0xc001100d, value
);
570 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
572 /* get apicid instead of initial apic id from cpuid */
573 c
->apicid
= hard_smp_processor_id();
577 * FIXME: We should handle the K5 here. Set up the write
578 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
589 case 6: /* An Athlon/Duron */
594 /* K6s reports MCEs but don't actually have all the MSRs */
596 clear_cpu_cap(c
, X86_FEATURE_MCE
);
599 /* Enable workaround for FXSAVE leak */
601 set_cpu_cap(c
, X86_FEATURE_FXSAVE_LEAK
);
603 if (!c
->x86_model_id
[0]) {
606 /* Should distinguish Models here, but this is only
607 a fallback anyways. */
608 strcpy(c
->x86_model_id
, "Hammer");
613 /* re-enable TopologyExtensions if switched off by BIOS */
614 if ((c
->x86
== 0x15) &&
615 (c
->x86_model
>= 0x10) && (c
->x86_model
<= 0x1f) &&
616 !cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
618 if (!rdmsrl_safe(0xc0011005, &value
)) {
620 wrmsrl_safe(0xc0011005, value
);
621 rdmsrl(0xc0011005, value
);
622 if (value
& (1ULL << 54)) {
623 set_cpu_cap(c
, X86_FEATURE_TOPOEXT
);
624 printk(KERN_INFO FW_INFO
"CPU: Re-enabling "
625 "disabled Topology Extensions Support\n");
631 * The way access filter has a performance penalty on some workloads.
632 * Disable it on the affected CPUs.
634 if ((c
->x86
== 0x15) &&
635 (c
->x86_model
>= 0x02) && (c
->x86_model
< 0x20)) {
637 if (!rdmsrl_safe(0xc0011021, &value
) && !(value
& 0x1E)) {
639 wrmsrl_safe(0xc0011021, value
);
643 cpu_detect_cache_sizes(c
);
645 /* Multi core CPU? */
646 if (c
->extended_cpuid_level
>= 0x80000008) {
655 init_amd_cacheinfo(c
);
658 set_cpu_cap(c
, X86_FEATURE_K8
);
661 /* MFENCE stops RDTSC speculation */
662 set_cpu_cap(c
, X86_FEATURE_MFENCE_RDTSC
);
666 if (c
->x86
== 0x10) {
667 /* do this for boot cpu */
668 if (c
== &boot_cpu_data
)
669 check_enable_amd_mmconf_dmi();
671 fam10h_check_enable_mmcfg();
674 if (c
== &boot_cpu_data
&& c
->x86
>= 0xf) {
675 unsigned long long tseg
;
678 * Split up direct mapping around the TSEG SMM area.
679 * Don't do it for gbpages because there seems very little
680 * benefit in doing so.
682 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR
, &tseg
)) {
683 printk(KERN_DEBUG
"tseg: %010llx\n", tseg
);
684 if ((tseg
>>PMD_SHIFT
) <
685 (max_low_pfn_mapped
>>(PMD_SHIFT
-PAGE_SHIFT
)) ||
687 (max_pfn_mapped
>>(PMD_SHIFT
-PAGE_SHIFT
)) &&
688 (tseg
>>PMD_SHIFT
) >= (1ULL<<(32 - PMD_SHIFT
))))
689 set_memory_4k((unsigned long)__va(tseg
), 1);
695 * Family 0x12 and above processors have APIC timer
696 * running in deep C states.
699 set_cpu_cap(c
, X86_FEATURE_ARAT
);
701 if (c
->x86
== 0x10) {
703 * Disable GART TLB Walk Errors on Fam10h. We do this here
704 * because this is always needed when GART is enabled, even in a
705 * kernel which has no MCE support built in.
706 * BIOS should disable GartTlbWlk Errors themself. If
707 * it doesn't do it here as suggested by the BKDG.
709 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
714 err
= rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask
);
717 wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask
);
721 * On family 10h BIOS may not have properly enabled WC+ support,
722 * causing it to be converted to CD memtype. This may result in
723 * performance degradation for certain nested-paging guests.
724 * Prevent this conversion by clearing bit 24 in
727 * NOTE: we want to use the _safe accessors so as not to #GP kvm
728 * guests on older kvm hosts.
731 rdmsrl_safe(MSR_AMD64_BU_CFG2
, &value
);
732 value
&= ~(1ULL << 24);
733 wrmsrl_safe(MSR_AMD64_BU_CFG2
, value
);
736 rdmsr_safe(MSR_AMD64_PATCH_LEVEL
, &c
->microcode
, &dummy
);
740 static unsigned int __cpuinit
amd_size_cache(struct cpuinfo_x86
*c
,
743 /* AMD errata T13 (order #21922) */
746 if (c
->x86_model
== 3 && c
->x86_mask
== 0)
748 /* Tbird rev A1/A2 */
749 if (c
->x86_model
== 4 &&
750 (c
->x86_mask
== 0 || c
->x86_mask
== 1))
757 static void __cpuinit
cpu_set_tlb_flushall_shift(struct cpuinfo_x86
*c
)
759 tlb_flushall_shift
= 5;
762 tlb_flushall_shift
= 4;
765 static void __cpuinit
cpu_detect_tlb_amd(struct cpuinfo_x86
*c
)
767 u32 ebx
, eax
, ecx
, edx
;
773 if (c
->extended_cpuid_level
< 0x80000006)
776 cpuid(0x80000006, &eax
, &ebx
, &ecx
, &edx
);
778 tlb_lld_4k
[ENTRIES
] = (ebx
>> 16) & mask
;
779 tlb_lli_4k
[ENTRIES
] = ebx
& mask
;
782 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
783 * characteristics from the CPUID function 0x80000005 instead.
786 cpuid(0x80000005, &eax
, &ebx
, &ecx
, &edx
);
790 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
791 if (!((eax
>> 16) & mask
)) {
794 cpuid(0x80000005, &a
, &b
, &c
, &d
);
795 tlb_lld_2m
[ENTRIES
] = (a
>> 16) & 0xff;
797 tlb_lld_2m
[ENTRIES
] = (eax
>> 16) & mask
;
800 /* a 4M entry uses two 2M entries */
801 tlb_lld_4m
[ENTRIES
] = tlb_lld_2m
[ENTRIES
] >> 1;
803 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
806 if (c
->x86
== 0x15 && c
->x86_model
<= 0x1f) {
807 tlb_lli_2m
[ENTRIES
] = 1024;
809 cpuid(0x80000005, &eax
, &ebx
, &ecx
, &edx
);
810 tlb_lli_2m
[ENTRIES
] = eax
& 0xff;
813 tlb_lli_2m
[ENTRIES
] = eax
& mask
;
815 tlb_lli_4m
[ENTRIES
] = tlb_lli_2m
[ENTRIES
] >> 1;
817 cpu_set_tlb_flushall_shift(c
);
820 static const struct cpu_dev __cpuinitconst amd_cpu_dev
= {
822 .c_ident
= { "AuthenticAMD" },
825 { .vendor
= X86_VENDOR_AMD
, .family
= 4, .model_names
=
836 .c_size_cache
= amd_size_cache
,
838 .c_early_init
= early_init_amd
,
839 .c_detect_tlb
= cpu_detect_tlb_amd
,
840 .c_bsp_init
= bsp_init_amd
,
842 .c_x86_vendor
= X86_VENDOR_AMD
,
845 cpu_dev_register(amd_cpu_dev
);
848 * AMD errata checking
850 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
851 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
852 * have an OSVW id assigned, which it takes as first argument. Both take a
853 * variable number of family-specific model-stepping ranges created by
854 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
855 * int[] in arch/x86/include/asm/processor.h.
859 * const int amd_erratum_319[] =
860 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
861 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
862 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
865 const int amd_erratum_400
[] =
866 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
867 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
868 EXPORT_SYMBOL_GPL(amd_erratum_400
);
870 const int amd_erratum_383
[] =
871 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
872 EXPORT_SYMBOL_GPL(amd_erratum_383
);
874 bool cpu_has_amd_erratum(const int *erratum
)
876 struct cpuinfo_x86
*cpu
= __this_cpu_ptr(&cpu_info
);
877 int osvw_id
= *erratum
++;
882 * If called early enough that current_cpu_data hasn't been initialized
883 * yet, fall back to boot_cpu_data.
886 cpu
= &boot_cpu_data
;
888 if (cpu
->x86_vendor
!= X86_VENDOR_AMD
)
891 if (osvw_id
>= 0 && osvw_id
< 65536 &&
892 cpu_has(cpu
, X86_FEATURE_OSVW
)) {
895 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH
, osvw_len
);
896 if (osvw_id
< osvw_len
) {
899 rdmsrl(MSR_AMD64_OSVW_STATUS
+ (osvw_id
>> 6),
901 return osvw_bits
& (1ULL << (osvw_id
& 0x3f));
905 /* OSVW unavailable or ID unknown, match family-model-stepping range */
906 ms
= (cpu
->x86_model
<< 4) | cpu
->x86_mask
;
907 while ((range
= *erratum
++))
908 if ((cpu
->x86
== AMD_MODEL_RANGE_FAMILY(range
)) &&
909 (ms
>= AMD_MODEL_RANGE_START(range
)) &&
910 (ms
<= AMD_MODEL_RANGE_END(range
)))
916 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum
);