arch/x86/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4 #include <asm/io.h>
   5 #include <asm/processor.h>
   6 #include <asm/apic.h>
   7
   8 #include <mach_apic.h>
   9 #include "cpu.h"
  10
  11 /*
  12  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  13  *      misexecution of code under Linux. Owners of such processors should
  14  *      contact AMD for precise details and a CPU swap.
  15  *
  16  *      See     http://www.multimania.com/poulot/k6bug.html
  17  *              http://www.amd.com/K6/k6docs/revgd.html
  18  *
  19  *      The following test is erm.. interesting. AMD neglected to up
  20  *      the chip setting when fixing the bug but they also tweaked some
  21  *      performance at the same time..
  22  */
  23
  24 extern void vide(void);
  25 __asm__(".align 4\nvide: ret");
  26
  27 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  28 {
  29         if (c->x86_power & (1<<8))
  30                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  31
  32         /*  Set MTRR capability flag if appropriate */
  33         if (c->x86_model == 13 || c->x86_model == 9 ||
  34            (c->x86_model == 8 && c->x86_mask >= 8))
  35                 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
  36 }
  37
  38 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  39 {
  40         u32 l, h;
  41         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  42
  43 #ifdef CONFIG_SMP
  44         unsigned long long value;
  45
  46         /*
  47          * Disable TLB flush filter by setting HWCR.FFDIS on K8
  48          * bit 6 of msr C001_0015
  49          *
  50          * Errata 63 for SH-B3 steppings
  51          * Errata 122 for all steppings (F+ have it disabled by default)
  52          */
  53         if (c->x86 == 15) {
  54                 rdmsrl(MSR_K7_HWCR, value);
  55                 value |= 1 << 6;
  56                 wrmsrl(MSR_K7_HWCR, value);
  57         }
  58 #endif
  59
  60         early_init_amd(c);
  61
  62         /*
  63          *      FIXME: We should handle the K5 here. Set up the write
  64          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
  65          *      no bus pipeline)
  66          */
  67
  68         /*
  69          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  70          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
  71          */
  72         clear_cpu_cap(c, 0*32+31);
  73
  74         switch (c->x86) {
  75         case 4:
  76                 /*
  77                  * General Systems BIOSen alias the cpu frequency registers
  78                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
  79                  * drivers subsequently pokes it, and changes the CPU speed.
  80                  * Workaround : Remove the unneeded alias.
  81                  */
  82 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
  83 #define CBAR_ENB        (0x80000000)
  84 #define CBAR_KEY        (0X000000CB)
  85                         if (c->x86_model == 9 || c->x86_model == 10) {
  86                                 if (inl (CBAR) & CBAR_ENB)
  87                                         outl (0 | CBAR_KEY, CBAR);
  88                         }
  89                         break;
  90         case 5:
  91                         if (c->x86_model < 6) {
  92                                 /* Based on AMD doc 20734R - June 2000 */
  93                                 if (c->x86_model == 0) {
  94                                         clear_cpu_cap(c, X86_FEATURE_APIC);
  95                                         set_cpu_cap(c, X86_FEATURE_PGE);
  96                                 }
  97                                 break;
  98                         }
  99
 100                         if (c->x86_model == 6 && c->x86_mask == 1) {
 101                                 const int K6_BUG_LOOP = 1000000;
 102                                 int n;
 103                                 void (*f_vide)(void);
 104                                 unsigned long d, d2;
 105
 106                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
 107
 108                                 /*
 109                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
 110                                  * calls at the same time.
 111                                  */
 112
 113                                 n = K6_BUG_LOOP;
 114                                 f_vide = vide;
 115                                 rdtscl(d);
 116                                 while (n--)
 117                                         f_vide();
 118                                 rdtscl(d2);
 119                                 d = d2-d;
 120
 121                                 if (d > 20*K6_BUG_LOOP)
 122                                         printk("system stability may be impaired when more than 32 MB are used.\n");
 123                                 else
 124                                         printk("probably OK (after B9730xxxx).\n");
 125                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
 126                         }
 127
 128                         /* K6 with old style WHCR */
 129                         if (c->x86_model < 8 ||
 130                            (c->x86_model == 8 && c->x86_mask < 8)) {
 131                                 /* We can only write allocate on the low 508Mb */
 132                                 if (mbytes > 508)
 133                                         mbytes = 508;
 134
 135                                 rdmsr(MSR_K6_WHCR, l, h);
 136                                 if ((l&0x0000FFFF) == 0) {
 137                                         unsigned long flags;
 138                                         l = (1<<0)|((mbytes/4)<<1);
 139                                         local_irq_save(flags);
 140                                         wbinvd();
 141                                         wrmsr(MSR_K6_WHCR, l, h);
 142                                         local_irq_restore(flags);
 143                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 144                                                 mbytes);
 145                                 }
 146                                 break;
 147                         }
 148
 149                         if ((c->x86_model == 8 && c->x86_mask > 7) ||
 150                              c->x86_model == 9 || c->x86_model == 13) {
 151                                 /* The more serious chips .. */
 152
 153                                 if (mbytes > 4092)
 154                                         mbytes = 4092;
 155
 156                                 rdmsr(MSR_K6_WHCR, l, h);
 157                                 if ((l&0xFFFF0000) == 0) {
 158                                         unsigned long flags;
 159                                         l = ((mbytes>>2)<<22)|(1<<16);
 160                                         local_irq_save(flags);
 161                                         wbinvd();
 162                                         wrmsr(MSR_K6_WHCR, l, h);
 163                                         local_irq_restore(flags);
 164                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 165                                                 mbytes);
 166                                 }
 167
 168                                 break;
 169                         }
 170
 171                         if (c->x86_model == 10) {
 172                                 /* AMD Geode LX is model 10 */
 173                                 /* placeholder for any needed mods */
 174                                 break;
 175                         }
 176                         break;
 177         case 6: /* An Athlon/Duron */
 178
 179                         /*
 180                          * Bit 15 of Athlon specific MSR 15, needs to be 0
 181                          * to enable SSE on Palomino/Morgan/Barton CPU's.
 182                          * If the BIOS didn't enable it already, enable it here.
 183                          */
 184                         if (c->x86_model >= 6 && c->x86_model <= 10) {
 185                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 186                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 187                                         rdmsr(MSR_K7_HWCR, l, h);
 188                                         l &= ~0x00008000;
 189                                         wrmsr(MSR_K7_HWCR, l, h);
 190                                         set_cpu_cap(c, X86_FEATURE_XMM);
 191                                 }
 192                         }
 193
 194                         /*
 195                          * It's been determined by AMD that Athlons since model 8 stepping 1
 196                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 197                          * As per AMD technical note 27212 0.2
 198                          */
 199                         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
 200                                 rdmsr(MSR_K7_CLK_CTL, l, h);
 201                                 if ((l & 0xfff00000) != 0x20000000) {
 202                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
 203                                                 ((l & 0x000fffff)|0x20000000));
 204                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 205                                 }
 206                         }
 207                         break;
 208         }
 209
 210         switch (c->x86) {
 211         case 15:
 212         /* Use K8 tuning for Fam10h and Fam11h */
 213         case 0x10:
 214         case 0x11:
 215                 set_cpu_cap(c, X86_FEATURE_K8);
 216                 break;
 217         case 6:
 218                 set_cpu_cap(c, X86_FEATURE_K7);
 219                 break;
 220         }
 221         if (c->x86 >= 6)
 222                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 223
 224         display_cacheinfo(c);
 225
 226         if (cpuid_eax(0x80000000) >= 0x80000008)
 227                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
 228
 229 #ifdef CONFIG_X86_HT
 230         /*
 231          * On a AMD multi core setup the lower bits of the APIC id
 232          * distinguish the cores.
 233          */
 234         if (c->x86_max_cores > 1) {
 235                 int cpu = smp_processor_id();
 236                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
 237
 238                 if (bits == 0) {
 239                         while ((1 << bits) < c->x86_max_cores)
 240                                 bits++;
 241                 }
 242                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
 243                 c->phys_proc_id >>= bits;
 244                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
 245                        cpu, c->x86_max_cores, c->cpu_core_id);
 246         }
 247 #endif
 248
 249         if (cpuid_eax(0x80000000) >= 0x80000006) {
 250                 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
 251                         num_cache_leaves = 4;
 252                 else
 253                         num_cache_leaves = 3;
 254         }
 255
 256         /* K6s reports MCEs but don't actually have all the MSRs */
 257         if (c->x86 < 6)
 258                 clear_cpu_cap(c, X86_FEATURE_MCE);
 259
 260         if (cpu_has_xmm2)
 261                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 262 }
 263
 264 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 265 {
 266         /* AMD errata T13 (order #21922) */
 267         if ((c->x86 == 6)) {
 268                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
 269                         size = 64;
 270                 if (c->x86_model == 4 &&
 271                     (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
 272                         size = 256;
 273         }
 274         return size;
 275 }
 276
 277 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
 278         .c_vendor       = "AMD",
 279         .c_ident        = { "AuthenticAMD" },
 280         .c_models = {
 281                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 282                   {
 283                           [3] = "486 DX/2",
 284                           [7] = "486 DX/2-WB",
 285                           [8] = "486 DX/4",
 286                           [9] = "486 DX/4-WB",
 287                           [14] = "Am5x86-WT",
 288                           [15] = "Am5x86-WB"
 289                   }
 290                 },
 291         },
 292         .c_early_init   = early_init_amd,
 293         .c_init         = init_amd,
 294         .c_size_cache   = amd_size_cache,
 295         .c_x86_vendor   = X86_VENDOR_AMD,
 296 };
 297
 298 cpu_dev_register(amd_cpu_dev);