1 #include <linux/export.h>
2 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/random.h>
9 #include <asm/processor.h>
13 #include <asm/pci-direct.h>
14 #include <asm/delay.h>
17 # include <asm/mmconfig.h>
18 # include <asm/cacheflush.h>
24 * nodes_per_socket: Stores the number of nodes per socket.
25 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
26 * Node Identifiers[10:8]
28 static u32 nodes_per_socket
= 1;
30 static inline int rdmsrl_amd_safe(unsigned msr
, unsigned long long *p
)
35 WARN_ONCE((boot_cpu_data
.x86
!= 0xf),
36 "%s should only be used on K8!\n", __func__
);
41 err
= rdmsr_safe_regs(gprs
);
43 *p
= gprs
[0] | ((u64
)gprs
[2] << 32);
48 static inline int wrmsrl_amd_safe(unsigned msr
, unsigned long long val
)
52 WARN_ONCE((boot_cpu_data
.x86
!= 0xf),
53 "%s should only be used on K8!\n", __func__
);
60 return wrmsr_safe_regs(gprs
);
64 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
65 * misexecution of code under Linux. Owners of such processors should
66 * contact AMD for precise details and a CPU swap.
68 * See http://www.multimania.com/poulot/k6bug.html
69 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
70 * (Publication # 21266 Issue Date: August 1998)
72 * The following test is erm.. interesting. AMD neglected to up
73 * the chip setting when fixing the bug but they also tweaked some
74 * performance at the same time..
77 extern __visible
void vide(void);
78 __asm__(".globl vide\n\t.align 4\nvide: ret");
80 static void init_amd_k5(struct cpuinfo_x86
*c
)
84 * General Systems BIOSen alias the cpu frequency registers
85 * of the Elan at 0x000df000. Unfortunately, one of the Linux
86 * drivers subsequently pokes it, and changes the CPU speed.
87 * Workaround : Remove the unneeded alias.
89 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
90 #define CBAR_ENB (0x80000000)
91 #define CBAR_KEY (0X000000CB)
92 if (c
->x86_model
== 9 || c
->x86_model
== 10) {
93 if (inl(CBAR
) & CBAR_ENB
)
94 outl(0 | CBAR_KEY
, CBAR
);
99 static void init_amd_k6(struct cpuinfo_x86
*c
)
103 int mbytes
= get_num_physpages() >> (20-PAGE_SHIFT
);
105 if (c
->x86_model
< 6) {
106 /* Based on AMD doc 20734R - June 2000 */
107 if (c
->x86_model
== 0) {
108 clear_cpu_cap(c
, X86_FEATURE_APIC
);
109 set_cpu_cap(c
, X86_FEATURE_PGE
);
114 if (c
->x86_model
== 6 && c
->x86_mask
== 1) {
115 const int K6_BUG_LOOP
= 1000000;
117 void (*f_vide
)(void);
120 pr_info("AMD K6 stepping B detected - ");
123 * It looks like AMD fixed the 2.6.2 bug and improved indirect
124 * calls at the same time.
135 if (d
> 20*K6_BUG_LOOP
)
136 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
138 pr_cont("probably OK (after B9730xxxx).\n");
141 /* K6 with old style WHCR */
142 if (c
->x86_model
< 8 ||
143 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
144 /* We can only write allocate on the low 508Mb */
148 rdmsr(MSR_K6_WHCR
, l
, h
);
149 if ((l
&0x0000FFFF) == 0) {
151 l
= (1<<0)|((mbytes
/4)<<1);
152 local_irq_save(flags
);
154 wrmsr(MSR_K6_WHCR
, l
, h
);
155 local_irq_restore(flags
);
156 pr_info("Enabling old style K6 write allocation for %d Mb\n",
162 if ((c
->x86_model
== 8 && c
->x86_mask
> 7) ||
163 c
->x86_model
== 9 || c
->x86_model
== 13) {
164 /* The more serious chips .. */
169 rdmsr(MSR_K6_WHCR
, l
, h
);
170 if ((l
&0xFFFF0000) == 0) {
172 l
= ((mbytes
>>2)<<22)|(1<<16);
173 local_irq_save(flags
);
175 wrmsr(MSR_K6_WHCR
, l
, h
);
176 local_irq_restore(flags
);
177 pr_info("Enabling new style K6 write allocation for %d Mb\n",
184 if (c
->x86_model
== 10) {
185 /* AMD Geode LX is model 10 */
186 /* placeholder for any needed mods */
192 static void init_amd_k7(struct cpuinfo_x86
*c
)
198 * Bit 15 of Athlon specific MSR 15, needs to be 0
199 * to enable SSE on Palomino/Morgan/Barton CPU's.
200 * If the BIOS didn't enable it already, enable it here.
202 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
203 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
204 pr_info("Enabling disabled K7/SSE Support.\n");
205 msr_clear_bit(MSR_K7_HWCR
, 15);
206 set_cpu_cap(c
, X86_FEATURE_XMM
);
211 * It's been determined by AMD that Athlons since model 8 stepping 1
212 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
213 * As per AMD technical note 27212 0.2
215 if ((c
->x86_model
== 8 && c
->x86_mask
>= 1) || (c
->x86_model
> 8)) {
216 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
217 if ((l
& 0xfff00000) != 0x20000000) {
218 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
219 l
, ((l
& 0x000fffff)|0x20000000));
220 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
224 set_cpu_cap(c
, X86_FEATURE_K7
);
226 /* calling is from identify_secondary_cpu() ? */
231 * Certain Athlons might work (for various values of 'work') in SMP
232 * but they are not certified as MP capable.
234 /* Athlon 660/661 is valid. */
235 if ((c
->x86_model
== 6) && ((c
->x86_mask
== 0) ||
239 /* Duron 670 is valid */
240 if ((c
->x86_model
== 7) && (c
->x86_mask
== 0))
244 * Athlon 662, Duron 671, and Athlon >model 7 have capability
245 * bit. It's worth noting that the A5 stepping (662) of some
246 * Athlon XP's have the MP bit set.
247 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
250 if (((c
->x86_model
== 6) && (c
->x86_mask
>= 2)) ||
251 ((c
->x86_model
== 7) && (c
->x86_mask
>= 1)) ||
253 if (cpu_has(c
, X86_FEATURE_MP
))
256 /* If we get here, not a certified SMP capable AMD system. */
259 * Don't taint if we are running SMP kernel on a single non-MP
262 WARN_ONCE(1, "WARNING: This combination of AMD"
263 " processors is not suitable for SMP.\n");
264 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_NOW_UNRELIABLE
);
270 * To workaround broken NUMA config. Read the comment in
271 * srat_detect_node().
273 static int nearby_node(int apicid
)
277 for (i
= apicid
- 1; i
>= 0; i
--) {
278 node
= __apicid_to_node
[i
];
279 if (node
!= NUMA_NO_NODE
&& node_online(node
))
282 for (i
= apicid
+ 1; i
< MAX_LOCAL_APIC
; i
++) {
283 node
= __apicid_to_node
[i
];
284 if (node
!= NUMA_NO_NODE
&& node_online(node
))
287 return first_node(node_online_map
); /* Shouldn't happen */
292 * Fixup core topology information for
293 * (1) AMD multi-node processors
294 * Assumption: Number of cores in each internal node is the same.
295 * (2) AMD processors supporting compute units
298 static void amd_get_topology(struct cpuinfo_x86
*c
)
300 u32 cores_per_cu
= 1;
302 int cpu
= smp_processor_id();
304 /* get information required for multi-node processors */
305 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
306 u32 eax
, ebx
, ecx
, edx
;
308 cpuid(0x8000001e, &eax
, &ebx
, &ecx
, &edx
);
311 /* get compute unit information */
312 smp_num_siblings
= ((ebx
>> 8) & 3) + 1;
313 c
->compute_unit_id
= ebx
& 0xff;
314 cores_per_cu
+= ((ebx
>> 8) & 3);
315 } else if (cpu_has(c
, X86_FEATURE_NODEID_MSR
)) {
318 rdmsrl(MSR_FAM10H_NODE_ID
, value
);
323 /* fixup multi-node processor information */
324 if (nodes_per_socket
> 1) {
328 set_cpu_cap(c
, X86_FEATURE_AMD_DCM
);
329 cores_per_node
= c
->x86_max_cores
/ nodes_per_socket
;
330 cus_per_node
= cores_per_node
/ cores_per_cu
;
332 /* store NodeID, use llc_shared_map to store sibling info */
333 per_cpu(cpu_llc_id
, cpu
) = node_id
;
335 /* core id has to be in the [0 .. cores_per_node - 1] range */
336 c
->cpu_core_id
%= cores_per_node
;
337 c
->compute_unit_id
%= cus_per_node
;
343 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
344 * Assumes number of cores is a power of two.
346 static void amd_detect_cmp(struct cpuinfo_x86
*c
)
350 int cpu
= smp_processor_id();
351 unsigned int socket_id
, core_complex_id
;
353 bits
= c
->x86_coreid_bits
;
354 /* Low order bits define the core id (index of core in socket) */
355 c
->cpu_core_id
= c
->initial_apicid
& ((1 << bits
)-1);
356 /* Convert the initial APIC ID into the socket ID */
357 c
->phys_proc_id
= c
->initial_apicid
>> bits
;
358 /* use socket ID also for last level cache */
359 per_cpu(cpu_llc_id
, cpu
) = c
->phys_proc_id
;
363 * Fix percpu cpu_llc_id here as LLC topology is different
364 * for Fam17h systems.
366 if (c
->x86
!= 0x17 || !cpuid_edx(0x80000006))
369 socket_id
= (c
->apicid
>> bits
) - 1;
370 core_complex_id
= (c
->apicid
& ((1 << bits
) - 1)) >> 3;
372 per_cpu(cpu_llc_id
, cpu
) = (socket_id
<< 3) | core_complex_id
;
376 u16
amd_get_nb_id(int cpu
)
380 id
= per_cpu(cpu_llc_id
, cpu
);
384 EXPORT_SYMBOL_GPL(amd_get_nb_id
);
386 u32
amd_get_nodes_per_socket(void)
388 return nodes_per_socket
;
390 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket
);
392 static void srat_detect_node(struct cpuinfo_x86
*c
)
395 int cpu
= smp_processor_id();
397 unsigned apicid
= c
->apicid
;
399 node
= numa_cpu_node(cpu
);
400 if (node
== NUMA_NO_NODE
)
401 node
= per_cpu(cpu_llc_id
, cpu
);
404 * On multi-fabric platform (e.g. Numascale NumaChip) a
405 * platform-specific handler needs to be called to fixup some
408 if (x86_cpuinit
.fixup_cpu_id
)
409 x86_cpuinit
.fixup_cpu_id(c
, node
);
411 if (!node_online(node
)) {
413 * Two possibilities here:
415 * - The CPU is missing memory and no node was created. In
416 * that case try picking one from a nearby CPU.
418 * - The APIC IDs differ from the HyperTransport node IDs
419 * which the K8 northbridge parsing fills in. Assume
420 * they are all increased by a constant offset, but in
421 * the same order as the HT nodeids. If that doesn't
422 * result in a usable node fall back to the path for the
425 * This workaround operates directly on the mapping between
426 * APIC ID and NUMA node, assuming certain relationship
427 * between APIC ID, HT node ID and NUMA topology. As going
428 * through CPU mapping may alter the outcome, directly
429 * access __apicid_to_node[].
431 int ht_nodeid
= c
->initial_apicid
;
433 if (__apicid_to_node
[ht_nodeid
] != NUMA_NO_NODE
)
434 node
= __apicid_to_node
[ht_nodeid
];
435 /* Pick a nearby node */
436 if (!node_online(node
))
437 node
= nearby_node(apicid
);
439 numa_set_node(cpu
, node
);
443 static void early_init_amd_mc(struct cpuinfo_x86
*c
)
448 /* Multi core CPU? */
449 if (c
->extended_cpuid_level
< 0x80000008)
452 ecx
= cpuid_ecx(0x80000008);
454 c
->x86_max_cores
= (ecx
& 0xff) + 1;
456 /* CPU telling us the core id bits shift? */
457 bits
= (ecx
>> 12) & 0xF;
459 /* Otherwise recompute */
461 while ((1 << bits
) < c
->x86_max_cores
)
465 c
->x86_coreid_bits
= bits
;
469 static void bsp_init_amd(struct cpuinfo_x86
*c
)
474 unsigned long long tseg
;
477 * Split up direct mapping around the TSEG SMM area.
478 * Don't do it for gbpages because there seems very little
479 * benefit in doing so.
481 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR
, &tseg
)) {
482 unsigned long pfn
= tseg
>> PAGE_SHIFT
;
484 pr_debug("tseg: %010llx\n", tseg
);
485 if (pfn_range_is_mapped(pfn
, pfn
+ 1))
486 set_memory_4k((unsigned long)__va(tseg
), 1);
491 if (cpu_has(c
, X86_FEATURE_CONSTANT_TSC
)) {
494 (c
->x86
== 0x10 && c
->x86_model
>= 0x2)) {
497 rdmsrl(MSR_K7_HWCR
, val
);
498 if (!(val
& BIT(24)))
499 pr_warn(FW_BUG
"TSC doesn't count with P0 frequency!\n");
503 if (c
->x86
== 0x15) {
504 unsigned long upperbit
;
507 cpuid
= cpuid_edx(0x80000005);
508 assoc
= cpuid
>> 16 & 0xff;
509 upperbit
= ((cpuid
>> 24) << 10) / assoc
;
511 va_align
.mask
= (upperbit
- 1) & PAGE_MASK
;
512 va_align
.flags
= ALIGN_VA_32
| ALIGN_VA_64
;
514 /* A random value per boot for bit slice [12:upper_bit) */
515 va_align
.bits
= get_random_int() & va_align
.mask
;
518 if (cpu_has(c
, X86_FEATURE_MWAITX
))
521 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
524 ecx
= cpuid_ecx(0x8000001e);
525 nodes_per_socket
= ((ecx
>> 8) & 7) + 1;
526 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR
)) {
529 rdmsrl(MSR_FAM10H_NODE_ID
, value
);
530 nodes_per_socket
= ((value
>> 3) & 7) + 1;
534 static void early_init_amd(struct cpuinfo_x86
*c
)
536 early_init_amd_mc(c
);
539 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
540 * with P/T states and does not stop in deep C-states
542 if (c
->x86_power
& (1 << 8)) {
543 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
544 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
545 if (!check_tsc_unstable())
546 set_sched_clock_stable();
550 set_cpu_cap(c
, X86_FEATURE_SYSCALL32
);
552 /* Set MTRR capability flag if appropriate */
554 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
555 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
556 set_cpu_cap(c
, X86_FEATURE_K6_MTRR
);
558 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
560 * ApicID can always be treated as an 8-bit value for AMD APIC versions
561 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
562 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
565 if (cpu_has_apic
&& c
->x86
> 0x16) {
566 set_cpu_cap(c
, X86_FEATURE_EXTD_APICID
);
567 } else if (cpu_has_apic
&& c
->x86
>= 0xf) {
568 /* check CPU config space for extended APIC ID */
570 val
= read_pci_config(0, 24, 0, 0x68);
571 if ((val
& ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
572 set_cpu_cap(c
, X86_FEATURE_EXTD_APICID
);
577 * This is only needed to tell the kernel whether to use VMCALL
578 * and VMMCALL. VMMCALL is never executed except under virt, so
579 * we can set it unconditionally.
581 set_cpu_cap(c
, X86_FEATURE_VMMCALL
);
583 /* F16h erratum 793, CVE-2013-6885 */
584 if (c
->x86
== 0x16 && c
->x86_model
<= 0xf)
585 msr_set_bit(MSR_AMD64_LS_CFG
, 15);
588 static const int amd_erratum_383
[];
589 static const int amd_erratum_400
[];
590 static bool cpu_has_amd_erratum(struct cpuinfo_x86
*cpu
, const int *erratum
);
592 static void init_amd_k8(struct cpuinfo_x86
*c
)
597 /* On C+ stepping K8 rep microcode works well for copy/memset */
598 level
= cpuid_eax(1);
599 if ((level
>= 0x0f48 && level
< 0x0f50) || level
>= 0x0f58)
600 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
603 * Some BIOSes incorrectly force this feature, but only K8 revision D
604 * (model = 0x14) and later actually support it.
605 * (AMD Erratum #110, docId: 25759).
607 if (c
->x86_model
< 0x14 && cpu_has(c
, X86_FEATURE_LAHF_LM
)) {
608 clear_cpu_cap(c
, X86_FEATURE_LAHF_LM
);
609 if (!rdmsrl_amd_safe(0xc001100d, &value
)) {
610 value
&= ~BIT_64(32);
611 wrmsrl_amd_safe(0xc001100d, value
);
615 if (!c
->x86_model_id
[0])
616 strcpy(c
->x86_model_id
, "Hammer");
620 * Disable TLB flush filter by setting HWCR.FFDIS on K8
621 * bit 6 of msr C001_0015
623 * Errata 63 for SH-B3 steppings
624 * Errata 122 for all steppings (F+ have it disabled by default)
626 msr_set_bit(MSR_K7_HWCR
, 6);
630 static void init_amd_gh(struct cpuinfo_x86
*c
)
633 /* do this for boot cpu */
634 if (c
== &boot_cpu_data
)
635 check_enable_amd_mmconf_dmi();
637 fam10h_check_enable_mmcfg();
641 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
642 * is always needed when GART is enabled, even in a kernel which has no
643 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
644 * If it doesn't, we do it here as suggested by the BKDG.
646 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
648 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
651 * On family 10h BIOS may not have properly enabled WC+ support, causing
652 * it to be converted to CD memtype. This may result in performance
653 * degradation for certain nested-paging guests. Prevent this conversion
654 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
656 * NOTE: we want to use the _safe accessors so as not to #GP kvm
657 * guests on older kvm hosts.
659 msr_clear_bit(MSR_AMD64_BU_CFG2
, 24);
661 if (cpu_has_amd_erratum(c
, amd_erratum_383
))
662 set_cpu_bug(c
, X86_BUG_AMD_TLB_MMATCH
);
665 static void init_amd_bd(struct cpuinfo_x86
*c
)
669 /* re-enable TopologyExtensions if switched off by BIOS */
670 if ((c
->x86_model
>= 0x10) && (c
->x86_model
<= 0x1f) &&
671 !cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
673 if (msr_set_bit(0xc0011005, 54) > 0) {
674 rdmsrl(0xc0011005, value
);
675 if (value
& BIT_64(54)) {
676 set_cpu_cap(c
, X86_FEATURE_TOPOEXT
);
677 pr_info(FW_INFO
"CPU: Re-enabling disabled Topology Extensions Support.\n");
683 * The way access filter has a performance penalty on some workloads.
684 * Disable it on the affected CPUs.
686 if ((c
->x86_model
>= 0x02) && (c
->x86_model
< 0x20)) {
687 if (!rdmsrl_safe(MSR_F15H_IC_CFG
, &value
) && !(value
& 0x1E)) {
689 wrmsrl_safe(MSR_F15H_IC_CFG
, value
);
694 static void init_amd(struct cpuinfo_x86
*c
)
701 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
702 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
704 clear_cpu_cap(c
, 0*32+31);
707 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
709 /* get apicid instead of initial apic id from cpuid */
710 c
->apicid
= hard_smp_processor_id();
712 /* K6s reports MCEs but don't actually have all the MSRs */
714 clear_cpu_cap(c
, X86_FEATURE_MCE
);
717 case 4: init_amd_k5(c
); break;
718 case 5: init_amd_k6(c
); break;
719 case 6: init_amd_k7(c
); break;
720 case 0xf: init_amd_k8(c
); break;
721 case 0x10: init_amd_gh(c
); break;
722 case 0x15: init_amd_bd(c
); break;
725 /* Enable workaround for FXSAVE leak */
727 set_cpu_bug(c
, X86_BUG_FXSAVE_LEAK
);
729 cpu_detect_cache_sizes(c
);
731 /* Multi core CPU? */
732 if (c
->extended_cpuid_level
>= 0x80000008) {
741 init_amd_cacheinfo(c
);
744 set_cpu_cap(c
, X86_FEATURE_K8
);
747 /* MFENCE stops RDTSC speculation */
748 set_cpu_cap(c
, X86_FEATURE_MFENCE_RDTSC
);
752 * Family 0x12 and above processors have APIC timer
753 * running in deep C states.
756 set_cpu_cap(c
, X86_FEATURE_ARAT
);
758 if (cpu_has_amd_erratum(c
, amd_erratum_400
))
759 set_cpu_bug(c
, X86_BUG_AMD_APIC_C1E
);
761 rdmsr_safe(MSR_AMD64_PATCH_LEVEL
, &c
->microcode
, &dummy
);
763 /* 3DNow or LM implies PREFETCHW */
764 if (!cpu_has(c
, X86_FEATURE_3DNOWPREFETCH
))
765 if (cpu_has(c
, X86_FEATURE_3DNOW
) || cpu_has(c
, X86_FEATURE_LM
))
766 set_cpu_cap(c
, X86_FEATURE_3DNOWPREFETCH
);
768 /* AMD CPUs don't reset SS attributes on SYSRET */
769 set_cpu_bug(c
, X86_BUG_SYSRET_SS_ATTRS
);
773 static unsigned int amd_size_cache(struct cpuinfo_x86
*c
, unsigned int size
)
775 /* AMD errata T13 (order #21922) */
778 if (c
->x86_model
== 3 && c
->x86_mask
== 0)
780 /* Tbird rev A1/A2 */
781 if (c
->x86_model
== 4 &&
782 (c
->x86_mask
== 0 || c
->x86_mask
== 1))
789 static void cpu_detect_tlb_amd(struct cpuinfo_x86
*c
)
791 u32 ebx
, eax
, ecx
, edx
;
797 if (c
->extended_cpuid_level
< 0x80000006)
800 cpuid(0x80000006, &eax
, &ebx
, &ecx
, &edx
);
802 tlb_lld_4k
[ENTRIES
] = (ebx
>> 16) & mask
;
803 tlb_lli_4k
[ENTRIES
] = ebx
& mask
;
806 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
807 * characteristics from the CPUID function 0x80000005 instead.
810 cpuid(0x80000005, &eax
, &ebx
, &ecx
, &edx
);
814 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
815 if (!((eax
>> 16) & mask
))
816 tlb_lld_2m
[ENTRIES
] = (cpuid_eax(0x80000005) >> 16) & 0xff;
818 tlb_lld_2m
[ENTRIES
] = (eax
>> 16) & mask
;
820 /* a 4M entry uses two 2M entries */
821 tlb_lld_4m
[ENTRIES
] = tlb_lld_2m
[ENTRIES
] >> 1;
823 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
826 if (c
->x86
== 0x15 && c
->x86_model
<= 0x1f) {
827 tlb_lli_2m
[ENTRIES
] = 1024;
829 cpuid(0x80000005, &eax
, &ebx
, &ecx
, &edx
);
830 tlb_lli_2m
[ENTRIES
] = eax
& 0xff;
833 tlb_lli_2m
[ENTRIES
] = eax
& mask
;
835 tlb_lli_4m
[ENTRIES
] = tlb_lli_2m
[ENTRIES
] >> 1;
838 static const struct cpu_dev amd_cpu_dev
= {
840 .c_ident
= { "AuthenticAMD" },
843 { .family
= 4, .model_names
=
854 .legacy_cache_size
= amd_size_cache
,
856 .c_early_init
= early_init_amd
,
857 .c_detect_tlb
= cpu_detect_tlb_amd
,
858 .c_bsp_init
= bsp_init_amd
,
860 .c_x86_vendor
= X86_VENDOR_AMD
,
863 cpu_dev_register(amd_cpu_dev
);
866 * AMD errata checking
868 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
869 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
870 * have an OSVW id assigned, which it takes as first argument. Both take a
871 * variable number of family-specific model-stepping ranges created by
876 * const int amd_erratum_319[] =
877 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
878 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
879 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
882 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
883 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
884 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
885 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
886 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
887 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
888 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
890 static const int amd_erratum_400
[] =
891 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
892 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
894 static const int amd_erratum_383
[] =
895 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
898 static bool cpu_has_amd_erratum(struct cpuinfo_x86
*cpu
, const int *erratum
)
900 int osvw_id
= *erratum
++;
904 if (osvw_id
>= 0 && osvw_id
< 65536 &&
905 cpu_has(cpu
, X86_FEATURE_OSVW
)) {
908 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH
, osvw_len
);
909 if (osvw_id
< osvw_len
) {
912 rdmsrl(MSR_AMD64_OSVW_STATUS
+ (osvw_id
>> 6),
914 return osvw_bits
& (1ULL << (osvw_id
& 0x3f));
918 /* OSVW unavailable or ID unknown, match family-model-stepping range */
919 ms
= (cpu
->x86_model
<< 4) | cpu
->x86_mask
;
920 while ((range
= *erratum
++))
921 if ((cpu
->x86
== AMD_MODEL_RANGE_FAMILY(range
)) &&
922 (ms
>= AMD_MODEL_RANGE_START(range
)) &&
923 (ms
<= AMD_MODEL_RANGE_END(range
)))
929 void set_dr_addr_mask(unsigned long mask
, int dr
)
931 if (!boot_cpu_has(X86_FEATURE_BPEXT
))
936 wrmsr(MSR_F16H_DR0_ADDR_MASK
, mask
, 0);
941 wrmsr(MSR_F16H_DR1_ADDR_MASK
- 1 + dr
, mask
, 0);