1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
34 static void __init
spectre_v2_select_mitigation(void);
35 static void __init
ssb_select_mitigation(void);
36 static void __init
l1tf_select_mitigation(void);
38 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
39 u64 x86_spec_ctrl_base
;
40 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
41 static DEFINE_MUTEX(spec_ctrl_mutex
);
44 * The vendor and possibly platform specific bits which can be modified in
47 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
50 * AMD specific MSR info for Speculative Store Bypass control.
51 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
53 u64 __ro_after_init x86_amd_ls_cfg_base
;
54 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
56 /* Control conditional STIBP in switch_to() */
57 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
58 /* Control conditional IBPB in switch_mm() */
59 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb
);
60 /* Control unconditional IBPB in switch_mm() */
61 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb
);
63 void __init
check_bugs(void)
68 * identify_boot_cpu() initialized SMT support information, let the
71 cpu_smt_check_topology_early();
73 if (!IS_ENABLED(CONFIG_SMP
)) {
75 print_cpu_info(&boot_cpu_data
);
79 * Read the SPEC_CTRL MSR to account for reserved bits which may
80 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
81 * init code as it is not enumerated and depends on the family.
83 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
84 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
86 /* Allow STIBP in MSR_SPEC_CTRL if supported */
87 if (boot_cpu_has(X86_FEATURE_STIBP
))
88 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
90 /* Select the proper spectre mitigation before patching alternatives */
91 spectre_v2_select_mitigation();
94 * Select proper mitigation for any exposure to the Speculative Store
95 * Bypass vulnerability.
97 ssb_select_mitigation();
99 l1tf_select_mitigation();
103 * Check whether we are able to run this kernel safely on SMP.
105 * - i386 is no longer supported.
106 * - In order to run on anything without a TSC, we need to be
107 * compiled for a i486.
109 if (boot_cpu_data
.x86
< 4)
110 panic("Kernel requires i486+ for 'invlpg' and other features");
112 init_utsname()->machine
[1] =
113 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
114 alternative_instructions();
116 fpu__init_check_bugs();
117 #else /* CONFIG_X86_64 */
118 alternative_instructions();
121 * Make sure the first 2MB area is not mapped by huge pages
122 * There are typically fixed size MTRRs in there and overlapping
123 * MTRRs into large pages causes slow downs.
125 * Right now we don't do that with gbpages because there seems
126 * very little benefit for that case.
129 set_memory_4k((unsigned long)__va(0), 1);
134 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
136 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
137 struct thread_info
*ti
= current_thread_info();
139 /* Is MSR_SPEC_CTRL implemented ? */
140 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
142 * Restrict guest_spec_ctrl to supported values. Clear the
143 * modifiable bits in the host base value and or the
144 * modifiable bits from the guest value.
146 guestval
= hostval
& ~x86_spec_ctrl_mask
;
147 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
149 /* SSBD controlled in MSR_SPEC_CTRL */
150 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
151 static_cpu_has(X86_FEATURE_AMD_SSBD
))
152 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
154 /* Conditional STIBP enabled? */
155 if (static_branch_unlikely(&switch_to_cond_stibp
))
156 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
158 if (hostval
!= guestval
) {
159 msrval
= setguest
? guestval
: hostval
;
160 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
165 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
166 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
168 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
169 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
173 * If the host has SSBD mitigation enabled, force it in the host's
174 * virtual MSR value. If its not permanently enabled, evaluate
175 * current's TIF_SSBD thread flag.
177 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
178 hostval
= SPEC_CTRL_SSBD
;
180 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
182 /* Sanitize the guest value */
183 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
185 if (hostval
!= guestval
) {
188 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
189 ssbd_spec_ctrl_to_tif(hostval
);
191 speculation_ctrl_update(tif
);
194 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
196 static void x86_amd_ssb_disable(void)
198 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
200 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
201 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
202 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
203 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
207 #define pr_fmt(fmt) "Spectre V2 : " fmt
209 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
212 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init
=
213 SPECTRE_V2_USER_NONE
;
215 #ifdef CONFIG_RETPOLINE
216 static bool spectre_v2_bad_module
;
218 bool retpoline_module_ok(bool has_retpoline
)
220 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
223 pr_err("System may be vulnerable to spectre v2\n");
224 spectre_v2_bad_module
= true;
228 static inline const char *spectre_v2_module_string(void)
230 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
233 static inline const char *spectre_v2_module_string(void) { return ""; }
236 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
238 int len
= strlen(opt
);
240 return len
== arglen
&& !strncmp(arg
, opt
, len
);
243 /* The kernel command line selection for spectre v2 */
244 enum spectre_v2_mitigation_cmd
{
247 SPECTRE_V2_CMD_FORCE
,
248 SPECTRE_V2_CMD_RETPOLINE
,
249 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
250 SPECTRE_V2_CMD_RETPOLINE_AMD
,
253 enum spectre_v2_user_cmd
{
254 SPECTRE_V2_USER_CMD_NONE
,
255 SPECTRE_V2_USER_CMD_AUTO
,
256 SPECTRE_V2_USER_CMD_FORCE
,
257 SPECTRE_V2_USER_CMD_PRCTL
,
258 SPECTRE_V2_USER_CMD_PRCTL_IBPB
,
259 SPECTRE_V2_USER_CMD_SECCOMP
,
260 SPECTRE_V2_USER_CMD_SECCOMP_IBPB
,
263 static const char * const spectre_v2_user_strings
[] = {
264 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
265 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
266 [SPECTRE_V2_USER_STRICT_PREFERRED
] = "User space: Mitigation: STIBP always-on protection",
267 [SPECTRE_V2_USER_PRCTL
] = "User space: Mitigation: STIBP via prctl",
268 [SPECTRE_V2_USER_SECCOMP
] = "User space: Mitigation: STIBP via seccomp and prctl",
271 static const struct {
273 enum spectre_v2_user_cmd cmd
;
275 } v2_user_options
[] __initdata
= {
276 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
277 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
278 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
279 { "prctl", SPECTRE_V2_USER_CMD_PRCTL
, false },
280 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB
, false },
281 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP
, false },
282 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB
, false },
285 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
287 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
288 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
291 static enum spectre_v2_user_cmd __init
292 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
298 case SPECTRE_V2_CMD_NONE
:
299 return SPECTRE_V2_USER_CMD_NONE
;
300 case SPECTRE_V2_CMD_FORCE
:
301 return SPECTRE_V2_USER_CMD_FORCE
;
306 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
309 return SPECTRE_V2_USER_CMD_AUTO
;
311 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
312 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
313 spec_v2_user_print_cond(v2_user_options
[i
].option
,
314 v2_user_options
[i
].secure
);
315 return v2_user_options
[i
].cmd
;
319 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
320 return SPECTRE_V2_USER_CMD_AUTO
;
324 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
326 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
327 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
328 enum spectre_v2_user_cmd cmd
;
330 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
333 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
334 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
335 smt_possible
= false;
337 cmd
= spectre_v2_parse_user_cmdline(v2_cmd
);
339 case SPECTRE_V2_USER_CMD_NONE
:
341 case SPECTRE_V2_USER_CMD_FORCE
:
342 mode
= SPECTRE_V2_USER_STRICT
;
344 case SPECTRE_V2_USER_CMD_PRCTL
:
345 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
346 mode
= SPECTRE_V2_USER_PRCTL
;
348 case SPECTRE_V2_USER_CMD_AUTO
:
349 case SPECTRE_V2_USER_CMD_SECCOMP
:
350 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
351 if (IS_ENABLED(CONFIG_SECCOMP
))
352 mode
= SPECTRE_V2_USER_SECCOMP
;
354 mode
= SPECTRE_V2_USER_PRCTL
;
359 * At this point, an STIBP mode other than "off" has been set.
360 * If STIBP support is not being forced, check if STIBP always-on
363 if (mode
!= SPECTRE_V2_USER_STRICT
&&
364 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON
))
365 mode
= SPECTRE_V2_USER_STRICT_PREFERRED
;
367 /* Initialize Indirect Branch Prediction Barrier */
368 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
369 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
372 case SPECTRE_V2_USER_CMD_FORCE
:
373 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
374 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
375 static_branch_enable(&switch_mm_always_ibpb
);
377 case SPECTRE_V2_USER_CMD_PRCTL
:
378 case SPECTRE_V2_USER_CMD_AUTO
:
379 case SPECTRE_V2_USER_CMD_SECCOMP
:
380 static_branch_enable(&switch_mm_cond_ibpb
);
386 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
387 static_key_enabled(&switch_mm_always_ibpb
) ?
388 "always-on" : "conditional");
391 /* If enhanced IBRS is enabled no STIBP required */
392 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
396 * If SMT is not possible or STIBP is not available clear the STIBP
399 if (!smt_possible
|| !boot_cpu_has(X86_FEATURE_STIBP
))
400 mode
= SPECTRE_V2_USER_NONE
;
402 spectre_v2_user
= mode
;
403 /* Only print the STIBP mode when SMT possible */
405 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
408 static const char * const spectre_v2_strings
[] = {
409 [SPECTRE_V2_NONE
] = "Vulnerable",
410 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
411 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
412 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
415 static const struct {
417 enum spectre_v2_mitigation_cmd cmd
;
419 } mitigation_options
[] __initdata
= {
420 { "off", SPECTRE_V2_CMD_NONE
, false },
421 { "on", SPECTRE_V2_CMD_FORCE
, true },
422 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
423 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
424 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
425 { "auto", SPECTRE_V2_CMD_AUTO
, false },
428 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
430 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
431 pr_info("%s selected on command line.\n", reason
);
434 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
436 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
440 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
441 return SPECTRE_V2_CMD_NONE
;
443 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
445 return SPECTRE_V2_CMD_AUTO
;
447 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
448 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
450 cmd
= mitigation_options
[i
].cmd
;
454 if (i
>= ARRAY_SIZE(mitigation_options
)) {
455 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
456 return SPECTRE_V2_CMD_AUTO
;
459 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
460 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
461 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
462 !IS_ENABLED(CONFIG_RETPOLINE
)) {
463 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
464 return SPECTRE_V2_CMD_AUTO
;
467 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
468 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
469 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
470 return SPECTRE_V2_CMD_AUTO
;
473 spec_v2_print_cond(mitigation_options
[i
].option
,
474 mitigation_options
[i
].secure
);
478 static void __init
spectre_v2_select_mitigation(void)
480 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
481 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
484 * If the CPU is not affected and the command line mode is NONE or AUTO
485 * then nothing to do.
487 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
488 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
492 case SPECTRE_V2_CMD_NONE
:
495 case SPECTRE_V2_CMD_FORCE
:
496 case SPECTRE_V2_CMD_AUTO
:
497 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
498 mode
= SPECTRE_V2_IBRS_ENHANCED
;
499 /* Force it so VMEXIT will restore correctly */
500 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
501 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
502 goto specv2_set_mode
;
504 if (IS_ENABLED(CONFIG_RETPOLINE
))
507 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
508 if (IS_ENABLED(CONFIG_RETPOLINE
))
511 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
512 if (IS_ENABLED(CONFIG_RETPOLINE
))
513 goto retpoline_generic
;
515 case SPECTRE_V2_CMD_RETPOLINE
:
516 if (IS_ENABLED(CONFIG_RETPOLINE
))
520 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
524 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
526 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
527 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
528 goto retpoline_generic
;
530 mode
= SPECTRE_V2_RETPOLINE_AMD
;
531 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
532 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
535 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
536 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
540 spectre_v2_enabled
= mode
;
541 pr_info("%s\n", spectre_v2_strings
[mode
]);
544 * If spectre v2 protection has been enabled, unconditionally fill
545 * RSB during a context switch; this protects against two independent
548 * - RSB underflow (and switch to BTB) on Skylake+
549 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
551 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
552 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
555 * Retpoline means the kernel is safe because it has no indirect
556 * branches. Enhanced IBRS protects firmware too, so, enable restricted
557 * speculation around firmware calls only when Enhanced IBRS isn't
560 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
561 * the user might select retpoline on the kernel command line and if
562 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
563 * enable IBRS around firmware calls.
565 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
566 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
567 pr_info("Enabling Restricted Speculation for firmware calls\n");
570 /* Set up IBPB and STIBP depending on the general spectre V2 command */
571 spectre_v2_user_select_mitigation(cmd
);
573 /* Enable STIBP if appropriate */
577 static void update_stibp_msr(void * __unused
)
579 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
582 /* Update x86_spec_ctrl_base in case SMT state changed. */
583 static void update_stibp_strict(void)
585 u64 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
587 if (sched_smt_active())
588 mask
|= SPEC_CTRL_STIBP
;
590 if (mask
== x86_spec_ctrl_base
)
593 pr_info("Update user space SMT mitigation: STIBP %s\n",
594 mask
& SPEC_CTRL_STIBP
? "always-on" : "off");
595 x86_spec_ctrl_base
= mask
;
596 on_each_cpu(update_stibp_msr
, NULL
, 1);
599 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
600 static void update_indir_branch_cond(void)
602 if (sched_smt_active())
603 static_branch_enable(&switch_to_cond_stibp
);
605 static_branch_disable(&switch_to_cond_stibp
);
608 void arch_smt_update(void)
610 /* Enhanced IBRS implies STIBP. No update required. */
611 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
614 mutex_lock(&spec_ctrl_mutex
);
616 switch (spectre_v2_user
) {
617 case SPECTRE_V2_USER_NONE
:
619 case SPECTRE_V2_USER_STRICT
:
620 case SPECTRE_V2_USER_STRICT_PREFERRED
:
621 update_stibp_strict();
623 case SPECTRE_V2_USER_PRCTL
:
624 case SPECTRE_V2_USER_SECCOMP
:
625 update_indir_branch_cond();
629 mutex_unlock(&spec_ctrl_mutex
);
633 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
635 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
637 /* The kernel command line selection */
638 enum ssb_mitigation_cmd
{
639 SPEC_STORE_BYPASS_CMD_NONE
,
640 SPEC_STORE_BYPASS_CMD_AUTO
,
641 SPEC_STORE_BYPASS_CMD_ON
,
642 SPEC_STORE_BYPASS_CMD_PRCTL
,
643 SPEC_STORE_BYPASS_CMD_SECCOMP
,
646 static const char * const ssb_strings
[] = {
647 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
648 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
649 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
650 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
653 static const struct {
655 enum ssb_mitigation_cmd cmd
;
656 } ssb_mitigation_options
[] __initdata
= {
657 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
658 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
659 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
660 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
661 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
664 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
666 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
670 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
671 return SPEC_STORE_BYPASS_CMD_NONE
;
673 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
676 return SPEC_STORE_BYPASS_CMD_AUTO
;
678 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
679 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
682 cmd
= ssb_mitigation_options
[i
].cmd
;
686 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
687 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
688 return SPEC_STORE_BYPASS_CMD_AUTO
;
695 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
697 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
698 enum ssb_mitigation_cmd cmd
;
700 if (!boot_cpu_has(X86_FEATURE_SSBD
))
703 cmd
= ssb_parse_cmdline();
704 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
705 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
706 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
710 case SPEC_STORE_BYPASS_CMD_AUTO
:
711 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
713 * Choose prctl+seccomp as the default mode if seccomp is
716 if (IS_ENABLED(CONFIG_SECCOMP
))
717 mode
= SPEC_STORE_BYPASS_SECCOMP
;
719 mode
= SPEC_STORE_BYPASS_PRCTL
;
721 case SPEC_STORE_BYPASS_CMD_ON
:
722 mode
= SPEC_STORE_BYPASS_DISABLE
;
724 case SPEC_STORE_BYPASS_CMD_PRCTL
:
725 mode
= SPEC_STORE_BYPASS_PRCTL
;
727 case SPEC_STORE_BYPASS_CMD_NONE
:
732 * We have three CPU feature flags that are in play here:
733 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
734 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
735 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
737 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
738 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
740 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
741 * use a completely different MSR and bit dependent on family.
743 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
744 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
745 x86_amd_ssb_disable();
747 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
748 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
749 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
756 static void ssb_select_mitigation(void)
758 ssb_mode
= __ssb_select_mitigation();
760 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
761 pr_info("%s\n", ssb_strings
[ssb_mode
]);
765 #define pr_fmt(fmt) "Speculation prctl: " fmt
767 static void task_update_spec_tif(struct task_struct
*tsk
)
769 /* Force the update of the real TIF bits */
770 set_tsk_thread_flag(tsk
, TIF_SPEC_FORCE_UPDATE
);
773 * Immediately update the speculation control MSRs for the current
774 * task, but for a non-current task delay setting the CPU
775 * mitigation until it is scheduled next.
777 * This can only happen for SECCOMP mitigation. For PRCTL it's
778 * always the current task.
781 speculation_ctrl_update_current();
784 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
786 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
787 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
792 /* If speculation is force disabled, enable is not allowed */
793 if (task_spec_ssb_force_disable(task
))
795 task_clear_spec_ssb_disable(task
);
796 task_update_spec_tif(task
);
798 case PR_SPEC_DISABLE
:
799 task_set_spec_ssb_disable(task
);
800 task_update_spec_tif(task
);
802 case PR_SPEC_FORCE_DISABLE
:
803 task_set_spec_ssb_disable(task
);
804 task_set_spec_ssb_force_disable(task
);
805 task_update_spec_tif(task
);
813 static int ib_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
817 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
820 * Indirect branch speculation is always disabled in strict
823 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
824 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
826 task_clear_spec_ib_disable(task
);
827 task_update_spec_tif(task
);
829 case PR_SPEC_DISABLE
:
830 case PR_SPEC_FORCE_DISABLE
:
832 * Indirect branch speculation is always allowed when
833 * mitigation is force disabled.
835 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
837 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
838 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
840 task_set_spec_ib_disable(task
);
841 if (ctrl
== PR_SPEC_FORCE_DISABLE
)
842 task_set_spec_ib_force_disable(task
);
843 task_update_spec_tif(task
);
851 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
855 case PR_SPEC_STORE_BYPASS
:
856 return ssb_prctl_set(task
, ctrl
);
857 case PR_SPEC_INDIRECT_BRANCH
:
858 return ib_prctl_set(task
, ctrl
);
864 #ifdef CONFIG_SECCOMP
865 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
867 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
868 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
869 if (spectre_v2_user
== SPECTRE_V2_USER_SECCOMP
)
870 ib_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
874 static int ssb_prctl_get(struct task_struct
*task
)
877 case SPEC_STORE_BYPASS_DISABLE
:
878 return PR_SPEC_DISABLE
;
879 case SPEC_STORE_BYPASS_SECCOMP
:
880 case SPEC_STORE_BYPASS_PRCTL
:
881 if (task_spec_ssb_force_disable(task
))
882 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
883 if (task_spec_ssb_disable(task
))
884 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
885 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
887 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
888 return PR_SPEC_ENABLE
;
889 return PR_SPEC_NOT_AFFECTED
;
893 static int ib_prctl_get(struct task_struct
*task
)
895 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
896 return PR_SPEC_NOT_AFFECTED
;
898 switch (spectre_v2_user
) {
899 case SPECTRE_V2_USER_NONE
:
900 return PR_SPEC_ENABLE
;
901 case SPECTRE_V2_USER_PRCTL
:
902 case SPECTRE_V2_USER_SECCOMP
:
903 if (task_spec_ib_force_disable(task
))
904 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
905 if (task_spec_ib_disable(task
))
906 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
907 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
908 case SPECTRE_V2_USER_STRICT
:
909 case SPECTRE_V2_USER_STRICT_PREFERRED
:
910 return PR_SPEC_DISABLE
;
912 return PR_SPEC_NOT_AFFECTED
;
916 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
919 case PR_SPEC_STORE_BYPASS
:
920 return ssb_prctl_get(task
);
921 case PR_SPEC_INDIRECT_BRANCH
:
922 return ib_prctl_get(task
);
928 void x86_spec_ctrl_setup_ap(void)
930 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
931 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
933 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
934 x86_amd_ssb_disable();
938 #define pr_fmt(fmt) "L1TF: " fmt
940 /* Default mitigation for L1TF-affected CPUs */
941 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
942 #if IS_ENABLED(CONFIG_KVM_INTEL)
943 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
945 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
946 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
950 * These CPUs all support 44bits physical address space internally in the
951 * cache but CPUID can report a smaller number of physical address bits.
953 * The L1TF mitigation uses the top most address bit for the inversion of
954 * non present PTEs. When the installed memory reaches into the top most
955 * address bit due to memory holes, which has been observed on machines
956 * which report 36bits physical address bits and have 32G RAM installed,
957 * then the mitigation range check in l1tf_select_mitigation() triggers.
958 * This is a false positive because the mitigation is still possible due to
959 * the fact that the cache uses 44bit internally. Use the cache bits
960 * instead of the reported physical bits and adjust them on the affected
961 * machines to 44bit if the reported bits are less than 44.
963 static void override_cache_bits(struct cpuinfo_x86
*c
)
968 switch (c
->x86_model
) {
969 case INTEL_FAM6_NEHALEM
:
970 case INTEL_FAM6_WESTMERE
:
971 case INTEL_FAM6_SANDYBRIDGE
:
972 case INTEL_FAM6_IVYBRIDGE
:
973 case INTEL_FAM6_HASWELL_CORE
:
974 case INTEL_FAM6_HASWELL_ULT
:
975 case INTEL_FAM6_HASWELL_GT3E
:
976 case INTEL_FAM6_BROADWELL_CORE
:
977 case INTEL_FAM6_BROADWELL_GT3E
:
978 case INTEL_FAM6_SKYLAKE_MOBILE
:
979 case INTEL_FAM6_SKYLAKE_DESKTOP
:
980 case INTEL_FAM6_KABYLAKE_MOBILE
:
981 case INTEL_FAM6_KABYLAKE_DESKTOP
:
982 if (c
->x86_cache_bits
< 44)
983 c
->x86_cache_bits
= 44;
988 static void __init
l1tf_select_mitigation(void)
992 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
995 override_cache_bits(&boot_cpu_data
);
997 switch (l1tf_mitigation
) {
998 case L1TF_MITIGATION_OFF
:
999 case L1TF_MITIGATION_FLUSH_NOWARN
:
1000 case L1TF_MITIGATION_FLUSH
:
1002 case L1TF_MITIGATION_FLUSH_NOSMT
:
1003 case L1TF_MITIGATION_FULL
:
1004 cpu_smt_disable(false);
1006 case L1TF_MITIGATION_FULL_FORCE
:
1007 cpu_smt_disable(true);
1011 #if CONFIG_PGTABLE_LEVELS == 2
1012 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1016 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
1017 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
1018 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1019 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1021 pr_info("However, doing so will make a part of your RAM unusable.\n");
1022 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
1026 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
1029 static int __init
l1tf_cmdline(char *str
)
1031 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1037 if (!strcmp(str
, "off"))
1038 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1039 else if (!strcmp(str
, "flush,nowarn"))
1040 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
1041 else if (!strcmp(str
, "flush"))
1042 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
1043 else if (!strcmp(str
, "flush,nosmt"))
1044 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1045 else if (!strcmp(str
, "full"))
1046 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
1047 else if (!strcmp(str
, "full,force"))
1048 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
1052 early_param("l1tf", l1tf_cmdline
);
1058 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1060 #if IS_ENABLED(CONFIG_KVM_INTEL)
1061 static const char * const l1tf_vmx_states
[] = {
1062 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
1063 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
1064 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
1065 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
1066 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
1067 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
1070 static ssize_t
l1tf_show_state(char *buf
)
1072 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
1073 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1075 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
1076 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
1077 sched_smt_active())) {
1078 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
1079 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
1082 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
1083 l1tf_vmx_states
[l1tf_vmx_mitigation
],
1084 sched_smt_active() ? "vulnerable" : "disabled");
1087 static ssize_t
l1tf_show_state(char *buf
)
1089 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1093 static char *stibp_state(void)
1095 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
1098 switch (spectre_v2_user
) {
1099 case SPECTRE_V2_USER_NONE
:
1100 return ", STIBP: disabled";
1101 case SPECTRE_V2_USER_STRICT
:
1102 return ", STIBP: forced";
1103 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1104 return ", STIBP: always-on";
1105 case SPECTRE_V2_USER_PRCTL
:
1106 case SPECTRE_V2_USER_SECCOMP
:
1107 if (static_key_enabled(&switch_to_cond_stibp
))
1108 return ", STIBP: conditional";
1113 static char *ibpb_state(void)
1115 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
1116 if (static_key_enabled(&switch_mm_always_ibpb
))
1117 return ", IBPB: always-on";
1118 if (static_key_enabled(&switch_mm_cond_ibpb
))
1119 return ", IBPB: conditional";
1120 return ", IBPB: disabled";
1125 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
1126 char *buf
, unsigned int bug
)
1128 if (!boot_cpu_has_bug(bug
))
1129 return sprintf(buf
, "Not affected\n");
1132 case X86_BUG_CPU_MELTDOWN
:
1133 if (boot_cpu_has(X86_FEATURE_PTI
))
1134 return sprintf(buf
, "Mitigation: PTI\n");
1138 case X86_BUG_SPECTRE_V1
:
1139 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
1141 case X86_BUG_SPECTRE_V2
:
1142 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
1144 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
1146 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
1147 spectre_v2_module_string());
1149 case X86_BUG_SPEC_STORE_BYPASS
:
1150 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
1153 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
1154 return l1tf_show_state(buf
);
1160 return sprintf(buf
, "Vulnerable\n");
1163 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1165 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1168 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1170 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
1173 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1175 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
1178 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1180 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
1183 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1185 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);