1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
34 static void __init
spectre_v2_select_mitigation(void);
35 static void __init
ssb_select_mitigation(void);
36 static void __init
l1tf_select_mitigation(void);
38 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
39 u64 x86_spec_ctrl_base
;
40 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
41 static DEFINE_MUTEX(spec_ctrl_mutex
);
44 * The vendor and possibly platform specific bits which can be modified in
47 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
50 * AMD specific MSR info for Speculative Store Bypass control.
51 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
53 u64 __ro_after_init x86_amd_ls_cfg_base
;
54 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
56 void __init
check_bugs(void)
61 * identify_boot_cpu() initialized SMT support information, let the
64 cpu_smt_check_topology_early();
66 if (!IS_ENABLED(CONFIG_SMP
)) {
68 print_cpu_info(&boot_cpu_data
);
72 * Read the SPEC_CTRL MSR to account for reserved bits which may
73 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
74 * init code as it is not enumerated and depends on the family.
76 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
77 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
79 /* Allow STIBP in MSR_SPEC_CTRL if supported */
80 if (boot_cpu_has(X86_FEATURE_STIBP
))
81 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
83 /* Select the proper spectre mitigation before patching alternatives */
84 spectre_v2_select_mitigation();
87 * Select proper mitigation for any exposure to the Speculative Store
88 * Bypass vulnerability.
90 ssb_select_mitigation();
92 l1tf_select_mitigation();
96 * Check whether we are able to run this kernel safely on SMP.
98 * - i386 is no longer supported.
99 * - In order to run on anything without a TSC, we need to be
100 * compiled for a i486.
102 if (boot_cpu_data
.x86
< 4)
103 panic("Kernel requires i486+ for 'invlpg' and other features");
105 init_utsname()->machine
[1] =
106 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
107 alternative_instructions();
109 fpu__init_check_bugs();
110 #else /* CONFIG_X86_64 */
111 alternative_instructions();
114 * Make sure the first 2MB area is not mapped by huge pages
115 * There are typically fixed size MTRRs in there and overlapping
116 * MTRRs into large pages causes slow downs.
118 * Right now we don't do that with gbpages because there seems
119 * very little benefit for that case.
122 set_memory_4k((unsigned long)__va(0), 1);
127 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
129 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
130 struct thread_info
*ti
= current_thread_info();
132 /* Is MSR_SPEC_CTRL implemented ? */
133 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
135 * Restrict guest_spec_ctrl to supported values. Clear the
136 * modifiable bits in the host base value and or the
137 * modifiable bits from the guest value.
139 guestval
= hostval
& ~x86_spec_ctrl_mask
;
140 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
142 /* SSBD controlled in MSR_SPEC_CTRL */
143 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
144 static_cpu_has(X86_FEATURE_AMD_SSBD
))
145 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
147 if (hostval
!= guestval
) {
148 msrval
= setguest
? guestval
: hostval
;
149 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
154 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
155 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
157 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
158 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
162 * If the host has SSBD mitigation enabled, force it in the host's
163 * virtual MSR value. If its not permanently enabled, evaluate
164 * current's TIF_SSBD thread flag.
166 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
167 hostval
= SPEC_CTRL_SSBD
;
169 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
171 /* Sanitize the guest value */
172 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
174 if (hostval
!= guestval
) {
177 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
178 ssbd_spec_ctrl_to_tif(hostval
);
180 speculation_ctrl_update(tif
);
183 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
185 static void x86_amd_ssb_disable(void)
187 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
189 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
190 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
191 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
192 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
196 #define pr_fmt(fmt) "Spectre V2 : " fmt
198 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
202 static bool spectre_v2_bad_module
;
204 bool retpoline_module_ok(bool has_retpoline
)
206 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
209 pr_err("System may be vulnerable to spectre v2\n");
210 spectre_v2_bad_module
= true;
214 static inline const char *spectre_v2_module_string(void)
216 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
219 static inline const char *spectre_v2_module_string(void) { return ""; }
222 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
224 int len
= strlen(opt
);
226 return len
== arglen
&& !strncmp(arg
, opt
, len
);
229 /* The kernel command line selection for spectre v2 */
230 enum spectre_v2_mitigation_cmd
{
233 SPECTRE_V2_CMD_FORCE
,
234 SPECTRE_V2_CMD_RETPOLINE
,
235 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
236 SPECTRE_V2_CMD_RETPOLINE_AMD
,
239 static const char * const spectre_v2_strings
[] = {
240 [SPECTRE_V2_NONE
] = "Vulnerable",
241 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
242 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
243 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
246 static const struct {
248 enum spectre_v2_mitigation_cmd cmd
;
250 } mitigation_options
[] __initdata
= {
251 { "off", SPECTRE_V2_CMD_NONE
, false },
252 { "on", SPECTRE_V2_CMD_FORCE
, true },
253 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
254 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
255 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
256 { "auto", SPECTRE_V2_CMD_AUTO
, false },
259 static void __init
spec2_print_if_insecure(const char *reason
)
261 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
262 pr_info("%s selected on command line.\n", reason
);
265 static void __init
spec2_print_if_secure(const char *reason
)
267 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
268 pr_info("%s selected on command line.\n", reason
);
271 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
273 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
277 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
278 return SPECTRE_V2_CMD_NONE
;
280 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
282 return SPECTRE_V2_CMD_AUTO
;
284 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
285 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
287 cmd
= mitigation_options
[i
].cmd
;
291 if (i
>= ARRAY_SIZE(mitigation_options
)) {
292 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
293 return SPECTRE_V2_CMD_AUTO
;
296 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
297 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
298 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
299 !IS_ENABLED(CONFIG_RETPOLINE
)) {
300 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
301 return SPECTRE_V2_CMD_AUTO
;
304 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
305 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
306 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
307 return SPECTRE_V2_CMD_AUTO
;
310 if (mitigation_options
[i
].secure
)
311 spec2_print_if_secure(mitigation_options
[i
].option
);
313 spec2_print_if_insecure(mitigation_options
[i
].option
);
318 static void __init
spectre_v2_select_mitigation(void)
320 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
321 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
324 * If the CPU is not affected and the command line mode is NONE or AUTO
325 * then nothing to do.
327 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
328 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
332 case SPECTRE_V2_CMD_NONE
:
335 case SPECTRE_V2_CMD_FORCE
:
336 case SPECTRE_V2_CMD_AUTO
:
337 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
338 mode
= SPECTRE_V2_IBRS_ENHANCED
;
339 /* Force it so VMEXIT will restore correctly */
340 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
341 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
342 goto specv2_set_mode
;
344 if (IS_ENABLED(CONFIG_RETPOLINE
))
347 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
348 if (IS_ENABLED(CONFIG_RETPOLINE
))
351 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
352 if (IS_ENABLED(CONFIG_RETPOLINE
))
353 goto retpoline_generic
;
355 case SPECTRE_V2_CMD_RETPOLINE
:
356 if (IS_ENABLED(CONFIG_RETPOLINE
))
360 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
364 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
366 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
367 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
368 goto retpoline_generic
;
370 mode
= SPECTRE_V2_RETPOLINE_AMD
;
371 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
372 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
375 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
376 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
380 spectre_v2_enabled
= mode
;
381 pr_info("%s\n", spectre_v2_strings
[mode
]);
384 * If spectre v2 protection has been enabled, unconditionally fill
385 * RSB during a context switch; this protects against two independent
388 * - RSB underflow (and switch to BTB) on Skylake+
389 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
391 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
392 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
394 /* Initialize Indirect Branch Prediction Barrier if supported */
395 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
396 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
397 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
401 * Retpoline means the kernel is safe because it has no indirect
402 * branches. Enhanced IBRS protects firmware too, so, enable restricted
403 * speculation around firmware calls only when Enhanced IBRS isn't
406 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
407 * the user might select retpoline on the kernel command line and if
408 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
409 * enable IBRS around firmware calls.
411 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
412 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
413 pr_info("Enabling Restricted Speculation for firmware calls\n");
416 /* Enable STIBP if appropriate */
420 static bool stibp_needed(void)
422 if (spectre_v2_enabled
== SPECTRE_V2_NONE
)
425 /* Enhanced IBRS makes using STIBP unnecessary. */
426 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
429 if (!boot_cpu_has(X86_FEATURE_STIBP
))
435 static void update_stibp_msr(void *info
)
437 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
440 void arch_smt_update(void)
447 mutex_lock(&spec_ctrl_mutex
);
449 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
450 if (sched_smt_active())
451 mask
|= SPEC_CTRL_STIBP
;
453 if (mask
!= x86_spec_ctrl_base
) {
454 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
455 mask
& SPEC_CTRL_STIBP
? "Enabling" : "Disabling");
456 x86_spec_ctrl_base
= mask
;
457 on_each_cpu(update_stibp_msr
, NULL
, 1);
459 mutex_unlock(&spec_ctrl_mutex
);
463 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
465 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
467 /* The kernel command line selection */
468 enum ssb_mitigation_cmd
{
469 SPEC_STORE_BYPASS_CMD_NONE
,
470 SPEC_STORE_BYPASS_CMD_AUTO
,
471 SPEC_STORE_BYPASS_CMD_ON
,
472 SPEC_STORE_BYPASS_CMD_PRCTL
,
473 SPEC_STORE_BYPASS_CMD_SECCOMP
,
476 static const char * const ssb_strings
[] = {
477 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
478 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
479 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
480 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
483 static const struct {
485 enum ssb_mitigation_cmd cmd
;
486 } ssb_mitigation_options
[] __initdata
= {
487 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
488 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
489 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
490 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
491 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
494 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
496 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
500 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
501 return SPEC_STORE_BYPASS_CMD_NONE
;
503 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
506 return SPEC_STORE_BYPASS_CMD_AUTO
;
508 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
509 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
512 cmd
= ssb_mitigation_options
[i
].cmd
;
516 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
517 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
518 return SPEC_STORE_BYPASS_CMD_AUTO
;
525 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
527 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
528 enum ssb_mitigation_cmd cmd
;
530 if (!boot_cpu_has(X86_FEATURE_SSBD
))
533 cmd
= ssb_parse_cmdline();
534 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
535 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
536 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
540 case SPEC_STORE_BYPASS_CMD_AUTO
:
541 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
543 * Choose prctl+seccomp as the default mode if seccomp is
546 if (IS_ENABLED(CONFIG_SECCOMP
))
547 mode
= SPEC_STORE_BYPASS_SECCOMP
;
549 mode
= SPEC_STORE_BYPASS_PRCTL
;
551 case SPEC_STORE_BYPASS_CMD_ON
:
552 mode
= SPEC_STORE_BYPASS_DISABLE
;
554 case SPEC_STORE_BYPASS_CMD_PRCTL
:
555 mode
= SPEC_STORE_BYPASS_PRCTL
;
557 case SPEC_STORE_BYPASS_CMD_NONE
:
562 * We have three CPU feature flags that are in play here:
563 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
564 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
565 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
567 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
568 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
570 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
571 * use a completely different MSR and bit dependent on family.
573 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
574 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
575 x86_amd_ssb_disable();
577 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
578 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
579 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
586 static void ssb_select_mitigation(void)
588 ssb_mode
= __ssb_select_mitigation();
590 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
591 pr_info("%s\n", ssb_strings
[ssb_mode
]);
595 #define pr_fmt(fmt) "Speculation prctl: " fmt
597 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
601 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
602 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
607 /* If speculation is force disabled, enable is not allowed */
608 if (task_spec_ssb_force_disable(task
))
610 task_clear_spec_ssb_disable(task
);
611 update
= test_and_clear_tsk_thread_flag(task
, TIF_SSBD
);
613 case PR_SPEC_DISABLE
:
614 task_set_spec_ssb_disable(task
);
615 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
617 case PR_SPEC_FORCE_DISABLE
:
618 task_set_spec_ssb_disable(task
);
619 task_set_spec_ssb_force_disable(task
);
620 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
627 * If being set on non-current task, delay setting the CPU
628 * mitigation until it is next scheduled.
630 if (task
== current
&& update
)
631 speculation_ctrl_update_current();
636 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
640 case PR_SPEC_STORE_BYPASS
:
641 return ssb_prctl_set(task
, ctrl
);
647 #ifdef CONFIG_SECCOMP
648 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
650 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
651 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
655 static int ssb_prctl_get(struct task_struct
*task
)
658 case SPEC_STORE_BYPASS_DISABLE
:
659 return PR_SPEC_DISABLE
;
660 case SPEC_STORE_BYPASS_SECCOMP
:
661 case SPEC_STORE_BYPASS_PRCTL
:
662 if (task_spec_ssb_force_disable(task
))
663 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
664 if (task_spec_ssb_disable(task
))
665 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
666 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
668 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
669 return PR_SPEC_ENABLE
;
670 return PR_SPEC_NOT_AFFECTED
;
674 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
677 case PR_SPEC_STORE_BYPASS
:
678 return ssb_prctl_get(task
);
684 void x86_spec_ctrl_setup_ap(void)
686 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
687 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
689 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
690 x86_amd_ssb_disable();
694 #define pr_fmt(fmt) "L1TF: " fmt
696 /* Default mitigation for L1TF-affected CPUs */
697 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
698 #if IS_ENABLED(CONFIG_KVM_INTEL)
699 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
701 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
702 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
706 * These CPUs all support 44bits physical address space internally in the
707 * cache but CPUID can report a smaller number of physical address bits.
709 * The L1TF mitigation uses the top most address bit for the inversion of
710 * non present PTEs. When the installed memory reaches into the top most
711 * address bit due to memory holes, which has been observed on machines
712 * which report 36bits physical address bits and have 32G RAM installed,
713 * then the mitigation range check in l1tf_select_mitigation() triggers.
714 * This is a false positive because the mitigation is still possible due to
715 * the fact that the cache uses 44bit internally. Use the cache bits
716 * instead of the reported physical bits and adjust them on the affected
717 * machines to 44bit if the reported bits are less than 44.
719 static void override_cache_bits(struct cpuinfo_x86
*c
)
724 switch (c
->x86_model
) {
725 case INTEL_FAM6_NEHALEM
:
726 case INTEL_FAM6_WESTMERE
:
727 case INTEL_FAM6_SANDYBRIDGE
:
728 case INTEL_FAM6_IVYBRIDGE
:
729 case INTEL_FAM6_HASWELL_CORE
:
730 case INTEL_FAM6_HASWELL_ULT
:
731 case INTEL_FAM6_HASWELL_GT3E
:
732 case INTEL_FAM6_BROADWELL_CORE
:
733 case INTEL_FAM6_BROADWELL_GT3E
:
734 case INTEL_FAM6_SKYLAKE_MOBILE
:
735 case INTEL_FAM6_SKYLAKE_DESKTOP
:
736 case INTEL_FAM6_KABYLAKE_MOBILE
:
737 case INTEL_FAM6_KABYLAKE_DESKTOP
:
738 if (c
->x86_cache_bits
< 44)
739 c
->x86_cache_bits
= 44;
744 static void __init
l1tf_select_mitigation(void)
748 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
751 override_cache_bits(&boot_cpu_data
);
753 switch (l1tf_mitigation
) {
754 case L1TF_MITIGATION_OFF
:
755 case L1TF_MITIGATION_FLUSH_NOWARN
:
756 case L1TF_MITIGATION_FLUSH
:
758 case L1TF_MITIGATION_FLUSH_NOSMT
:
759 case L1TF_MITIGATION_FULL
:
760 cpu_smt_disable(false);
762 case L1TF_MITIGATION_FULL_FORCE
:
763 cpu_smt_disable(true);
767 #if CONFIG_PGTABLE_LEVELS == 2
768 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
772 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
773 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
774 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
778 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
781 static int __init
l1tf_cmdline(char *str
)
783 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
789 if (!strcmp(str
, "off"))
790 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
791 else if (!strcmp(str
, "flush,nowarn"))
792 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
793 else if (!strcmp(str
, "flush"))
794 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
795 else if (!strcmp(str
, "flush,nosmt"))
796 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
797 else if (!strcmp(str
, "full"))
798 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
799 else if (!strcmp(str
, "full,force"))
800 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
804 early_param("l1tf", l1tf_cmdline
);
810 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
812 #if IS_ENABLED(CONFIG_KVM_INTEL)
813 static const char * const l1tf_vmx_states
[] = {
814 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
815 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
816 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
817 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
818 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
819 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
822 static ssize_t
l1tf_show_state(char *buf
)
824 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
825 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
827 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
828 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
829 sched_smt_active())) {
830 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
831 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
834 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
835 l1tf_vmx_states
[l1tf_vmx_mitigation
],
836 sched_smt_active() ? "vulnerable" : "disabled");
839 static ssize_t
l1tf_show_state(char *buf
)
841 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
845 static char *stibp_state(void)
847 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
850 if (x86_spec_ctrl_base
& SPEC_CTRL_STIBP
)
856 static char *ibpb_state(void)
858 if (boot_cpu_has(X86_FEATURE_USE_IBPB
))
864 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
865 char *buf
, unsigned int bug
)
867 if (!boot_cpu_has_bug(bug
))
868 return sprintf(buf
, "Not affected\n");
871 case X86_BUG_CPU_MELTDOWN
:
872 if (boot_cpu_has(X86_FEATURE_PTI
))
873 return sprintf(buf
, "Mitigation: PTI\n");
877 case X86_BUG_SPECTRE_V1
:
878 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
880 case X86_BUG_SPECTRE_V2
:
881 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
883 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
885 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
886 spectre_v2_module_string());
888 case X86_BUG_SPEC_STORE_BYPASS
:
889 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
892 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
893 return l1tf_show_state(buf
);
899 return sprintf(buf
, "Vulnerable\n");
902 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
904 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
907 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
909 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
912 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
914 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
917 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
919 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
922 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
924 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);