1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
19 #include <linux/bpf.h>
21 #include <asm/spec-ctrl.h>
22 #include <asm/cmdline.h>
24 #include <asm/processor.h>
25 #include <asm/processor-flags.h>
26 #include <asm/fpu/api.h>
29 #include <asm/paravirt.h>
30 #include <asm/alternative.h>
31 #include <asm/set_memory.h>
32 #include <asm/intel-family.h>
33 #include <asm/e820/api.h>
34 #include <asm/hypervisor.h>
35 #include <asm/tlbflush.h>
39 static void __init
spectre_v1_select_mitigation(void);
40 static void __init
spectre_v2_select_mitigation(void);
41 static void __init
ssb_select_mitigation(void);
42 static void __init
l1tf_select_mitigation(void);
43 static void __init
mds_select_mitigation(void);
44 static void __init
md_clear_update_mitigation(void);
45 static void __init
taa_select_mitigation(void);
46 static void __init
mmio_select_mitigation(void);
47 static void __init
srbds_select_mitigation(void);
48 static void __init
l1d_flush_select_mitigation(void);
50 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
51 u64 x86_spec_ctrl_base
;
52 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
53 static DEFINE_MUTEX(spec_ctrl_mutex
);
56 * The vendor and possibly platform specific bits which can be modified in
59 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
62 * AMD specific MSR info for Speculative Store Bypass control.
63 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
65 u64 __ro_after_init x86_amd_ls_cfg_base
;
66 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
68 /* Control conditional STIBP in switch_to() */
69 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
70 /* Control conditional IBPB in switch_mm() */
71 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb
);
72 /* Control unconditional IBPB in switch_mm() */
73 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb
);
75 /* Control MDS CPU buffer clear before returning to user space */
76 DEFINE_STATIC_KEY_FALSE(mds_user_clear
);
77 EXPORT_SYMBOL_GPL(mds_user_clear
);
78 /* Control MDS CPU buffer clear before idling (halt, mwait) */
79 DEFINE_STATIC_KEY_FALSE(mds_idle_clear
);
80 EXPORT_SYMBOL_GPL(mds_idle_clear
);
83 * Controls whether l1d flush based mitigations are enabled,
84 * based on hw features and admin setting via boot parameter
87 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush
);
89 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
90 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear
);
91 EXPORT_SYMBOL_GPL(mmio_stale_data_clear
);
93 void __init
check_bugs(void)
98 * identify_boot_cpu() initialized SMT support information, let the
101 cpu_smt_check_topology();
103 if (!IS_ENABLED(CONFIG_SMP
)) {
105 print_cpu_info(&boot_cpu_data
);
109 * Read the SPEC_CTRL MSR to account for reserved bits which may
110 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
111 * init code as it is not enumerated and depends on the family.
113 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
114 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
116 /* Allow STIBP in MSR_SPEC_CTRL if supported */
117 if (boot_cpu_has(X86_FEATURE_STIBP
))
118 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
120 /* Select the proper CPU mitigations before patching alternatives: */
121 spectre_v1_select_mitigation();
122 spectre_v2_select_mitigation();
123 ssb_select_mitigation();
124 l1tf_select_mitigation();
125 mds_select_mitigation();
126 taa_select_mitigation();
127 mmio_select_mitigation();
128 srbds_select_mitigation();
129 l1d_flush_select_mitigation();
132 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
133 * and print their mitigation after MDS, TAA and MMIO Stale Data
134 * mitigation selection is done.
136 md_clear_update_mitigation();
142 * Check whether we are able to run this kernel safely on SMP.
144 * - i386 is no longer supported.
145 * - In order to run on anything without a TSC, we need to be
146 * compiled for a i486.
148 if (boot_cpu_data
.x86
< 4)
149 panic("Kernel requires i486+ for 'invlpg' and other features");
151 init_utsname()->machine
[1] =
152 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
153 alternative_instructions();
155 fpu__init_check_bugs();
156 #else /* CONFIG_X86_64 */
157 alternative_instructions();
160 * Make sure the first 2MB area is not mapped by huge pages
161 * There are typically fixed size MTRRs in there and overlapping
162 * MTRRs into large pages causes slow downs.
164 * Right now we don't do that with gbpages because there seems
165 * very little benefit for that case.
168 set_memory_4k((unsigned long)__va(0), 1);
173 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
175 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
176 struct thread_info
*ti
= current_thread_info();
178 /* Is MSR_SPEC_CTRL implemented ? */
179 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
181 * Restrict guest_spec_ctrl to supported values. Clear the
182 * modifiable bits in the host base value and or the
183 * modifiable bits from the guest value.
185 guestval
= hostval
& ~x86_spec_ctrl_mask
;
186 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
188 /* SSBD controlled in MSR_SPEC_CTRL */
189 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
190 static_cpu_has(X86_FEATURE_AMD_SSBD
))
191 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
193 /* Conditional STIBP enabled? */
194 if (static_branch_unlikely(&switch_to_cond_stibp
))
195 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
197 if (hostval
!= guestval
) {
198 msrval
= setguest
? guestval
: hostval
;
199 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
204 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
205 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
207 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
208 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
212 * If the host has SSBD mitigation enabled, force it in the host's
213 * virtual MSR value. If its not permanently enabled, evaluate
214 * current's TIF_SSBD thread flag.
216 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
217 hostval
= SPEC_CTRL_SSBD
;
219 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
221 /* Sanitize the guest value */
222 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
224 if (hostval
!= guestval
) {
227 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
228 ssbd_spec_ctrl_to_tif(hostval
);
230 speculation_ctrl_update(tif
);
233 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
235 static void x86_amd_ssb_disable(void)
237 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
239 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
240 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
241 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
242 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
246 #define pr_fmt(fmt) "MDS: " fmt
248 /* Default mitigation for MDS-affected CPUs */
249 static enum mds_mitigations mds_mitigation __ro_after_init
= MDS_MITIGATION_FULL
;
250 static bool mds_nosmt __ro_after_init
= false;
252 static const char * const mds_strings
[] = {
253 [MDS_MITIGATION_OFF
] = "Vulnerable",
254 [MDS_MITIGATION_FULL
] = "Mitigation: Clear CPU buffers",
255 [MDS_MITIGATION_VMWERV
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
258 static void __init
mds_select_mitigation(void)
260 if (!boot_cpu_has_bug(X86_BUG_MDS
) || cpu_mitigations_off()) {
261 mds_mitigation
= MDS_MITIGATION_OFF
;
265 if (mds_mitigation
== MDS_MITIGATION_FULL
) {
266 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR
))
267 mds_mitigation
= MDS_MITIGATION_VMWERV
;
269 static_branch_enable(&mds_user_clear
);
271 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY
) &&
272 (mds_nosmt
|| cpu_mitigations_auto_nosmt()))
273 cpu_smt_disable(false);
277 static int __init
mds_cmdline(char *str
)
279 if (!boot_cpu_has_bug(X86_BUG_MDS
))
285 if (!strcmp(str
, "off"))
286 mds_mitigation
= MDS_MITIGATION_OFF
;
287 else if (!strcmp(str
, "full"))
288 mds_mitigation
= MDS_MITIGATION_FULL
;
289 else if (!strcmp(str
, "full,nosmt")) {
290 mds_mitigation
= MDS_MITIGATION_FULL
;
296 early_param("mds", mds_cmdline
);
299 #define pr_fmt(fmt) "TAA: " fmt
301 enum taa_mitigations
{
303 TAA_MITIGATION_UCODE_NEEDED
,
305 TAA_MITIGATION_TSX_DISABLED
,
308 /* Default mitigation for TAA-affected CPUs */
309 static enum taa_mitigations taa_mitigation __ro_after_init
= TAA_MITIGATION_VERW
;
310 static bool taa_nosmt __ro_after_init
;
312 static const char * const taa_strings
[] = {
313 [TAA_MITIGATION_OFF
] = "Vulnerable",
314 [TAA_MITIGATION_UCODE_NEEDED
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
315 [TAA_MITIGATION_VERW
] = "Mitigation: Clear CPU buffers",
316 [TAA_MITIGATION_TSX_DISABLED
] = "Mitigation: TSX disabled",
319 static void __init
taa_select_mitigation(void)
323 if (!boot_cpu_has_bug(X86_BUG_TAA
)) {
324 taa_mitigation
= TAA_MITIGATION_OFF
;
328 /* TSX previously disabled by tsx=off */
329 if (!boot_cpu_has(X86_FEATURE_RTM
)) {
330 taa_mitigation
= TAA_MITIGATION_TSX_DISABLED
;
334 if (cpu_mitigations_off()) {
335 taa_mitigation
= TAA_MITIGATION_OFF
;
340 * TAA mitigation via VERW is turned off if both
341 * tsx_async_abort=off and mds=off are specified.
343 if (taa_mitigation
== TAA_MITIGATION_OFF
&&
344 mds_mitigation
== MDS_MITIGATION_OFF
)
347 if (boot_cpu_has(X86_FEATURE_MD_CLEAR
))
348 taa_mitigation
= TAA_MITIGATION_VERW
;
350 taa_mitigation
= TAA_MITIGATION_UCODE_NEEDED
;
353 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
354 * A microcode update fixes this behavior to clear CPU buffers. It also
355 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
356 * ARCH_CAP_TSX_CTRL_MSR bit.
358 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
359 * update is required.
361 ia32_cap
= x86_read_arch_cap_msr();
362 if ( (ia32_cap
& ARCH_CAP_MDS_NO
) &&
363 !(ia32_cap
& ARCH_CAP_TSX_CTRL_MSR
))
364 taa_mitigation
= TAA_MITIGATION_UCODE_NEEDED
;
367 * TSX is enabled, select alternate mitigation for TAA which is
368 * the same as MDS. Enable MDS static branch to clear CPU buffers.
370 * For guests that can't determine whether the correct microcode is
371 * present on host, enable the mitigation for UCODE_NEEDED as well.
373 static_branch_enable(&mds_user_clear
);
375 if (taa_nosmt
|| cpu_mitigations_auto_nosmt())
376 cpu_smt_disable(false);
379 static int __init
tsx_async_abort_parse_cmdline(char *str
)
381 if (!boot_cpu_has_bug(X86_BUG_TAA
))
387 if (!strcmp(str
, "off")) {
388 taa_mitigation
= TAA_MITIGATION_OFF
;
389 } else if (!strcmp(str
, "full")) {
390 taa_mitigation
= TAA_MITIGATION_VERW
;
391 } else if (!strcmp(str
, "full,nosmt")) {
392 taa_mitigation
= TAA_MITIGATION_VERW
;
398 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline
);
401 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
403 enum mmio_mitigations
{
405 MMIO_MITIGATION_UCODE_NEEDED
,
406 MMIO_MITIGATION_VERW
,
409 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
410 static enum mmio_mitigations mmio_mitigation __ro_after_init
= MMIO_MITIGATION_VERW
;
411 static bool mmio_nosmt __ro_after_init
= false;
413 static const char * const mmio_strings
[] = {
414 [MMIO_MITIGATION_OFF
] = "Vulnerable",
415 [MMIO_MITIGATION_UCODE_NEEDED
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
416 [MMIO_MITIGATION_VERW
] = "Mitigation: Clear CPU buffers",
419 static void __init
mmio_select_mitigation(void)
423 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA
) ||
424 cpu_mitigations_off()) {
425 mmio_mitigation
= MMIO_MITIGATION_OFF
;
429 if (mmio_mitigation
== MMIO_MITIGATION_OFF
)
432 ia32_cap
= x86_read_arch_cap_msr();
435 * Enable CPU buffer clear mitigation for host and VMM, if also affected
436 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
438 if (boot_cpu_has_bug(X86_BUG_MDS
) || (boot_cpu_has_bug(X86_BUG_TAA
) &&
439 boot_cpu_has(X86_FEATURE_RTM
)))
440 static_branch_enable(&mds_user_clear
);
442 static_branch_enable(&mmio_stale_data_clear
);
445 * Check if the system has the right microcode.
447 * CPU Fill buffer clear mitigation is enumerated by either an explicit
448 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
451 if ((ia32_cap
& ARCH_CAP_FB_CLEAR
) ||
452 (boot_cpu_has(X86_FEATURE_MD_CLEAR
) &&
453 boot_cpu_has(X86_FEATURE_FLUSH_L1D
) &&
454 !(ia32_cap
& ARCH_CAP_MDS_NO
)))
455 mmio_mitigation
= MMIO_MITIGATION_VERW
;
457 mmio_mitigation
= MMIO_MITIGATION_UCODE_NEEDED
;
459 if (mmio_nosmt
|| cpu_mitigations_auto_nosmt())
460 cpu_smt_disable(false);
463 static int __init
mmio_stale_data_parse_cmdline(char *str
)
465 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA
))
471 if (!strcmp(str
, "off")) {
472 mmio_mitigation
= MMIO_MITIGATION_OFF
;
473 } else if (!strcmp(str
, "full")) {
474 mmio_mitigation
= MMIO_MITIGATION_VERW
;
475 } else if (!strcmp(str
, "full,nosmt")) {
476 mmio_mitigation
= MMIO_MITIGATION_VERW
;
482 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline
);
485 #define pr_fmt(fmt) "" fmt
487 static void __init
md_clear_update_mitigation(void)
489 if (cpu_mitigations_off())
492 if (!static_key_enabled(&mds_user_clear
))
496 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
497 * mitigation, if necessary.
499 if (mds_mitigation
== MDS_MITIGATION_OFF
&&
500 boot_cpu_has_bug(X86_BUG_MDS
)) {
501 mds_mitigation
= MDS_MITIGATION_FULL
;
502 mds_select_mitigation();
504 if (taa_mitigation
== TAA_MITIGATION_OFF
&&
505 boot_cpu_has_bug(X86_BUG_TAA
)) {
506 taa_mitigation
= TAA_MITIGATION_VERW
;
507 taa_select_mitigation();
509 if (mmio_mitigation
== MMIO_MITIGATION_OFF
&&
510 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA
)) {
511 mmio_mitigation
= MMIO_MITIGATION_VERW
;
512 mmio_select_mitigation();
515 if (boot_cpu_has_bug(X86_BUG_MDS
))
516 pr_info("MDS: %s\n", mds_strings
[mds_mitigation
]);
517 if (boot_cpu_has_bug(X86_BUG_TAA
))
518 pr_info("TAA: %s\n", taa_strings
[taa_mitigation
]);
519 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA
))
520 pr_info("MMIO Stale Data: %s\n", mmio_strings
[mmio_mitigation
]);
524 #define pr_fmt(fmt) "SRBDS: " fmt
526 enum srbds_mitigations
{
527 SRBDS_MITIGATION_OFF
,
528 SRBDS_MITIGATION_UCODE_NEEDED
,
529 SRBDS_MITIGATION_FULL
,
530 SRBDS_MITIGATION_TSX_OFF
,
531 SRBDS_MITIGATION_HYPERVISOR
,
534 static enum srbds_mitigations srbds_mitigation __ro_after_init
= SRBDS_MITIGATION_FULL
;
536 static const char * const srbds_strings
[] = {
537 [SRBDS_MITIGATION_OFF
] = "Vulnerable",
538 [SRBDS_MITIGATION_UCODE_NEEDED
] = "Vulnerable: No microcode",
539 [SRBDS_MITIGATION_FULL
] = "Mitigation: Microcode",
540 [SRBDS_MITIGATION_TSX_OFF
] = "Mitigation: TSX disabled",
541 [SRBDS_MITIGATION_HYPERVISOR
] = "Unknown: Dependent on hypervisor status",
544 static bool srbds_off
;
546 void update_srbds_msr(void)
550 if (!boot_cpu_has_bug(X86_BUG_SRBDS
))
553 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
))
556 if (srbds_mitigation
== SRBDS_MITIGATION_UCODE_NEEDED
)
559 rdmsrl(MSR_IA32_MCU_OPT_CTRL
, mcu_ctrl
);
561 switch (srbds_mitigation
) {
562 case SRBDS_MITIGATION_OFF
:
563 case SRBDS_MITIGATION_TSX_OFF
:
564 mcu_ctrl
|= RNGDS_MITG_DIS
;
566 case SRBDS_MITIGATION_FULL
:
567 mcu_ctrl
&= ~RNGDS_MITG_DIS
;
573 wrmsrl(MSR_IA32_MCU_OPT_CTRL
, mcu_ctrl
);
576 static void __init
srbds_select_mitigation(void)
580 if (!boot_cpu_has_bug(X86_BUG_SRBDS
))
584 * Check to see if this is one of the MDS_NO systems supporting
585 * TSX that are only exposed to SRBDS when TSX is enabled.
587 ia32_cap
= x86_read_arch_cap_msr();
588 if ((ia32_cap
& ARCH_CAP_MDS_NO
) && !boot_cpu_has(X86_FEATURE_RTM
))
589 srbds_mitigation
= SRBDS_MITIGATION_TSX_OFF
;
590 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR
))
591 srbds_mitigation
= SRBDS_MITIGATION_HYPERVISOR
;
592 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL
))
593 srbds_mitigation
= SRBDS_MITIGATION_UCODE_NEEDED
;
594 else if (cpu_mitigations_off() || srbds_off
)
595 srbds_mitigation
= SRBDS_MITIGATION_OFF
;
598 pr_info("%s\n", srbds_strings
[srbds_mitigation
]);
601 static int __init
srbds_parse_cmdline(char *str
)
606 if (!boot_cpu_has_bug(X86_BUG_SRBDS
))
609 srbds_off
= !strcmp(str
, "off");
612 early_param("srbds", srbds_parse_cmdline
);
615 #define pr_fmt(fmt) "L1D Flush : " fmt
617 enum l1d_flush_mitigations
{
622 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata
= L1D_FLUSH_OFF
;
624 static void __init
l1d_flush_select_mitigation(void)
626 if (!l1d_flush_mitigation
|| !boot_cpu_has(X86_FEATURE_FLUSH_L1D
))
629 static_branch_enable(&switch_mm_cond_l1d_flush
);
630 pr_info("Conditional flush on switch_mm() enabled\n");
633 static int __init
l1d_flush_parse_cmdline(char *str
)
635 if (!strcmp(str
, "on"))
636 l1d_flush_mitigation
= L1D_FLUSH_ON
;
640 early_param("l1d_flush", l1d_flush_parse_cmdline
);
643 #define pr_fmt(fmt) "Spectre V1 : " fmt
645 enum spectre_v1_mitigation
{
646 SPECTRE_V1_MITIGATION_NONE
,
647 SPECTRE_V1_MITIGATION_AUTO
,
650 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init
=
651 SPECTRE_V1_MITIGATION_AUTO
;
653 static const char * const spectre_v1_strings
[] = {
654 [SPECTRE_V1_MITIGATION_NONE
] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
655 [SPECTRE_V1_MITIGATION_AUTO
] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
659 * Does SMAP provide full mitigation against speculative kernel access to
662 static bool smap_works_speculatively(void)
664 if (!boot_cpu_has(X86_FEATURE_SMAP
))
668 * On CPUs which are vulnerable to Meltdown, SMAP does not
669 * prevent speculative access to user data in the L1 cache.
670 * Consider SMAP to be non-functional as a mitigation on these
673 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN
))
679 static void __init
spectre_v1_select_mitigation(void)
681 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1
) || cpu_mitigations_off()) {
682 spectre_v1_mitigation
= SPECTRE_V1_MITIGATION_NONE
;
686 if (spectre_v1_mitigation
== SPECTRE_V1_MITIGATION_AUTO
) {
688 * With Spectre v1, a user can speculatively control either
689 * path of a conditional swapgs with a user-controlled GS
690 * value. The mitigation is to add lfences to both code paths.
692 * If FSGSBASE is enabled, the user can put a kernel address in
693 * GS, in which case SMAP provides no protection.
695 * If FSGSBASE is disabled, the user can only put a user space
696 * address in GS. That makes an attack harder, but still
697 * possible if there's no SMAP protection.
699 if (boot_cpu_has(X86_FEATURE_FSGSBASE
) ||
700 !smap_works_speculatively()) {
702 * Mitigation can be provided from SWAPGS itself or
703 * PTI as the CR3 write in the Meltdown mitigation
706 * If neither is there, mitigate with an LFENCE to
707 * stop speculation through swapgs.
709 if (boot_cpu_has_bug(X86_BUG_SWAPGS
) &&
710 !boot_cpu_has(X86_FEATURE_PTI
))
711 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER
);
714 * Enable lfences in the kernel entry (non-swapgs)
715 * paths, to prevent user entry from speculatively
718 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL
);
722 pr_info("%s\n", spectre_v1_strings
[spectre_v1_mitigation
]);
725 static int __init
nospectre_v1_cmdline(char *str
)
727 spectre_v1_mitigation
= SPECTRE_V1_MITIGATION_NONE
;
730 early_param("nospectre_v1", nospectre_v1_cmdline
);
733 #define pr_fmt(fmt) "Spectre V2 : " fmt
735 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
738 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init
=
739 SPECTRE_V2_USER_NONE
;
740 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init
=
741 SPECTRE_V2_USER_NONE
;
743 #ifdef CONFIG_RETPOLINE
744 static bool spectre_v2_bad_module
;
746 bool retpoline_module_ok(bool has_retpoline
)
748 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
751 pr_err("System may be vulnerable to spectre v2\n");
752 spectre_v2_bad_module
= true;
756 static inline const char *spectre_v2_module_string(void)
758 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
761 static inline const char *spectre_v2_module_string(void) { return ""; }
764 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
765 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
766 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
768 #ifdef CONFIG_BPF_SYSCALL
769 void unpriv_ebpf_notify(int new_state
)
774 /* Unprivileged eBPF is enabled */
776 switch (spectre_v2_enabled
) {
777 case SPECTRE_V2_EIBRS
:
778 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG
);
780 case SPECTRE_V2_EIBRS_LFENCE
:
781 if (sched_smt_active())
782 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG
);
790 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
792 int len
= strlen(opt
);
794 return len
== arglen
&& !strncmp(arg
, opt
, len
);
797 /* The kernel command line selection for spectre v2 */
798 enum spectre_v2_mitigation_cmd
{
801 SPECTRE_V2_CMD_FORCE
,
802 SPECTRE_V2_CMD_RETPOLINE
,
803 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
804 SPECTRE_V2_CMD_RETPOLINE_LFENCE
,
805 SPECTRE_V2_CMD_EIBRS
,
806 SPECTRE_V2_CMD_EIBRS_RETPOLINE
,
807 SPECTRE_V2_CMD_EIBRS_LFENCE
,
810 enum spectre_v2_user_cmd
{
811 SPECTRE_V2_USER_CMD_NONE
,
812 SPECTRE_V2_USER_CMD_AUTO
,
813 SPECTRE_V2_USER_CMD_FORCE
,
814 SPECTRE_V2_USER_CMD_PRCTL
,
815 SPECTRE_V2_USER_CMD_PRCTL_IBPB
,
816 SPECTRE_V2_USER_CMD_SECCOMP
,
817 SPECTRE_V2_USER_CMD_SECCOMP_IBPB
,
820 static const char * const spectre_v2_user_strings
[] = {
821 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
822 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
823 [SPECTRE_V2_USER_STRICT_PREFERRED
] = "User space: Mitigation: STIBP always-on protection",
824 [SPECTRE_V2_USER_PRCTL
] = "User space: Mitigation: STIBP via prctl",
825 [SPECTRE_V2_USER_SECCOMP
] = "User space: Mitigation: STIBP via seccomp and prctl",
828 static const struct {
830 enum spectre_v2_user_cmd cmd
;
832 } v2_user_options
[] __initconst
= {
833 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
834 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
835 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
836 { "prctl", SPECTRE_V2_USER_CMD_PRCTL
, false },
837 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB
, false },
838 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP
, false },
839 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB
, false },
842 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
844 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
845 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
848 static enum spectre_v2_user_cmd __init
849 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
855 case SPECTRE_V2_CMD_NONE
:
856 return SPECTRE_V2_USER_CMD_NONE
;
857 case SPECTRE_V2_CMD_FORCE
:
858 return SPECTRE_V2_USER_CMD_FORCE
;
863 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
866 return SPECTRE_V2_USER_CMD_AUTO
;
868 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
869 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
870 spec_v2_user_print_cond(v2_user_options
[i
].option
,
871 v2_user_options
[i
].secure
);
872 return v2_user_options
[i
].cmd
;
876 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
877 return SPECTRE_V2_USER_CMD_AUTO
;
880 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode
)
882 return (mode
== SPECTRE_V2_EIBRS
||
883 mode
== SPECTRE_V2_EIBRS_RETPOLINE
||
884 mode
== SPECTRE_V2_EIBRS_LFENCE
);
888 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
890 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
891 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
892 enum spectre_v2_user_cmd cmd
;
894 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
897 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
898 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
899 smt_possible
= false;
901 cmd
= spectre_v2_parse_user_cmdline(v2_cmd
);
903 case SPECTRE_V2_USER_CMD_NONE
:
905 case SPECTRE_V2_USER_CMD_FORCE
:
906 mode
= SPECTRE_V2_USER_STRICT
;
908 case SPECTRE_V2_USER_CMD_PRCTL
:
909 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
910 mode
= SPECTRE_V2_USER_PRCTL
;
912 case SPECTRE_V2_USER_CMD_AUTO
:
913 case SPECTRE_V2_USER_CMD_SECCOMP
:
914 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
915 if (IS_ENABLED(CONFIG_SECCOMP
))
916 mode
= SPECTRE_V2_USER_SECCOMP
;
918 mode
= SPECTRE_V2_USER_PRCTL
;
922 /* Initialize Indirect Branch Prediction Barrier */
923 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
924 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
926 spectre_v2_user_ibpb
= mode
;
928 case SPECTRE_V2_USER_CMD_FORCE
:
929 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
930 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
931 static_branch_enable(&switch_mm_always_ibpb
);
932 spectre_v2_user_ibpb
= SPECTRE_V2_USER_STRICT
;
934 case SPECTRE_V2_USER_CMD_PRCTL
:
935 case SPECTRE_V2_USER_CMD_AUTO
:
936 case SPECTRE_V2_USER_CMD_SECCOMP
:
937 static_branch_enable(&switch_mm_cond_ibpb
);
943 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
944 static_key_enabled(&switch_mm_always_ibpb
) ?
945 "always-on" : "conditional");
949 * If no STIBP, enhanced IBRS is enabled or SMT impossible, STIBP is not
952 if (!boot_cpu_has(X86_FEATURE_STIBP
) ||
954 spectre_v2_in_eibrs_mode(spectre_v2_enabled
))
958 * At this point, an STIBP mode other than "off" has been set.
959 * If STIBP support is not being forced, check if STIBP always-on
962 if (mode
!= SPECTRE_V2_USER_STRICT
&&
963 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON
))
964 mode
= SPECTRE_V2_USER_STRICT_PREFERRED
;
966 spectre_v2_user_stibp
= mode
;
969 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
972 static const char * const spectre_v2_strings
[] = {
973 [SPECTRE_V2_NONE
] = "Vulnerable",
974 [SPECTRE_V2_RETPOLINE
] = "Mitigation: Retpolines",
975 [SPECTRE_V2_LFENCE
] = "Mitigation: LFENCE",
976 [SPECTRE_V2_EIBRS
] = "Mitigation: Enhanced IBRS",
977 [SPECTRE_V2_EIBRS_LFENCE
] = "Mitigation: Enhanced IBRS + LFENCE",
978 [SPECTRE_V2_EIBRS_RETPOLINE
] = "Mitigation: Enhanced IBRS + Retpolines",
981 static const struct {
983 enum spectre_v2_mitigation_cmd cmd
;
985 } mitigation_options
[] __initconst
= {
986 { "off", SPECTRE_V2_CMD_NONE
, false },
987 { "on", SPECTRE_V2_CMD_FORCE
, true },
988 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
989 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE
, false },
990 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE
, false },
991 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
992 { "eibrs", SPECTRE_V2_CMD_EIBRS
, false },
993 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE
, false },
994 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE
, false },
995 { "auto", SPECTRE_V2_CMD_AUTO
, false },
998 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
1000 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
1001 pr_info("%s selected on command line.\n", reason
);
1004 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
1006 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
1010 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2") ||
1011 cpu_mitigations_off())
1012 return SPECTRE_V2_CMD_NONE
;
1014 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
1016 return SPECTRE_V2_CMD_AUTO
;
1018 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
1019 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
1021 cmd
= mitigation_options
[i
].cmd
;
1025 if (i
>= ARRAY_SIZE(mitigation_options
)) {
1026 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
1027 return SPECTRE_V2_CMD_AUTO
;
1030 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
1031 cmd
== SPECTRE_V2_CMD_RETPOLINE_LFENCE
||
1032 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
||
1033 cmd
== SPECTRE_V2_CMD_EIBRS_LFENCE
||
1034 cmd
== SPECTRE_V2_CMD_EIBRS_RETPOLINE
) &&
1035 !IS_ENABLED(CONFIG_RETPOLINE
)) {
1036 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1037 mitigation_options
[i
].option
);
1038 return SPECTRE_V2_CMD_AUTO
;
1041 if ((cmd
== SPECTRE_V2_CMD_EIBRS
||
1042 cmd
== SPECTRE_V2_CMD_EIBRS_LFENCE
||
1043 cmd
== SPECTRE_V2_CMD_EIBRS_RETPOLINE
) &&
1044 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
1045 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1046 mitigation_options
[i
].option
);
1047 return SPECTRE_V2_CMD_AUTO
;
1050 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE_LFENCE
||
1051 cmd
== SPECTRE_V2_CMD_EIBRS_LFENCE
) &&
1052 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
1053 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1054 mitigation_options
[i
].option
);
1055 return SPECTRE_V2_CMD_AUTO
;
1058 spec_v2_print_cond(mitigation_options
[i
].option
,
1059 mitigation_options
[i
].secure
);
1063 static enum spectre_v2_mitigation __init
spectre_v2_select_retpoline(void)
1065 if (!IS_ENABLED(CONFIG_RETPOLINE
)) {
1066 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1067 return SPECTRE_V2_NONE
;
1070 return SPECTRE_V2_RETPOLINE
;
1073 static void __init
spectre_v2_select_mitigation(void)
1075 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
1076 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
1079 * If the CPU is not affected and the command line mode is NONE or AUTO
1080 * then nothing to do.
1082 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
1083 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
1087 case SPECTRE_V2_CMD_NONE
:
1090 case SPECTRE_V2_CMD_FORCE
:
1091 case SPECTRE_V2_CMD_AUTO
:
1092 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
1093 mode
= SPECTRE_V2_EIBRS
;
1097 mode
= spectre_v2_select_retpoline();
1100 case SPECTRE_V2_CMD_RETPOLINE_LFENCE
:
1101 pr_err(SPECTRE_V2_LFENCE_MSG
);
1102 mode
= SPECTRE_V2_LFENCE
;
1105 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
1106 mode
= SPECTRE_V2_RETPOLINE
;
1109 case SPECTRE_V2_CMD_RETPOLINE
:
1110 mode
= spectre_v2_select_retpoline();
1113 case SPECTRE_V2_CMD_EIBRS
:
1114 mode
= SPECTRE_V2_EIBRS
;
1117 case SPECTRE_V2_CMD_EIBRS_LFENCE
:
1118 mode
= SPECTRE_V2_EIBRS_LFENCE
;
1121 case SPECTRE_V2_CMD_EIBRS_RETPOLINE
:
1122 mode
= SPECTRE_V2_EIBRS_RETPOLINE
;
1126 if (mode
== SPECTRE_V2_EIBRS
&& unprivileged_ebpf_enabled())
1127 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG
);
1129 if (spectre_v2_in_eibrs_mode(mode
)) {
1130 /* Force it so VMEXIT will restore correctly */
1131 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
1132 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1136 case SPECTRE_V2_NONE
:
1137 case SPECTRE_V2_EIBRS
:
1140 case SPECTRE_V2_LFENCE
:
1141 case SPECTRE_V2_EIBRS_LFENCE
:
1142 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE
);
1145 case SPECTRE_V2_RETPOLINE
:
1146 case SPECTRE_V2_EIBRS_RETPOLINE
:
1147 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
1151 spectre_v2_enabled
= mode
;
1152 pr_info("%s\n", spectre_v2_strings
[mode
]);
1155 * If spectre v2 protection has been enabled, unconditionally fill
1156 * RSB during a context switch; this protects against two independent
1159 * - RSB underflow (and switch to BTB) on Skylake+
1160 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
1162 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
1163 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1166 * Retpoline means the kernel is safe because it has no indirect
1167 * branches. Enhanced IBRS protects firmware too, so, enable restricted
1168 * speculation around firmware calls only when Enhanced IBRS isn't
1171 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1172 * the user might select retpoline on the kernel command line and if
1173 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1174 * enable IBRS around firmware calls.
1176 if (boot_cpu_has(X86_FEATURE_IBRS
) && !spectre_v2_in_eibrs_mode(mode
)) {
1177 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
1178 pr_info("Enabling Restricted Speculation for firmware calls\n");
1181 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1182 spectre_v2_user_select_mitigation(cmd
);
1185 static void update_stibp_msr(void * __unused
)
1187 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1190 /* Update x86_spec_ctrl_base in case SMT state changed. */
1191 static void update_stibp_strict(void)
1193 u64 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
1195 if (sched_smt_active())
1196 mask
|= SPEC_CTRL_STIBP
;
1198 if (mask
== x86_spec_ctrl_base
)
1201 pr_info("Update user space SMT mitigation: STIBP %s\n",
1202 mask
& SPEC_CTRL_STIBP
? "always-on" : "off");
1203 x86_spec_ctrl_base
= mask
;
1204 on_each_cpu(update_stibp_msr
, NULL
, 1);
1207 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1208 static void update_indir_branch_cond(void)
1210 if (sched_smt_active())
1211 static_branch_enable(&switch_to_cond_stibp
);
1213 static_branch_disable(&switch_to_cond_stibp
);
1217 #define pr_fmt(fmt) fmt
1219 /* Update the static key controlling the MDS CPU buffer clear in idle */
1220 static void update_mds_branch_idle(void)
1223 * Enable the idle clearing if SMT is active on CPUs which are
1224 * affected only by MSBDS and not any other MDS variant.
1226 * The other variants cannot be mitigated when SMT is enabled, so
1227 * clearing the buffers on idle just to prevent the Store Buffer
1228 * repartitioning leak would be a window dressing exercise.
1230 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY
))
1233 if (sched_smt_active())
1234 static_branch_enable(&mds_idle_clear
);
1236 static_branch_disable(&mds_idle_clear
);
1239 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1240 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1242 void cpu_bugs_smt_update(void)
1244 mutex_lock(&spec_ctrl_mutex
);
1246 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1247 spectre_v2_enabled
== SPECTRE_V2_EIBRS_LFENCE
)
1248 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG
);
1250 switch (spectre_v2_user_stibp
) {
1251 case SPECTRE_V2_USER_NONE
:
1253 case SPECTRE_V2_USER_STRICT
:
1254 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1255 update_stibp_strict();
1257 case SPECTRE_V2_USER_PRCTL
:
1258 case SPECTRE_V2_USER_SECCOMP
:
1259 update_indir_branch_cond();
1263 switch (mds_mitigation
) {
1264 case MDS_MITIGATION_FULL
:
1265 case MDS_MITIGATION_VMWERV
:
1266 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY
))
1267 pr_warn_once(MDS_MSG_SMT
);
1268 update_mds_branch_idle();
1270 case MDS_MITIGATION_OFF
:
1274 switch (taa_mitigation
) {
1275 case TAA_MITIGATION_VERW
:
1276 case TAA_MITIGATION_UCODE_NEEDED
:
1277 if (sched_smt_active())
1278 pr_warn_once(TAA_MSG_SMT
);
1280 case TAA_MITIGATION_TSX_DISABLED
:
1281 case TAA_MITIGATION_OFF
:
1285 mutex_unlock(&spec_ctrl_mutex
);
1289 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1291 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
1293 /* The kernel command line selection */
1294 enum ssb_mitigation_cmd
{
1295 SPEC_STORE_BYPASS_CMD_NONE
,
1296 SPEC_STORE_BYPASS_CMD_AUTO
,
1297 SPEC_STORE_BYPASS_CMD_ON
,
1298 SPEC_STORE_BYPASS_CMD_PRCTL
,
1299 SPEC_STORE_BYPASS_CMD_SECCOMP
,
1302 static const char * const ssb_strings
[] = {
1303 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
1304 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
1305 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
1306 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1309 static const struct {
1311 enum ssb_mitigation_cmd cmd
;
1312 } ssb_mitigation_options
[] __initconst
= {
1313 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
1314 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
1315 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
1316 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
1317 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
1320 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
1322 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
1326 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable") ||
1327 cpu_mitigations_off()) {
1328 return SPEC_STORE_BYPASS_CMD_NONE
;
1330 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
1333 return SPEC_STORE_BYPASS_CMD_AUTO
;
1335 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
1336 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
1339 cmd
= ssb_mitigation_options
[i
].cmd
;
1343 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
1344 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
1345 return SPEC_STORE_BYPASS_CMD_AUTO
;
1352 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
1354 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
1355 enum ssb_mitigation_cmd cmd
;
1357 if (!boot_cpu_has(X86_FEATURE_SSBD
))
1360 cmd
= ssb_parse_cmdline();
1361 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
1362 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
1363 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
1367 case SPEC_STORE_BYPASS_CMD_AUTO
:
1368 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
1370 * Choose prctl+seccomp as the default mode if seccomp is
1373 if (IS_ENABLED(CONFIG_SECCOMP
))
1374 mode
= SPEC_STORE_BYPASS_SECCOMP
;
1376 mode
= SPEC_STORE_BYPASS_PRCTL
;
1378 case SPEC_STORE_BYPASS_CMD_ON
:
1379 mode
= SPEC_STORE_BYPASS_DISABLE
;
1381 case SPEC_STORE_BYPASS_CMD_PRCTL
:
1382 mode
= SPEC_STORE_BYPASS_PRCTL
;
1384 case SPEC_STORE_BYPASS_CMD_NONE
:
1389 * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1390 * bit in the mask to allow guests to use the mitigation even in the
1391 * case where the host does not enable it.
1393 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
1394 static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
1395 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
1399 * We have three CPU feature flags that are in play here:
1400 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1401 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1402 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1404 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
1405 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
1407 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1408 * use a completely different MSR and bit dependent on family.
1410 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
1411 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
1412 x86_amd_ssb_disable();
1414 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
1415 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1422 static void ssb_select_mitigation(void)
1424 ssb_mode
= __ssb_select_mitigation();
1426 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
1427 pr_info("%s\n", ssb_strings
[ssb_mode
]);
1431 #define pr_fmt(fmt) "Speculation prctl: " fmt
1433 static void task_update_spec_tif(struct task_struct
*tsk
)
1435 /* Force the update of the real TIF bits */
1436 set_tsk_thread_flag(tsk
, TIF_SPEC_FORCE_UPDATE
);
1439 * Immediately update the speculation control MSRs for the current
1440 * task, but for a non-current task delay setting the CPU
1441 * mitigation until it is scheduled next.
1443 * This can only happen for SECCOMP mitigation. For PRCTL it's
1444 * always the current task.
1447 speculation_ctrl_update_current();
1450 static int l1d_flush_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
1453 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush
))
1457 case PR_SPEC_ENABLE
:
1458 set_ti_thread_flag(&task
->thread_info
, TIF_SPEC_L1D_FLUSH
);
1460 case PR_SPEC_DISABLE
:
1461 clear_ti_thread_flag(&task
->thread_info
, TIF_SPEC_L1D_FLUSH
);
1468 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
1470 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
1471 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
1475 case PR_SPEC_ENABLE
:
1476 /* If speculation is force disabled, enable is not allowed */
1477 if (task_spec_ssb_force_disable(task
))
1479 task_clear_spec_ssb_disable(task
);
1480 task_clear_spec_ssb_noexec(task
);
1481 task_update_spec_tif(task
);
1483 case PR_SPEC_DISABLE
:
1484 task_set_spec_ssb_disable(task
);
1485 task_clear_spec_ssb_noexec(task
);
1486 task_update_spec_tif(task
);
1488 case PR_SPEC_FORCE_DISABLE
:
1489 task_set_spec_ssb_disable(task
);
1490 task_set_spec_ssb_force_disable(task
);
1491 task_clear_spec_ssb_noexec(task
);
1492 task_update_spec_tif(task
);
1494 case PR_SPEC_DISABLE_NOEXEC
:
1495 if (task_spec_ssb_force_disable(task
))
1497 task_set_spec_ssb_disable(task
);
1498 task_set_spec_ssb_noexec(task
);
1499 task_update_spec_tif(task
);
1507 static bool is_spec_ib_user_controlled(void)
1509 return spectre_v2_user_ibpb
== SPECTRE_V2_USER_PRCTL
||
1510 spectre_v2_user_ibpb
== SPECTRE_V2_USER_SECCOMP
||
1511 spectre_v2_user_stibp
== SPECTRE_V2_USER_PRCTL
||
1512 spectre_v2_user_stibp
== SPECTRE_V2_USER_SECCOMP
;
1515 static int ib_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
1518 case PR_SPEC_ENABLE
:
1519 if (spectre_v2_user_ibpb
== SPECTRE_V2_USER_NONE
&&
1520 spectre_v2_user_stibp
== SPECTRE_V2_USER_NONE
)
1524 * With strict mode for both IBPB and STIBP, the instruction
1525 * code paths avoid checking this task flag and instead,
1526 * unconditionally run the instruction. However, STIBP and IBPB
1527 * are independent and either can be set to conditionally
1528 * enabled regardless of the mode of the other.
1530 * If either is set to conditional, allow the task flag to be
1531 * updated, unless it was force-disabled by a previous prctl
1532 * call. Currently, this is possible on an AMD CPU which has the
1533 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1534 * kernel is booted with 'spectre_v2_user=seccomp', then
1535 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1536 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1538 if (!is_spec_ib_user_controlled() ||
1539 task_spec_ib_force_disable(task
))
1542 task_clear_spec_ib_disable(task
);
1543 task_update_spec_tif(task
);
1545 case PR_SPEC_DISABLE
:
1546 case PR_SPEC_FORCE_DISABLE
:
1548 * Indirect branch speculation is always allowed when
1549 * mitigation is force disabled.
1551 if (spectre_v2_user_ibpb
== SPECTRE_V2_USER_NONE
&&
1552 spectre_v2_user_stibp
== SPECTRE_V2_USER_NONE
)
1555 if (!is_spec_ib_user_controlled())
1558 task_set_spec_ib_disable(task
);
1559 if (ctrl
== PR_SPEC_FORCE_DISABLE
)
1560 task_set_spec_ib_force_disable(task
);
1561 task_update_spec_tif(task
);
1569 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
1573 case PR_SPEC_STORE_BYPASS
:
1574 return ssb_prctl_set(task
, ctrl
);
1575 case PR_SPEC_INDIRECT_BRANCH
:
1576 return ib_prctl_set(task
, ctrl
);
1577 case PR_SPEC_L1D_FLUSH
:
1578 return l1d_flush_prctl_set(task
, ctrl
);
1584 #ifdef CONFIG_SECCOMP
1585 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
1587 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
1588 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
1589 if (spectre_v2_user_ibpb
== SPECTRE_V2_USER_SECCOMP
||
1590 spectre_v2_user_stibp
== SPECTRE_V2_USER_SECCOMP
)
1591 ib_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
1595 static int l1d_flush_prctl_get(struct task_struct
*task
)
1597 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush
))
1598 return PR_SPEC_FORCE_DISABLE
;
1600 if (test_ti_thread_flag(&task
->thread_info
, TIF_SPEC_L1D_FLUSH
))
1601 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
1603 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
1606 static int ssb_prctl_get(struct task_struct
*task
)
1609 case SPEC_STORE_BYPASS_DISABLE
:
1610 return PR_SPEC_DISABLE
;
1611 case SPEC_STORE_BYPASS_SECCOMP
:
1612 case SPEC_STORE_BYPASS_PRCTL
:
1613 if (task_spec_ssb_force_disable(task
))
1614 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
1615 if (task_spec_ssb_noexec(task
))
1616 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE_NOEXEC
;
1617 if (task_spec_ssb_disable(task
))
1618 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
1619 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
1621 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
1622 return PR_SPEC_ENABLE
;
1623 return PR_SPEC_NOT_AFFECTED
;
1627 static int ib_prctl_get(struct task_struct
*task
)
1629 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
1630 return PR_SPEC_NOT_AFFECTED
;
1632 if (spectre_v2_user_ibpb
== SPECTRE_V2_USER_NONE
&&
1633 spectre_v2_user_stibp
== SPECTRE_V2_USER_NONE
)
1634 return PR_SPEC_ENABLE
;
1635 else if (is_spec_ib_user_controlled()) {
1636 if (task_spec_ib_force_disable(task
))
1637 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
1638 if (task_spec_ib_disable(task
))
1639 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
1640 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
1641 } else if (spectre_v2_user_ibpb
== SPECTRE_V2_USER_STRICT
||
1642 spectre_v2_user_stibp
== SPECTRE_V2_USER_STRICT
||
1643 spectre_v2_user_stibp
== SPECTRE_V2_USER_STRICT_PREFERRED
)
1644 return PR_SPEC_DISABLE
;
1646 return PR_SPEC_NOT_AFFECTED
;
1649 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
1652 case PR_SPEC_STORE_BYPASS
:
1653 return ssb_prctl_get(task
);
1654 case PR_SPEC_INDIRECT_BRANCH
:
1655 return ib_prctl_get(task
);
1656 case PR_SPEC_L1D_FLUSH
:
1657 return l1d_flush_prctl_get(task
);
1663 void x86_spec_ctrl_setup_ap(void)
1665 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
1666 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1668 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
1669 x86_amd_ssb_disable();
1672 bool itlb_multihit_kvm_mitigation
;
1673 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation
);
1676 #define pr_fmt(fmt) "L1TF: " fmt
1678 /* Default mitigation for L1TF-affected CPUs */
1679 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
1680 #if IS_ENABLED(CONFIG_KVM_INTEL)
1681 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
1683 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
1684 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
1687 * These CPUs all support 44bits physical address space internally in the
1688 * cache but CPUID can report a smaller number of physical address bits.
1690 * The L1TF mitigation uses the top most address bit for the inversion of
1691 * non present PTEs. When the installed memory reaches into the top most
1692 * address bit due to memory holes, which has been observed on machines
1693 * which report 36bits physical address bits and have 32G RAM installed,
1694 * then the mitigation range check in l1tf_select_mitigation() triggers.
1695 * This is a false positive because the mitigation is still possible due to
1696 * the fact that the cache uses 44bit internally. Use the cache bits
1697 * instead of the reported physical bits and adjust them on the affected
1698 * machines to 44bit if the reported bits are less than 44.
1700 static void override_cache_bits(struct cpuinfo_x86
*c
)
1705 switch (c
->x86_model
) {
1706 case INTEL_FAM6_NEHALEM
:
1707 case INTEL_FAM6_WESTMERE
:
1708 case INTEL_FAM6_SANDYBRIDGE
:
1709 case INTEL_FAM6_IVYBRIDGE
:
1710 case INTEL_FAM6_HASWELL
:
1711 case INTEL_FAM6_HASWELL_L
:
1712 case INTEL_FAM6_HASWELL_G
:
1713 case INTEL_FAM6_BROADWELL
:
1714 case INTEL_FAM6_BROADWELL_G
:
1715 case INTEL_FAM6_SKYLAKE_L
:
1716 case INTEL_FAM6_SKYLAKE
:
1717 case INTEL_FAM6_KABYLAKE_L
:
1718 case INTEL_FAM6_KABYLAKE
:
1719 if (c
->x86_cache_bits
< 44)
1720 c
->x86_cache_bits
= 44;
1725 static void __init
l1tf_select_mitigation(void)
1729 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1732 if (cpu_mitigations_off())
1733 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1734 else if (cpu_mitigations_auto_nosmt())
1735 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1737 override_cache_bits(&boot_cpu_data
);
1739 switch (l1tf_mitigation
) {
1740 case L1TF_MITIGATION_OFF
:
1741 case L1TF_MITIGATION_FLUSH_NOWARN
:
1742 case L1TF_MITIGATION_FLUSH
:
1744 case L1TF_MITIGATION_FLUSH_NOSMT
:
1745 case L1TF_MITIGATION_FULL
:
1746 cpu_smt_disable(false);
1748 case L1TF_MITIGATION_FULL_FORCE
:
1749 cpu_smt_disable(true);
1753 #if CONFIG_PGTABLE_LEVELS == 2
1754 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1758 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
1759 if (l1tf_mitigation
!= L1TF_MITIGATION_OFF
&&
1760 e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
1761 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1762 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1764 pr_info("However, doing so will make a part of your RAM unusable.\n");
1765 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1769 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
1772 static int __init
l1tf_cmdline(char *str
)
1774 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1780 if (!strcmp(str
, "off"))
1781 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1782 else if (!strcmp(str
, "flush,nowarn"))
1783 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
1784 else if (!strcmp(str
, "flush"))
1785 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
1786 else if (!strcmp(str
, "flush,nosmt"))
1787 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1788 else if (!strcmp(str
, "full"))
1789 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
1790 else if (!strcmp(str
, "full,force"))
1791 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
1795 early_param("l1tf", l1tf_cmdline
);
1798 #define pr_fmt(fmt) fmt
1802 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1804 #if IS_ENABLED(CONFIG_KVM_INTEL)
1805 static const char * const l1tf_vmx_states
[] = {
1806 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
1807 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
1808 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
1809 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
1810 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
1811 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
1814 static ssize_t
l1tf_show_state(char *buf
)
1816 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
1817 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1819 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
1820 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
1821 sched_smt_active())) {
1822 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
1823 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
1826 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
1827 l1tf_vmx_states
[l1tf_vmx_mitigation
],
1828 sched_smt_active() ? "vulnerable" : "disabled");
1831 static ssize_t
itlb_multihit_show_state(char *buf
)
1833 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL
) ||
1834 !boot_cpu_has(X86_FEATURE_VMX
))
1835 return sprintf(buf
, "KVM: Mitigation: VMX unsupported\n");
1836 else if (!(cr4_read_shadow() & X86_CR4_VMXE
))
1837 return sprintf(buf
, "KVM: Mitigation: VMX disabled\n");
1838 else if (itlb_multihit_kvm_mitigation
)
1839 return sprintf(buf
, "KVM: Mitigation: Split huge pages\n");
1841 return sprintf(buf
, "KVM: Vulnerable\n");
1844 static ssize_t
l1tf_show_state(char *buf
)
1846 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1849 static ssize_t
itlb_multihit_show_state(char *buf
)
1851 return sprintf(buf
, "Processor vulnerable\n");
1855 static ssize_t
mds_show_state(char *buf
)
1857 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
1858 return sprintf(buf
, "%s; SMT Host state unknown\n",
1859 mds_strings
[mds_mitigation
]);
1862 if (boot_cpu_has(X86_BUG_MSBDS_ONLY
)) {
1863 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1864 (mds_mitigation
== MDS_MITIGATION_OFF
? "vulnerable" :
1865 sched_smt_active() ? "mitigated" : "disabled"));
1868 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1869 sched_smt_active() ? "vulnerable" : "disabled");
1872 static ssize_t
tsx_async_abort_show_state(char *buf
)
1874 if ((taa_mitigation
== TAA_MITIGATION_TSX_DISABLED
) ||
1875 (taa_mitigation
== TAA_MITIGATION_OFF
))
1876 return sprintf(buf
, "%s\n", taa_strings
[taa_mitigation
]);
1878 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
1879 return sprintf(buf
, "%s; SMT Host state unknown\n",
1880 taa_strings
[taa_mitigation
]);
1883 return sprintf(buf
, "%s; SMT %s\n", taa_strings
[taa_mitigation
],
1884 sched_smt_active() ? "vulnerable" : "disabled");
1887 static char *stibp_state(void)
1889 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled
))
1892 switch (spectre_v2_user_stibp
) {
1893 case SPECTRE_V2_USER_NONE
:
1894 return ", STIBP: disabled";
1895 case SPECTRE_V2_USER_STRICT
:
1896 return ", STIBP: forced";
1897 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1898 return ", STIBP: always-on";
1899 case SPECTRE_V2_USER_PRCTL
:
1900 case SPECTRE_V2_USER_SECCOMP
:
1901 if (static_key_enabled(&switch_to_cond_stibp
))
1902 return ", STIBP: conditional";
1907 static char *ibpb_state(void)
1909 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
1910 if (static_key_enabled(&switch_mm_always_ibpb
))
1911 return ", IBPB: always-on";
1912 if (static_key_enabled(&switch_mm_cond_ibpb
))
1913 return ", IBPB: conditional";
1914 return ", IBPB: disabled";
1919 static ssize_t
spectre_v2_show_state(char *buf
)
1921 if (spectre_v2_enabled
== SPECTRE_V2_LFENCE
)
1922 return sprintf(buf
, "Vulnerable: LFENCE\n");
1924 if (spectre_v2_enabled
== SPECTRE_V2_EIBRS
&& unprivileged_ebpf_enabled())
1925 return sprintf(buf
, "Vulnerable: eIBRS with unprivileged eBPF\n");
1927 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1928 spectre_v2_enabled
== SPECTRE_V2_EIBRS_LFENCE
)
1929 return sprintf(buf
, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
1931 return sprintf(buf
, "%s%s%s%s%s%s\n",
1932 spectre_v2_strings
[spectre_v2_enabled
],
1934 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
1936 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
1937 spectre_v2_module_string());
1940 static ssize_t
srbds_show_state(char *buf
)
1942 return sprintf(buf
, "%s\n", srbds_strings
[srbds_mitigation
]);
1945 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
1946 char *buf
, unsigned int bug
)
1948 if (!boot_cpu_has_bug(bug
))
1949 return sprintf(buf
, "Not affected\n");
1952 case X86_BUG_CPU_MELTDOWN
:
1953 if (boot_cpu_has(X86_FEATURE_PTI
))
1954 return sprintf(buf
, "Mitigation: PTI\n");
1956 if (hypervisor_is_type(X86_HYPER_XEN_PV
))
1957 return sprintf(buf
, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
1961 case X86_BUG_SPECTRE_V1
:
1962 return sprintf(buf
, "%s\n", spectre_v1_strings
[spectre_v1_mitigation
]);
1964 case X86_BUG_SPECTRE_V2
:
1965 return spectre_v2_show_state(buf
);
1967 case X86_BUG_SPEC_STORE_BYPASS
:
1968 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
1971 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
1972 return l1tf_show_state(buf
);
1976 return mds_show_state(buf
);
1979 return tsx_async_abort_show_state(buf
);
1981 case X86_BUG_ITLB_MULTIHIT
:
1982 return itlb_multihit_show_state(buf
);
1985 return srbds_show_state(buf
);
1991 return sprintf(buf
, "Vulnerable\n");
1994 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1996 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1999 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2001 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
2004 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2006 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
2009 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2011 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
2014 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2016 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);
2019 ssize_t
cpu_show_mds(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2021 return cpu_show_common(dev
, attr
, buf
, X86_BUG_MDS
);
2024 ssize_t
cpu_show_tsx_async_abort(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2026 return cpu_show_common(dev
, attr
, buf
, X86_BUG_TAA
);
2029 ssize_t
cpu_show_itlb_multihit(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2031 return cpu_show_common(dev
, attr
, buf
, X86_BUG_ITLB_MULTIHIT
);
2034 ssize_t
cpu_show_srbds(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
2036 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SRBDS
);