arch/x86/kernel/cpu/bugs.c

   1 /*
   2  *  Copyright (C) 1994  Linus Torvalds
   3  *
   4  *  Cyrix stuff, June 1998 by:
   5  *      - Rafael R. Reilova (moved everything from head.S),
   6  *        <rreilova@ececs.uc.edu>
   7  *      - Channing Corn (tests & fixes),
   8  *      - Andrew D. Balsa (code cleanup).
   9  */
  10 #include <linux/init.h>
  11 #include <linux/utsname.h>
  12 #include <linux/cpu.h>
  13 #include <linux/smp.h>
  14 #include <linux/nospec.h>
  15 #include <linux/prctl.h>
  16
  17 #include <asm/spec-ctrl.h>
  18 #include <asm/cmdline.h>
  19 #include <asm/bugs.h>
  20 #include <asm/processor.h>
  21 #include <asm/processor-flags.h>
  22 #include <asm/fpu/internal.h>
  23 #include <asm/msr.h>
  24 #include <asm/paravirt.h>
  25 #include <asm/alternative.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/set_memory.h>
  28 #include <asm/intel-family.h>
  29
  30 static void __init spectre_v2_select_mitigation(void);
  31 static void __init ssb_select_mitigation(void);
  32
  33 /*
  34  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  35  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  36  */
  37 u64 __ro_after_init x86_spec_ctrl_base;
  38 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  39
  40 /*
  41  * The vendor and possibly platform specific bits which can be modified in
  42  * x86_spec_ctrl_base.
  43  */
  44 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  45
  46 /*
  47  * AMD specific MSR info for Speculative Store Bypass control.
  48  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  49  */
  50 u64 __ro_after_init x86_amd_ls_cfg_base;
  51 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  52
  53 void __init check_bugs(void)
  54 {
  55         identify_boot_cpu();
  56
  57         if (!IS_ENABLED(CONFIG_SMP)) {
  58                 pr_info("CPU: ");
  59                 print_cpu_info(&boot_cpu_data);
  60         }
  61
  62         /*
  63          * Read the SPEC_CTRL MSR to account for reserved bits which may
  64          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  65          * init code as it is not enumerated and depends on the family.
  66          */
  67         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  68                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  69
  70         /* Select the proper spectre mitigation before patching alternatives */
  71         spectre_v2_select_mitigation();
  72
  73         /*
  74          * Select proper mitigation for any exposure to the Speculative Store
  75          * Bypass vulnerability.
  76          */
  77         ssb_select_mitigation();
  78
  79 #ifdef CONFIG_X86_32
  80         /*
  81          * Check whether we are able to run this kernel safely on SMP.
  82          *
  83          * - i386 is no longer supported.
  84          * - In order to run on anything without a TSC, we need to be
  85          *   compiled for a i486.
  86          */
  87         if (boot_cpu_data.x86 < 4)
  88                 panic("Kernel requires i486+ for 'invlpg' and other features");
  89
  90         init_utsname()->machine[1] =
  91                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  92         alternative_instructions();
  93
  94         fpu__init_check_bugs();
  95 #else /* CONFIG_X86_64 */
  96         alternative_instructions();
  97
  98         /*
  99          * Make sure the first 2MB area is not mapped by huge pages
 100          * There are typically fixed size MTRRs in there and overlapping
 101          * MTRRs into large pages causes slow downs.
 102          *
 103          * Right now we don't do that with gbpages because there seems
 104          * very little benefit for that case.
 105          */
 106         if (!direct_gbpages)
 107                 set_memory_4k((unsigned long)__va(0), 1);
 108 #endif
 109 }
 110
 111 /* The kernel command line selection */
 112 enum spectre_v2_mitigation_cmd {
 113         SPECTRE_V2_CMD_NONE,
 114         SPECTRE_V2_CMD_AUTO,
 115         SPECTRE_V2_CMD_FORCE,
 116         SPECTRE_V2_CMD_RETPOLINE,
 117         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 118         SPECTRE_V2_CMD_RETPOLINE_AMD,
 119 };
 120
 121 static const char *spectre_v2_strings[] = {
 122         [SPECTRE_V2_NONE]                       = "Vulnerable",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 125         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 126         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 127 };
 128
 129 #undef pr_fmt
 130 #define pr_fmt(fmt)     "Spectre V2 mitigation: " fmt
 131
 132 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 133         SPECTRE_V2_NONE;
 134
 135 void
 136 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 137 {
 138         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 139         struct thread_info *ti = current_thread_info();
 140
 141         /* Is MSR_SPEC_CTRL implemented ? */
 142         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 143                 /*
 144                  * Restrict guest_spec_ctrl to supported values. Clear the
 145                  * modifiable bits in the host base value and or the
 146                  * modifiable bits from the guest value.
 147                  */
 148                 guestval = hostval & ~x86_spec_ctrl_mask;
 149                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 150
 151                 /* SSBD controlled in MSR_SPEC_CTRL */
 152                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 153                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 154
 155                 if (hostval != guestval) {
 156                         msrval = setguest ? guestval : hostval;
 157                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 158                 }
 159         }
 160
 161         /*
 162          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 163          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 164          */
 165         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 166             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 167                 return;
 168
 169         /*
 170          * If the host has SSBD mitigation enabled, force it in the host's
 171          * virtual MSR value. If its not permanently enabled, evaluate
 172          * current's TIF_SSBD thread flag.
 173          */
 174         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 175                 hostval = SPEC_CTRL_SSBD;
 176         else
 177                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 178
 179         /* Sanitize the guest value */
 180         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 181
 182         if (hostval != guestval) {
 183                 unsigned long tif;
 184
 185                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 186                                  ssbd_spec_ctrl_to_tif(hostval);
 187
 188                 speculative_store_bypass_update(tif);
 189         }
 190 }
 191 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 192
 193 static void x86_amd_ssb_disable(void)
 194 {
 195         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 196
 197         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 198                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 199         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 200                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 201 }
 202
 203 static void __init spec2_print_if_insecure(const char *reason)
 204 {
 205         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 206                 pr_info("%s\n", reason);
 207 }
 208
 209 static void __init spec2_print_if_secure(const char *reason)
 210 {
 211         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 212                 pr_info("%s\n", reason);
 213 }
 214
 215 static inline bool retp_compiler(void)
 216 {
 217         return __is_defined(RETPOLINE);
 218 }
 219
 220 static inline bool match_option(const char *arg, int arglen, const char *opt)
 221 {
 222         int len = strlen(opt);
 223
 224         return len == arglen && !strncmp(arg, opt, len);
 225 }
 226
 227 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 228 {
 229         char arg[20];
 230         int ret;
 231
 232         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
 233                                   sizeof(arg));
 234         if (ret > 0)  {
 235                 if (match_option(arg, ret, "off")) {
 236                         goto disable;
 237                 } else if (match_option(arg, ret, "on")) {
 238                         spec2_print_if_secure("force enabled on command line.");
 239                         return SPECTRE_V2_CMD_FORCE;
 240                 } else if (match_option(arg, ret, "retpoline")) {
 241                         spec2_print_if_insecure("retpoline selected on command line.");
 242                         return SPECTRE_V2_CMD_RETPOLINE;
 243                 } else if (match_option(arg, ret, "retpoline,amd")) {
 244                         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 245                                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 246                                 return SPECTRE_V2_CMD_AUTO;
 247                         }
 248                         spec2_print_if_insecure("AMD retpoline selected on command line.");
 249                         return SPECTRE_V2_CMD_RETPOLINE_AMD;
 250                 } else if (match_option(arg, ret, "retpoline,generic")) {
 251                         spec2_print_if_insecure("generic retpoline selected on command line.");
 252                         return SPECTRE_V2_CMD_RETPOLINE_GENERIC;
 253                 } else if (match_option(arg, ret, "auto")) {
 254                         return SPECTRE_V2_CMD_AUTO;
 255                 }
 256         }
 257
 258         if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 259                 return SPECTRE_V2_CMD_AUTO;
 260 disable:
 261         spec2_print_if_insecure("disabled on command line.");
 262         return SPECTRE_V2_CMD_NONE;
 263 }
 264
 265 /* Check for Skylake-like CPUs (for RSB handling) */
 266 static bool __init is_skylake_era(void)
 267 {
 268         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 269             boot_cpu_data.x86 == 6) {
 270                 switch (boot_cpu_data.x86_model) {
 271                 case INTEL_FAM6_SKYLAKE_MOBILE:
 272                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 273                 case INTEL_FAM6_SKYLAKE_X:
 274                 case INTEL_FAM6_KABYLAKE_MOBILE:
 275                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 276                         return true;
 277                 }
 278         }
 279         return false;
 280 }
 281
 282 static void __init spectre_v2_select_mitigation(void)
 283 {
 284         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 285         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 286
 287         /*
 288          * If the CPU is not affected and the command line mode is NONE or AUTO
 289          * then nothing to do.
 290          */
 291         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 292             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 293                 return;
 294
 295         switch (cmd) {
 296         case SPECTRE_V2_CMD_NONE:
 297                 return;
 298
 299         case SPECTRE_V2_CMD_FORCE:
 300                 /* FALLTRHU */
 301         case SPECTRE_V2_CMD_AUTO:
 302                 goto retpoline_auto;
 303
 304         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 305                 if (IS_ENABLED(CONFIG_RETPOLINE))
 306                         goto retpoline_amd;
 307                 break;
 308         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 309                 if (IS_ENABLED(CONFIG_RETPOLINE))
 310                         goto retpoline_generic;
 311                 break;
 312         case SPECTRE_V2_CMD_RETPOLINE:
 313                 if (IS_ENABLED(CONFIG_RETPOLINE))
 314                         goto retpoline_auto;
 315                 break;
 316         }
 317         pr_err("kernel not compiled with retpoline; no mitigation available!");
 318         return;
 319
 320 retpoline_auto:
 321         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 322         retpoline_amd:
 323                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 324                         pr_err("LFENCE not serializing. Switching to generic retpoline\n");
 325                         goto retpoline_generic;
 326                 }
 327                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 328                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 329                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 330                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 331         } else {
 332         retpoline_generic:
 333                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 334                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 335                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 336         }
 337
 338         spectre_v2_enabled = mode;
 339         pr_info("%s\n", spectre_v2_strings[mode]);
 340
 341         pr_info("Speculation control IBPB %s IBRS %s",
 342                 ibpb_supported ? "supported" : "not-supported",
 343                 ibrs_supported ? "supported" : "not-supported");
 344
 345         /*
 346          * If we have a full retpoline mode and then disable IBPB in kernel mode
 347          * we do not require both.
 348          */
 349         if (mode == SPECTRE_V2_RETPOLINE_AMD ||
 350             mode == SPECTRE_V2_RETPOLINE_GENERIC)
 351         {
 352                 if (ibrs_supported) {
 353                         pr_info("Retpoline compiled kernel.  Defaulting IBRS to disabled");
 354                         set_ibrs_disabled();
 355                         if (!ibrs_inuse)
 356                                 sysctl_ibrs_enabled = 0;
 357                 }
 358         }
 359
 360         /*
 361          * If neither SMEP or KPTI are available, there is a risk of
 362          * hitting userspace addresses in the RSB after a context switch
 363          * from a shallow call stack to a deeper one. To prevent this fill
 364          * the entire RSB, even when using IBRS.
 365          *
 366          * Skylake era CPUs have a separate issue with *underflow* of the
 367          * RSB, when they will predict 'ret' targets from the generic BTB.
 368          * The proper mitigation for this is IBRS. If IBRS is not supported
 369          * or deactivated in favour of retpolines the RSB fill on context
 370          * switch is required.
 371          */
 372         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 373              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 374                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 375                 pr_info("Filling RSB on context switch\n");
 376         }
 377 }
 378
 379 #undef pr_fmt
 380 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 381
 382 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 383
 384 /* The kernel command line selection */
 385 enum ssb_mitigation_cmd {
 386         SPEC_STORE_BYPASS_CMD_NONE,
 387         SPEC_STORE_BYPASS_CMD_AUTO,
 388         SPEC_STORE_BYPASS_CMD_ON,
 389         SPEC_STORE_BYPASS_CMD_PRCTL,
 390         SPEC_STORE_BYPASS_CMD_SECCOMP,
 391 };
 392
 393 static const char *ssb_strings[] = {
 394         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 395         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 396         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 397         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 398 };
 399
 400 static const struct {
 401         const char *option;
 402         enum ssb_mitigation_cmd cmd;
 403 } ssb_mitigation_options[] = {
 404         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 405         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 406         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 407         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 408         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 409 };
 410
 411 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 412 {
 413         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 414         char arg[20];
 415         int ret, i;
 416
 417         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 418                 return SPEC_STORE_BYPASS_CMD_NONE;
 419         } else {
 420                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 421                                           arg, sizeof(arg));
 422                 if (ret < 0)
 423                         return SPEC_STORE_BYPASS_CMD_AUTO;
 424
 425                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 426                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 427                                 continue;
 428
 429                         cmd = ssb_mitigation_options[i].cmd;
 430                         break;
 431                 }
 432
 433                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 434                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 435                         return SPEC_STORE_BYPASS_CMD_AUTO;
 436                 }
 437         }
 438
 439         return cmd;
 440 }
 441
 442 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 443 {
 444         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 445         enum ssb_mitigation_cmd cmd;
 446
 447         if (!boot_cpu_has(X86_FEATURE_SSBD))
 448                 return mode;
 449
 450         cmd = ssb_parse_cmdline();
 451         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 452             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 453              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 454                 return mode;
 455
 456         switch (cmd) {
 457         case SPEC_STORE_BYPASS_CMD_AUTO:
 458         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 459                 /*
 460                  * Choose prctl+seccomp as the default mode if seccomp is
 461                  * enabled.
 462                  */
 463                 if (IS_ENABLED(CONFIG_SECCOMP))
 464                         mode = SPEC_STORE_BYPASS_SECCOMP;
 465                 else
 466                         mode = SPEC_STORE_BYPASS_PRCTL;
 467                 break;
 468         case SPEC_STORE_BYPASS_CMD_ON:
 469                 mode = SPEC_STORE_BYPASS_DISABLE;
 470                 break;
 471         case SPEC_STORE_BYPASS_CMD_PRCTL:
 472                 mode = SPEC_STORE_BYPASS_PRCTL;
 473                 break;
 474         case SPEC_STORE_BYPASS_CMD_NONE:
 475                 break;
 476         }
 477
 478         /*
 479          * We have three CPU feature flags that are in play here:
 480          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 481          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 482          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 483          */
 484         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 485                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 486                 /*
 487                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 488                  * a completely different MSR and bit dependent on family.
 489                  */
 490                 switch (boot_cpu_data.x86_vendor) {
 491                 case X86_VENDOR_INTEL:
 492                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 493                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 494                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 495                         break;
 496                 case X86_VENDOR_AMD:
 497                         x86_amd_ssb_disable();
 498                         break;
 499                 }
 500         }
 501
 502         return mode;
 503 }
 504
 505 static void ssb_select_mitigation(void)
 506 {
 507         ssb_mode = __ssb_select_mitigation();
 508
 509         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 510                 pr_info("%s\n", ssb_strings[ssb_mode]);
 511 }
 512
 513 #undef pr_fmt
 514 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 515
 516 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 517 {
 518         bool update;
 519
 520         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 521             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 522                 return -ENXIO;
 523
 524         switch (ctrl) {
 525         case PR_SPEC_ENABLE:
 526                 /* If speculation is force disabled, enable is not allowed */
 527                 if (task_spec_ssb_force_disable(task))
 528                         return -EPERM;
 529                 task_clear_spec_ssb_disable(task);
 530                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 531                 break;
 532         case PR_SPEC_DISABLE:
 533                 task_set_spec_ssb_disable(task);
 534                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 535                 break;
 536         case PR_SPEC_FORCE_DISABLE:
 537                 task_set_spec_ssb_disable(task);
 538                 task_set_spec_ssb_force_disable(task);
 539                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 540                 break;
 541         default:
 542                 return -ERANGE;
 543         }
 544
 545         /*
 546          * If being set on non-current task, delay setting the CPU
 547          * mitigation until it is next scheduled.
 548          */
 549         if (task == current && update)
 550                 speculative_store_bypass_update_current();
 551
 552         return 0;
 553 }
 554
 555 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 556                              unsigned long ctrl)
 557 {
 558         switch (which) {
 559         case PR_SPEC_STORE_BYPASS:
 560                 return ssb_prctl_set(task, ctrl);
 561         default:
 562                 return -ENODEV;
 563         }
 564 }
 565
 566 #ifdef CONFIG_SECCOMP
 567 void arch_seccomp_spec_mitigate(struct task_struct *task)
 568 {
 569         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 570                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 571 }
 572 #endif
 573
 574 static int ssb_prctl_get(struct task_struct *task)
 575 {
 576         switch (ssb_mode) {
 577         case SPEC_STORE_BYPASS_DISABLE:
 578                 return PR_SPEC_DISABLE;
 579         case SPEC_STORE_BYPASS_SECCOMP:
 580         case SPEC_STORE_BYPASS_PRCTL:
 581                 if (task_spec_ssb_force_disable(task))
 582                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 583                 if (task_spec_ssb_disable(task))
 584                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 585                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 586         default:
 587                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 588                         return PR_SPEC_ENABLE;
 589                 return PR_SPEC_NOT_AFFECTED;
 590         }
 591 }
 592
 593 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 594 {
 595         switch (which) {
 596         case PR_SPEC_STORE_BYPASS:
 597                 return ssb_prctl_get(task);
 598         default:
 599                 return -ENODEV;
 600         }
 601 }
 602
 603 void x86_spec_ctrl_setup_ap(void)
 604 {
 605         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 606                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 607
 608         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 609                 x86_amd_ssb_disable();
 610 }
 611
 612 #ifdef CONFIG_SYSFS
 613 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 614                                char *buf, unsigned int bug)
 615 {
 616         if (!boot_cpu_has_bug(bug))
 617                 return sprintf(buf, "Not affected\n");
 618
 619         switch (bug) {
 620         case X86_BUG_CPU_MELTDOWN:
 621                 if (boot_cpu_has(X86_FEATURE_PTI))
 622                         return sprintf(buf, "Mitigation: PTI\n");
 623                 break;
 624
 625         case X86_BUG_SPECTRE_V1:
 626                 if (osb_is_enabled)
 627                         return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");
 628
 629         case X86_BUG_SPECTRE_V2:
 630                 return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : "");
 631
 632         case X86_BUG_SPEC_STORE_BYPASS:
 633                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 634
 635         default:
 636                 break;
 637         }
 638
 639         return sprintf(buf, "Vulnerable\n");
 640 }
 641
 642 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
 643                           char *buf)
 644 {
 645         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 646 }
 647
 648 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
 649                             char *buf)
 650 {
 651         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 652 }
 653
 654 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
 655                             char *buf)
 656 {
 657         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 658 }
 659
 660 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 661 {
 662         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 663 }
 664 #endif