arch/x86/kernel/cpu/centaur.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <linux/sched.h>
   4 #include <linux/sched/clock.h>
   5
   6 #include <asm/cpufeature.h>
   7 #include <asm/e820/api.h>
   8 #include <asm/mtrr.h>
   9 #include <asm/msr.h>
  10
  11 #include "cpu.h"
  12
  13 #define ACE_PRESENT     (1 << 6)
  14 #define ACE_ENABLED     (1 << 7)
  15 #define ACE_FCR         (1 << 28)       /* MSR_VIA_FCR */
  16
  17 #define RNG_PRESENT     (1 << 2)
  18 #define RNG_ENABLED     (1 << 3)
  19 #define RNG_ENABLE      (1 << 6)        /* MSR_VIA_RNG */
  20
  21 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
  22 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
  23 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
  24 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
  25 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
  26 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
  27
  28 static void init_c3(struct cpuinfo_x86 *c)
  29 {
  30         u32  lo, hi;
  31
  32         /* Test for Centaur Extended Feature Flags presence */
  33         if (cpuid_eax(0xC0000000) >= 0xC0000001) {
  34                 u32 tmp = cpuid_edx(0xC0000001);
  35
  36                 /* enable ACE unit, if present and disabled */
  37                 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
  38                         rdmsr(MSR_VIA_FCR, lo, hi);
  39                         lo |= ACE_FCR;          /* enable ACE unit */
  40                         wrmsr(MSR_VIA_FCR, lo, hi);
  41                         pr_info("CPU: Enabled ACE h/w crypto\n");
  42                 }
  43
  44                 /* enable RNG unit, if present and disabled */
  45                 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
  46                         rdmsr(MSR_VIA_RNG, lo, hi);
  47                         lo |= RNG_ENABLE;       /* enable RNG unit */
  48                         wrmsr(MSR_VIA_RNG, lo, hi);
  49                         pr_info("CPU: Enabled h/w RNG\n");
  50                 }
  51
  52                 /* store Centaur Extended Feature Flags as
  53                  * word 5 of the CPU capability bit array
  54                  */
  55                 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
  56         }
  57 #ifdef CONFIG_X86_32
  58         /* Cyrix III family needs CX8 & PGE explicitly enabled. */
  59         if (c->x86_model >= 6 && c->x86_model <= 13) {
  60                 rdmsr(MSR_VIA_FCR, lo, hi);
  61                 lo |= (1<<1 | 1<<7);
  62                 wrmsr(MSR_VIA_FCR, lo, hi);
  63                 set_cpu_cap(c, X86_FEATURE_CX8);
  64         }
  65
  66         /* Before Nehemiah, the C3's had 3dNOW! */
  67         if (c->x86_model >= 6 && c->x86_model < 9)
  68                 set_cpu_cap(c, X86_FEATURE_3DNOW);
  69 #endif
  70         if (c->x86 == 0x6 && c->x86_model >= 0xf) {
  71                 c->x86_cache_alignment = c->x86_clflush_size * 2;
  72                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  73         }
  74
  75         cpu_detect_cache_sizes(c);
  76 }
  77
  78 enum {
  79                 ECX8            = 1<<1,
  80                 EIERRINT        = 1<<2,
  81                 DPM             = 1<<3,
  82                 DMCE            = 1<<4,
  83                 DSTPCLK         = 1<<5,
  84                 ELINEAR         = 1<<6,
  85                 DSMC            = 1<<7,
  86                 DTLOCK          = 1<<8,
  87                 EDCTLB          = 1<<8,
  88                 EMMX            = 1<<9,
  89                 DPDC            = 1<<11,
  90                 EBRPRED         = 1<<12,
  91                 DIC             = 1<<13,
  92                 DDC             = 1<<14,
  93                 DNA             = 1<<15,
  94                 ERETSTK         = 1<<16,
  95                 E2MMX           = 1<<19,
  96                 EAMD3D          = 1<<20,
  97 };
  98
  99 static void early_init_centaur(struct cpuinfo_x86 *c)
 100 {
 101         switch (c->x86) {
 102 #ifdef CONFIG_X86_32
 103         case 5:
 104                 /* Emulate MTRRs using Centaur's MCR. */
 105                 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
 106                 break;
 107 #endif
 108         case 6:
 109                 if (c->x86_model >= 0xf)
 110                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 111                 break;
 112         }
 113 #ifdef CONFIG_X86_64
 114         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 115 #endif
 116 }
 117
 118 static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
 119 {
 120         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 121
 122         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 123         msr_ctl = vmx_msr_high | vmx_msr_low;
 124
 125         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 126                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 127         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 128                 set_cpu_cap(c, X86_FEATURE_VNMI);
 129         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 130                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 131                       vmx_msr_low, vmx_msr_high);
 132                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 133                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 134                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 135                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 136                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 137                         set_cpu_cap(c, X86_FEATURE_EPT);
 138                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 139                         set_cpu_cap(c, X86_FEATURE_VPID);
 140         }
 141 }
 142
 143 static void init_centaur(struct cpuinfo_x86 *c)
 144 {
 145 #ifdef CONFIG_X86_32
 146         char *name;
 147         u32  fcr_set = 0;
 148         u32  fcr_clr = 0;
 149         u32  lo, hi, newlo;
 150         u32  aa, bb, cc, dd;
 151
 152         /*
 153          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 154          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 155          */
 156         clear_cpu_cap(c, 0*32+31);
 157 #endif
 158         early_init_centaur(c);
 159         init_intel_cacheinfo(c);
 160         detect_num_cpu_cores(c);
 161 #ifdef CONFIG_X86_32
 162         detect_ht(c);
 163 #endif
 164
 165         if (c->cpuid_level > 9) {
 166                 unsigned int eax = cpuid_eax(10);
 167
 168                 /*
 169                  * Check for version and the number of counters
 170                  * Version(eax[7:0]) can't be 0;
 171                  * Counters(eax[15:8]) should be greater than 1;
 172                  */
 173                 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
 174                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 175         }
 176
 177         switch (c->x86) {
 178 #ifdef CONFIG_X86_32
 179         case 5:
 180                 switch (c->x86_model) {
 181                 case 4:
 182                         name = "C6";
 183                         fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
 184                         fcr_clr = DPDC;
 185                         pr_notice("Disabling bugged TSC.\n");
 186                         clear_cpu_cap(c, X86_FEATURE_TSC);
 187                         break;
 188                 case 8:
 189                         switch (c->x86_stepping) {
 190                         default:
 191                         name = "2";
 192                                 break;
 193                         case 7 ... 9:
 194                                 name = "2A";
 195                                 break;
 196                         case 10 ... 15:
 197                                 name = "2B";
 198                                 break;
 199                         }
 200                         fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
 201                                   E2MMX|EAMD3D;
 202                         fcr_clr = DPDC;
 203                         break;
 204                 case 9:
 205                         name = "3";
 206                         fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
 207                                   E2MMX|EAMD3D;
 208                         fcr_clr = DPDC;
 209                         break;
 210                 default:
 211                         name = "??";
 212                 }
 213
 214                 rdmsr(MSR_IDT_FCR1, lo, hi);
 215                 newlo = (lo|fcr_set) & (~fcr_clr);
 216
 217                 if (newlo != lo) {
 218                         pr_info("Centaur FCR was 0x%X now 0x%X\n",
 219                                 lo, newlo);
 220                         wrmsr(MSR_IDT_FCR1, newlo, hi);
 221                 } else {
 222                         pr_info("Centaur FCR is 0x%X\n", lo);
 223                 }
 224                 /* Emulate MTRRs using Centaur's MCR. */
 225                 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
 226                 /* Report CX8 */
 227                 set_cpu_cap(c, X86_FEATURE_CX8);
 228                 /* Set 3DNow! on Winchip 2 and above. */
 229                 if (c->x86_model >= 8)
 230                         set_cpu_cap(c, X86_FEATURE_3DNOW);
 231                 /* See if we can find out some more. */
 232                 if (cpuid_eax(0x80000000) >= 0x80000005) {
 233                         /* Yes, we can. */
 234                         cpuid(0x80000005, &aa, &bb, &cc, &dd);
 235                         /* Add L1 data and code cache sizes. */
 236                         c->x86_cache_size = (cc>>24)+(dd>>24);
 237                 }
 238                 sprintf(c->x86_model_id, "WinChip %s", name);
 239                 break;
 240 #endif
 241         case 6:
 242                 init_c3(c);
 243                 break;
 244         }
 245 #ifdef CONFIG_X86_64
 246         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 247 #endif
 248
 249         if (cpu_has(c, X86_FEATURE_VMX))
 250                 centaur_detect_vmx_virtcap(c);
 251 }
 252
 253 #ifdef CONFIG_X86_32
 254 static unsigned int
 255 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 256 {
 257         /* VIA C3 CPUs (670-68F) need further shifting. */
 258         if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
 259                 size >>= 8;
 260
 261         /*
 262          * There's also an erratum in Nehemiah stepping 1, which
 263          * returns '65KB' instead of '64KB'
 264          *  - Note, it seems this may only be in engineering samples.
 265          */
 266         if ((c->x86 == 6) && (c->x86_model == 9) &&
 267                                 (c->x86_stepping == 1) && (size == 65))
 268                 size -= 1;
 269         return size;
 270 }
 271 #endif
 272
 273 static const struct cpu_dev centaur_cpu_dev = {
 274         .c_vendor       = "Centaur",
 275         .c_ident        = { "CentaurHauls" },
 276         .c_early_init   = early_init_centaur,
 277         .c_init         = init_centaur,
 278 #ifdef CONFIG_X86_32
 279         .legacy_cache_size = centaur_size_cache,
 280 #endif
 281         .c_x86_vendor   = X86_VENDOR_CENTAUR,
 282 };
 283
 284 cpu_dev_register(centaur_cpu_dev);