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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - arch/x86/kernel/cpu/centaur.c
1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/sched.h>
4 #include <linux/sched/clock.h>
7 #include <asm/cpufeature.h>
8 #include <asm/e820/api.h>
14 #define ACE_PRESENT (1 << 6)
15 #define ACE_ENABLED (1 << 7)
16 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
18 #define RNG_PRESENT (1 << 2)
19 #define RNG_ENABLED (1 << 3)
20 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
22 static void init_c3(struct cpuinfo_x86
*c
)
26 /* Test for Centaur Extended Feature Flags presence */
27 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
28 u32 tmp
= cpuid_edx(0xC0000001);
30 /* enable ACE unit, if present and disabled */
31 if ((tmp
& (ACE_PRESENT
| ACE_ENABLED
)) == ACE_PRESENT
) {
32 rdmsr(MSR_VIA_FCR
, lo
, hi
);
33 lo
|= ACE_FCR
; /* enable ACE unit */
34 wrmsr(MSR_VIA_FCR
, lo
, hi
);
35 pr_info("CPU: Enabled ACE h/w crypto\n");
38 /* enable RNG unit, if present and disabled */
39 if ((tmp
& (RNG_PRESENT
| RNG_ENABLED
)) == RNG_PRESENT
) {
40 rdmsr(MSR_VIA_RNG
, lo
, hi
);
41 lo
|= RNG_ENABLE
; /* enable RNG unit */
42 wrmsr(MSR_VIA_RNG
, lo
, hi
);
43 pr_info("CPU: Enabled h/w RNG\n");
46 /* store Centaur Extended Feature Flags as
47 * word 5 of the CPU capability bit array
49 c
->x86_capability
[CPUID_C000_0001_EDX
] = cpuid_edx(0xC0000001);
52 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
53 if (c
->x86_model
>= 6 && c
->x86_model
<= 13) {
54 rdmsr(MSR_VIA_FCR
, lo
, hi
);
56 wrmsr(MSR_VIA_FCR
, lo
, hi
);
57 set_cpu_cap(c
, X86_FEATURE_CX8
);
60 /* Before Nehemiah, the C3's had 3dNOW! */
61 if (c
->x86_model
>= 6 && c
->x86_model
< 9)
62 set_cpu_cap(c
, X86_FEATURE_3DNOW
);
64 if (c
->x86
== 0x6 && c
->x86_model
>= 0xf) {
65 c
->x86_cache_alignment
= c
->x86_clflush_size
* 2;
66 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
70 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
94 static void early_init_centaur(struct cpuinfo_x86
*c
)
97 /* Emulate MTRRs using Centaur's MCR. */
99 set_cpu_cap(c
, X86_FEATURE_CENTAUR_MCR
);
101 if ((c
->x86
== 6 && c
->x86_model
>= 0xf) ||
103 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
106 set_cpu_cap(c
, X86_FEATURE_SYSENTER32
);
108 if (c
->x86_power
& (1 << 8)) {
109 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
110 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
114 static void init_centaur(struct cpuinfo_x86
*c
)
124 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
125 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
127 clear_cpu_cap(c
, 0*32+31);
129 early_init_centaur(c
);
130 init_intel_cacheinfo(c
);
131 detect_num_cpu_cores(c
);
136 if (c
->cpuid_level
> 9) {
137 unsigned int eax
= cpuid_eax(10);
140 * Check for version and the number of counters
141 * Version(eax[7:0]) can't be 0;
142 * Counters(eax[15:8]) should be greater than 1;
144 if ((eax
& 0xff) && (((eax
>> 8) & 0xff) > 1))
145 set_cpu_cap(c
, X86_FEATURE_ARCH_PERFMON
);
150 switch (c
->x86_model
) {
153 fcr_set
= ECX8
|DSMC
|EDCTLB
|EMMX
|ERETSTK
;
155 pr_notice("Disabling bugged TSC.\n");
156 clear_cpu_cap(c
, X86_FEATURE_TSC
);
159 switch (c
->x86_stepping
) {
170 fcr_set
= ECX8
|DSMC
|DTLOCK
|EMMX
|EBRPRED
|ERETSTK
|
176 fcr_set
= ECX8
|DSMC
|DTLOCK
|EMMX
|EBRPRED
|ERETSTK
|
184 rdmsr(MSR_IDT_FCR1
, lo
, hi
);
185 newlo
= (lo
|fcr_set
) & (~fcr_clr
);
188 pr_info("Centaur FCR was 0x%X now 0x%X\n",
190 wrmsr(MSR_IDT_FCR1
, newlo
, hi
);
192 pr_info("Centaur FCR is 0x%X\n", lo
);
194 /* Emulate MTRRs using Centaur's MCR. */
195 set_cpu_cap(c
, X86_FEATURE_CENTAUR_MCR
);
197 set_cpu_cap(c
, X86_FEATURE_CX8
);
198 /* Set 3DNow! on Winchip 2 and above. */
199 if (c
->x86_model
>= 8)
200 set_cpu_cap(c
, X86_FEATURE_3DNOW
);
201 /* See if we can find out some more. */
202 if (cpuid_eax(0x80000000) >= 0x80000005) {
204 cpuid(0x80000005, &aa
, &bb
, &cc
, &dd
);
205 /* Add L1 data and code cache sizes. */
206 c
->x86_cache_size
= (cc
>>24)+(dd
>>24);
208 sprintf(c
->x86_model_id
, "WinChip %s", name
);
211 if (c
->x86
== 6 || c
->x86
>= 7)
214 set_cpu_cap(c
, X86_FEATURE_LFENCE_RDTSC
);
217 init_ia32_feat_ctl(c
);
222 centaur_size_cache(struct cpuinfo_x86
*c
, unsigned int size
)
224 /* VIA C3 CPUs (670-68F) need further shifting. */
225 if ((c
->x86
== 6) && ((c
->x86_model
== 7) || (c
->x86_model
== 8)))
229 * There's also an erratum in Nehemiah stepping 1, which
230 * returns '65KB' instead of '64KB'
231 * - Note, it seems this may only be in engineering samples.
233 if ((c
->x86
== 6) && (c
->x86_model
== 9) &&
234 (c
->x86_stepping
== 1) && (size
== 65))
240 static const struct cpu_dev centaur_cpu_dev
= {
241 .c_vendor
= "Centaur",
242 .c_ident
= { "CentaurHauls" },
243 .c_early_init
= early_init_centaur
,
244 .c_init
= init_centaur
,
246 .legacy_cache_size
= centaur_size_cache
,
248 .c_x86_vendor
= X86_VENDOR_CENTAUR
,
251 cpu_dev_register(centaur_cpu_dev
);