1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
25 #include <asm/cpumask.h>
26 #ifdef CONFIG_X86_LOCAL_APIC
27 #include <asm/mpspec.h>
29 #include <mach_apic.h>
30 #include <asm/genapic.h>
31 #include <asm/uv/uv.h>
34 #include <asm/pgtable.h>
35 #include <asm/processor.h>
37 #include <asm/atomic.h>
38 #include <asm/proto.h>
39 #include <asm/sections.h>
40 #include <asm/setup.h>
41 #include <asm/hypervisor.h>
42 #include <asm/stackprotector.h>
48 /* all of these masks are initialized in setup_cpu_local_masks() */
49 cpumask_var_t cpu_callin_mask
;
50 cpumask_var_t cpu_callout_mask
;
51 cpumask_var_t cpu_initialized_mask
;
53 /* representing cpus for which sibling maps can be computed */
54 cpumask_var_t cpu_sibling_setup_mask
;
56 /* correctly size the local cpu masks */
57 void __init
setup_cpu_local_masks(void)
59 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
60 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
61 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
62 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
65 #else /* CONFIG_X86_32 */
67 cpumask_t cpu_callin_map
;
68 cpumask_t cpu_callout_map
;
69 cpumask_t cpu_initialized
;
70 cpumask_t cpu_sibling_setup_map
;
72 #endif /* CONFIG_X86_32 */
75 static struct cpu_dev
*this_cpu __cpuinitdata
;
77 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
80 * We need valid kernel segments for data and code in long mode too
81 * IRET will check the segment types kkeil 2000/10/28
82 * Also sysret mandates a special GDT layout
84 * The TLS descriptors are currently at a different place compared to i386.
85 * Hopefully nobody expects them at a fixed place (Wine?)
87 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
88 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
89 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
90 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
91 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
92 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
94 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
95 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
96 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
97 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
99 * Segments used for calling PnP BIOS have byte granularity.
100 * They code segments and data segments have fixed 64k limits,
101 * the transfer segment sizes are set at run time.
104 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
106 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
108 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
110 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
112 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
114 * The APM segments have byte granularity and their bases
115 * are set at run time. All have 64k limits.
118 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
120 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
122 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
124 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
125 [GDT_ENTRY_PERCPU
] = { { { 0x0000ffff, 0x00cf9200 } } },
126 GDT_STACK_CANARY_INIT
129 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
132 static int cachesize_override __cpuinitdata
= -1;
133 static int disable_x86_serial_nr __cpuinitdata
= 1;
135 static int __init
cachesize_setup(char *str
)
137 get_option(&str
, &cachesize_override
);
140 __setup("cachesize=", cachesize_setup
);
142 static int __init
x86_fxsr_setup(char *s
)
144 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
145 setup_clear_cpu_cap(X86_FEATURE_XMM
);
148 __setup("nofxsr", x86_fxsr_setup
);
150 static int __init
x86_sep_setup(char *s
)
152 setup_clear_cpu_cap(X86_FEATURE_SEP
);
155 __setup("nosep", x86_sep_setup
);
157 /* Standard macro to see if a specific flag is changeable */
158 static inline int flag_is_changeable_p(u32 flag
)
163 * Cyrix and IDT cpus allow disabling of CPUID
164 * so the code below may return different results
165 * when it is executed before and after enabling
166 * the CPUID. Add "volatile" to not allow gcc to
167 * optimize the subsequent calls to this function.
169 asm volatile ("pushfl\n\t"
179 : "=&r" (f1
), "=&r" (f2
)
182 return ((f1
^f2
) & flag
) != 0;
185 /* Probe for the CPUID instruction */
186 static int __cpuinit
have_cpuid_p(void)
188 return flag_is_changeable_p(X86_EFLAGS_ID
);
191 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
193 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
194 /* Disable processor serial number */
195 unsigned long lo
, hi
;
196 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
198 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
199 printk(KERN_NOTICE
"CPU serial number disabled.\n");
200 clear_cpu_cap(c
, X86_FEATURE_PN
);
202 /* Disabling the serial number may affect the cpuid level */
203 c
->cpuid_level
= cpuid_eax(0);
207 static int __init
x86_serial_nr_setup(char *s
)
209 disable_x86_serial_nr
= 0;
212 __setup("serialnumber", x86_serial_nr_setup
);
214 static inline int flag_is_changeable_p(u32 flag
)
218 /* Probe for the CPUID instruction */
219 static inline int have_cpuid_p(void)
223 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
229 * Naming convention should be: <Name> [(<Codename>)]
230 * This table only is used unless init_<vendor>() below doesn't set it;
231 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
235 /* Look up CPU names by table lookup. */
236 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
238 struct cpu_model_info
*info
;
240 if (c
->x86_model
>= 16)
241 return NULL
; /* Range check */
246 info
= this_cpu
->c_models
;
248 while (info
&& info
->family
) {
249 if (info
->family
== c
->x86
)
250 return info
->model_names
[c
->x86_model
];
253 return NULL
; /* Not found */
256 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
258 void load_percpu_segment(int cpu
)
261 loadsegment(fs
, __KERNEL_PERCPU
);
264 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
266 load_stack_canary_segment();
269 /* Current gdt points %fs at the "master" per-cpu area: after this,
270 * it's on the real one. */
271 void switch_to_new_gdt(int cpu
)
273 struct desc_ptr gdt_descr
;
275 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
276 gdt_descr
.size
= GDT_SIZE
- 1;
277 load_gdt(&gdt_descr
);
278 /* Reload the per-cpu base */
280 load_percpu_segment(cpu
);
283 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
285 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
288 display_cacheinfo(c
);
290 /* Not much we can do here... */
291 /* Check if at least it has cpuid */
292 if (c
->cpuid_level
== -1) {
293 /* No cpuid. It must be an ancient CPU */
295 strcpy(c
->x86_model_id
, "486");
296 else if (c
->x86
== 3)
297 strcpy(c
->x86_model_id
, "386");
302 static struct cpu_dev __cpuinitdata default_cpu
= {
303 .c_init
= default_init
,
304 .c_vendor
= "Unknown",
305 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
308 static void __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
313 if (c
->extended_cpuid_level
< 0x80000004)
316 v
= (unsigned int *) c
->x86_model_id
;
317 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
318 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
319 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
320 c
->x86_model_id
[48] = 0;
322 /* Intel chips right-justify this string for some dumb reason;
323 undo that brain damage */
324 p
= q
= &c
->x86_model_id
[0];
330 while (q
<= &c
->x86_model_id
[48])
331 *q
++ = '\0'; /* Zero-pad the rest */
335 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
337 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
339 n
= c
->extended_cpuid_level
;
341 if (n
>= 0x80000005) {
342 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
343 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
344 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
345 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
347 /* On K8 L1 TLB is inclusive, so don't count it */
352 if (n
< 0x80000006) /* Some chips just has a large L1. */
355 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
359 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
361 /* do processor-specific cache resizing */
362 if (this_cpu
->c_size_cache
)
363 l2size
= this_cpu
->c_size_cache(c
, l2size
);
365 /* Allow user to override all this if necessary. */
366 if (cachesize_override
!= -1)
367 l2size
= cachesize_override
;
370 return; /* Again, no L2 cache is possible */
373 c
->x86_cache_size
= l2size
;
375 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
379 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
382 u32 eax
, ebx
, ecx
, edx
;
383 int index_msb
, core_bits
;
385 if (!cpu_has(c
, X86_FEATURE_HT
))
388 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
391 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
394 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
396 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
398 if (smp_num_siblings
== 1) {
399 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
400 } else if (smp_num_siblings
> 1) {
402 if (smp_num_siblings
> nr_cpu_ids
) {
403 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
405 smp_num_siblings
= 1;
409 index_msb
= get_count_order(smp_num_siblings
);
411 c
->phys_proc_id
= phys_pkg_id(index_msb
);
413 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
416 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
418 index_msb
= get_count_order(smp_num_siblings
);
420 core_bits
= get_count_order(c
->x86_max_cores
);
423 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
424 ((1 << core_bits
) - 1);
426 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
427 ((1 << core_bits
) - 1);
432 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
433 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
435 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
441 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
443 char *v
= c
->x86_vendor_id
;
447 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
451 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
452 (cpu_devs
[i
]->c_ident
[1] &&
453 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
454 this_cpu
= cpu_devs
[i
];
455 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
462 printk(KERN_ERR
"CPU: vendor_id '%s' unknown, using generic init.\n", v
);
463 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
466 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
467 this_cpu
= &default_cpu
;
470 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
472 /* Get vendor name */
473 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
474 (unsigned int *)&c
->x86_vendor_id
[0],
475 (unsigned int *)&c
->x86_vendor_id
[8],
476 (unsigned int *)&c
->x86_vendor_id
[4]);
479 /* Intel-defined flags: level 0x00000001 */
480 if (c
->cpuid_level
>= 0x00000001) {
481 u32 junk
, tfms
, cap0
, misc
;
482 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
483 c
->x86
= (tfms
>> 8) & 0xf;
484 c
->x86_model
= (tfms
>> 4) & 0xf;
485 c
->x86_mask
= tfms
& 0xf;
487 c
->x86
+= (tfms
>> 20) & 0xff;
489 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
490 if (cap0
& (1<<19)) {
491 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
492 c
->x86_cache_alignment
= c
->x86_clflush_size
;
497 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
502 /* Intel-defined flags: level 0x00000001 */
503 if (c
->cpuid_level
>= 0x00000001) {
504 u32 capability
, excap
;
505 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
506 c
->x86_capability
[0] = capability
;
507 c
->x86_capability
[4] = excap
;
510 /* AMD-defined flags: level 0x80000001 */
511 xlvl
= cpuid_eax(0x80000000);
512 c
->extended_cpuid_level
= xlvl
;
513 if ((xlvl
& 0xffff0000) == 0x80000000) {
514 if (xlvl
>= 0x80000001) {
515 c
->x86_capability
[1] = cpuid_edx(0x80000001);
516 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
521 if (c
->extended_cpuid_level
>= 0x80000008) {
522 u32 eax
= cpuid_eax(0x80000008);
524 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
525 c
->x86_phys_bits
= eax
& 0xff;
529 if (c
->extended_cpuid_level
>= 0x80000007)
530 c
->x86_power
= cpuid_edx(0x80000007);
534 static void __cpuinit
identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
540 * First of all, decide if this is a 486 or higher
541 * It's a 486 if we can modify the AC flag
543 if (flag_is_changeable_p(X86_EFLAGS_AC
))
548 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
549 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
550 c
->x86_vendor_id
[0] = 0;
551 cpu_devs
[i
]->c_identify(c
);
552 if (c
->x86_vendor_id
[0]) {
561 * Do minimum CPU detection early.
562 * Fields really needed: vendor, cpuid_level, family, model, mask,
564 * The others are not touched to avoid unwanted side effects.
566 * WARNING: this function is only called on the BP. Don't add code here
567 * that is supposed to run on all CPUs.
569 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
572 c
->x86_clflush_size
= 64;
574 c
->x86_clflush_size
= 32;
576 c
->x86_cache_alignment
= c
->x86_clflush_size
;
578 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
579 c
->extended_cpuid_level
= 0;
582 identify_cpu_without_cpuid(c
);
584 /* cyrix could have cpuid enabled via c_identify()*/
594 if (this_cpu
->c_early_init
)
595 this_cpu
->c_early_init(c
);
597 validate_pat_support(c
);
600 c
->cpu_index
= boot_cpu_id
;
604 void __init
early_cpu_init(void)
606 struct cpu_dev
**cdev
;
609 printk("KERNEL supported cpus:\n");
610 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
611 struct cpu_dev
*cpudev
= *cdev
;
614 if (count
>= X86_VENDOR_NUM
)
616 cpu_devs
[count
] = cpudev
;
619 for (j
= 0; j
< 2; j
++) {
620 if (!cpudev
->c_ident
[j
])
622 printk(" %s %s\n", cpudev
->c_vendor
,
627 early_identify_cpu(&boot_cpu_data
);
631 * The NOPL instruction is supposed to exist on all CPUs with
632 * family >= 6; unfortunately, that's not true in practice because
633 * of early VIA chips and (more importantly) broken virtualizers that
634 * are not easy to detect. In the latter case it doesn't even *fail*
635 * reliably, so probing for it doesn't even work. Disable it completely
636 * unless we can find a reliable way to detect all the broken cases.
638 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
640 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
643 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
645 c
->extended_cpuid_level
= 0;
648 identify_cpu_without_cpuid(c
);
650 /* cyrix could have cpuid enabled via c_identify()*/
660 if (c
->cpuid_level
>= 0x00000001) {
661 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
663 # ifdef CONFIG_X86_HT
664 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
666 c
->apicid
= c
->initial_apicid
;
671 c
->phys_proc_id
= c
->initial_apicid
;
675 get_model_name(c
); /* Default name */
677 init_scattered_cpuid_features(c
);
682 * This does the hard work of actually picking apart the CPU stuff...
684 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
688 c
->loops_per_jiffy
= loops_per_jiffy
;
689 c
->x86_cache_size
= -1;
690 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
691 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
692 c
->x86_vendor_id
[0] = '\0'; /* Unset */
693 c
->x86_model_id
[0] = '\0'; /* Unset */
694 c
->x86_max_cores
= 1;
695 c
->x86_coreid_bits
= 0;
697 c
->x86_clflush_size
= 64;
699 c
->cpuid_level
= -1; /* CPUID not detected */
700 c
->x86_clflush_size
= 32;
702 c
->x86_cache_alignment
= c
->x86_clflush_size
;
703 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
707 if (this_cpu
->c_identify
)
708 this_cpu
->c_identify(c
);
711 c
->apicid
= phys_pkg_id(0);
715 * Vendor-specific initialization. In this section we
716 * canonicalize the feature flags, meaning if there are
717 * features a certain CPU supports which CPUID doesn't
718 * tell us, CPUID claiming incorrect flags, or other bugs,
719 * we handle them here.
721 * At the end of this section, c->x86_capability better
722 * indicate the features this CPU genuinely supports!
724 if (this_cpu
->c_init
)
727 /* Disable the PN if appropriate */
728 squash_the_stupid_serial_number(c
);
731 * The vendor-specific functions might have changed features. Now
732 * we do "generic changes."
735 /* If the model name is still unset, do table lookup. */
736 if (!c
->x86_model_id
[0]) {
738 p
= table_lookup_model(c
);
740 strcpy(c
->x86_model_id
, p
);
743 sprintf(c
->x86_model_id
, "%02x/%02x",
744 c
->x86
, c
->x86_model
);
753 * On SMP, boot_cpu_data holds the common feature set between
754 * all CPUs; so make sure that we indicate which features are
755 * common between the CPUs. The first time this routine gets
756 * executed, c == &boot_cpu_data.
758 if (c
!= &boot_cpu_data
) {
759 /* AND the already accumulated flags with these */
760 for (i
= 0; i
< NCAPINTS
; i
++)
761 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
764 /* Clear all flags overriden by options */
765 for (i
= 0; i
< NCAPINTS
; i
++)
766 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
768 #ifdef CONFIG_X86_MCE
769 /* Init Machine Check Exception if available. */
773 select_idle_routine(c
);
775 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
776 numa_add_cpu(smp_processor_id());
781 static void vgetcpu_set_mode(void)
783 if (cpu_has(&boot_cpu_data
, X86_FEATURE_RDTSCP
))
784 vgetcpu_mode
= VGETCPU_RDTSCP
;
786 vgetcpu_mode
= VGETCPU_LSL
;
790 void __init
identify_boot_cpu(void)
792 identify_cpu(&boot_cpu_data
);
801 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
803 BUG_ON(c
== &boot_cpu_data
);
816 static struct msr_range msr_range_array
[] __cpuinitdata
= {
817 { 0x00000000, 0x00000418},
818 { 0xc0000000, 0xc000040b},
819 { 0xc0010000, 0xc0010142},
820 { 0xc0011000, 0xc001103b},
823 static void __cpuinit
print_cpu_msr(void)
828 unsigned index_min
, index_max
;
830 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
831 index_min
= msr_range_array
[i
].min
;
832 index_max
= msr_range_array
[i
].max
;
833 for (index
= index_min
; index
< index_max
; index
++) {
834 if (rdmsrl_amd_safe(index
, &val
))
836 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
841 static int show_msr __cpuinitdata
;
842 static __init
int setup_show_msr(char *arg
)
846 get_option(&arg
, &num
);
852 __setup("show_msr=", setup_show_msr
);
854 static __init
int setup_noclflush(char *arg
)
856 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
859 __setup("noclflush", setup_noclflush
);
861 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
865 if (c
->x86_vendor
< X86_VENDOR_NUM
)
866 vendor
= this_cpu
->c_vendor
;
867 else if (c
->cpuid_level
>= 0)
868 vendor
= c
->x86_vendor_id
;
870 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
871 printk(KERN_CONT
"%s ", vendor
);
873 if (c
->x86_model_id
[0])
874 printk(KERN_CONT
"%s", c
->x86_model_id
);
876 printk(KERN_CONT
"%d86", c
->x86
);
878 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
879 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
881 printk(KERN_CONT
"\n");
884 if (c
->cpu_index
< show_msr
)
892 static __init
int setup_disablecpuid(char *arg
)
895 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
896 setup_clear_cpu_cap(bit
);
901 __setup("clearcpuid=", setup_disablecpuid
);
904 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
906 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
907 irq_stack_union
) __aligned(PAGE_SIZE
);
908 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
909 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
- 64;
911 DEFINE_PER_CPU(unsigned long, kernel_stack
) =
912 (unsigned long)&init_thread_union
- KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
913 EXPORT_PER_CPU_SYMBOL(kernel_stack
);
915 DEFINE_PER_CPU(unsigned int, irq_count
) = -1;
917 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
918 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
])
919 __aligned(PAGE_SIZE
);
921 extern asmlinkage
void ignore_sysret(void);
923 /* May not be marked __init: used by software suspend */
924 void syscall_init(void)
927 * LSTAR and STAR live in a bit strange symbiosis.
928 * They both write to the same internal register. STAR allows to
929 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
931 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
932 wrmsrl(MSR_LSTAR
, system_call
);
933 wrmsrl(MSR_CSTAR
, ignore_sysret
);
935 #ifdef CONFIG_IA32_EMULATION
936 syscall32_cpu_init();
939 /* Flags to clear on syscall */
940 wrmsrl(MSR_SYSCALL_MASK
,
941 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
944 unsigned long kernel_eflags
;
947 * Copies of the original ist values from the tss are only accessed during
948 * debugging, no special alignment required.
950 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
954 #ifdef CONFIG_CC_STACKPROTECTOR
955 DEFINE_PER_CPU(unsigned long, stack_canary
);
958 /* Make sure %fs and %gs are initialized properly in idle threads */
959 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
961 memset(regs
, 0, sizeof(struct pt_regs
));
962 regs
->fs
= __KERNEL_PERCPU
;
963 regs
->gs
= __KERNEL_STACK_CANARY
;
969 * cpu_init() initializes state that is per-CPU. Some data is already
970 * initialized (naturally) in the bootstrap process, such as the GDT
971 * and IDT. We reload them nevertheless, this function acts as a
972 * 'CPU state barrier', nothing should get across.
973 * A lot of state is already set up in PDA init for 64 bit
976 void __cpuinit
cpu_init(void)
978 int cpu
= stack_smp_processor_id();
979 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
980 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
982 struct task_struct
*me
;
986 if (cpu
!= 0 && percpu_read(node_number
) == 0 &&
987 cpu_to_node(cpu
) != NUMA_NO_NODE
)
988 percpu_write(node_number
, cpu_to_node(cpu
));
993 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
))
994 panic("CPU#%d already initialized!\n", cpu
);
996 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
998 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1001 * Initialize the per-CPU GDT with the boot GDT,
1002 * and set up the GDT descriptor:
1005 switch_to_new_gdt(cpu
);
1008 load_idt((const struct desc_ptr
*)&idt_descr
);
1010 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1013 wrmsrl(MSR_FS_BASE
, 0);
1014 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1018 if (cpu
!= 0 && x2apic
)
1022 * set up and load the per-CPU TSS
1024 if (!orig_ist
->ist
[0]) {
1025 static const unsigned int sizes
[N_EXCEPTION_STACKS
] = {
1026 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1027 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1029 char *estacks
= per_cpu(exception_stacks
, cpu
);
1030 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1031 estacks
+= sizes
[v
];
1032 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1033 (unsigned long)estacks
;
1037 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1039 * <= is required because the CPU will access up to
1040 * 8 bits beyond the end of the IO permission bitmap.
1042 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1043 t
->io_bitmap
[i
] = ~0UL;
1045 atomic_inc(&init_mm
.mm_count
);
1046 me
->active_mm
= &init_mm
;
1049 enter_lazy_tlb(&init_mm
, me
);
1051 load_sp0(t
, ¤t
->thread
);
1052 set_tss_desc(cpu
, t
);
1054 load_LDT(&init_mm
.context
);
1058 * If the kgdb is connected no debug regs should be altered. This
1059 * is only applicable when KGDB and a KGDB I/O module are built
1060 * into the kernel and you are using early debugging with
1061 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1063 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
1064 arch_kgdb_ops
.correct_hw_break();
1068 * Clear all 6 debug registers:
1071 set_debugreg(0UL, 0);
1072 set_debugreg(0UL, 1);
1073 set_debugreg(0UL, 2);
1074 set_debugreg(0UL, 3);
1075 set_debugreg(0UL, 6);
1076 set_debugreg(0UL, 7);
1078 /* If the kgdb is connected no debug regs should be altered. */
1084 raw_local_save_flags(kernel_eflags
);
1092 void __cpuinit
cpu_init(void)
1094 int cpu
= smp_processor_id();
1095 struct task_struct
*curr
= current
;
1096 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1097 struct thread_struct
*thread
= &curr
->thread
;
1099 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
)) {
1100 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1101 for (;;) local_irq_enable();
1104 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1106 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1107 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1109 load_idt(&idt_descr
);
1110 switch_to_new_gdt(cpu
);
1113 * Set up and load the per-CPU TSS and LDT
1115 atomic_inc(&init_mm
.mm_count
);
1116 curr
->active_mm
= &init_mm
;
1119 enter_lazy_tlb(&init_mm
, curr
);
1121 load_sp0(t
, thread
);
1122 set_tss_desc(cpu
, t
);
1124 load_LDT(&init_mm
.context
);
1126 #ifdef CONFIG_DOUBLEFAULT
1127 /* Set up doublefault TSS pointer in the GDT */
1128 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1131 /* Clear all 6 debug registers: */
1140 * Force FPU initialization:
1143 current_thread_info()->status
= TS_XSAVE
;
1145 current_thread_info()->status
= 0;
1147 mxcsr_feature_mask_init();
1150 * Boot processor to setup the FP and extended state context info.
1152 if (smp_processor_id() == boot_cpu_id
)
1153 init_thread_xstate();