1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/init.h>
18 #include <linux/kprobes.h>
19 #include <linux/kgdb.h>
20 #include <linux/smp.h>
22 #include <linux/syscore_ops.h>
24 #include <asm/stackprotector.h>
25 #include <asm/perf_event.h>
26 #include <asm/mmu_context.h>
27 #include <asm/archrandom.h>
28 #include <asm/hypervisor.h>
29 #include <asm/processor.h>
30 #include <asm/tlbflush.h>
31 #include <asm/debugreg.h>
32 #include <asm/sections.h>
33 #include <asm/vsyscall.h>
34 #include <linux/topology.h>
35 #include <linux/cpumask.h>
36 #include <asm/pgtable.h>
37 #include <linux/atomic.h>
38 #include <asm/proto.h>
39 #include <asm/setup.h>
42 #include <asm/fpu/internal.h>
44 #include <asm/hwcap2.h>
45 #include <linux/numa.h>
52 #include <asm/microcode.h>
53 #include <asm/microcode_intel.h>
54 #include <asm/intel-family.h>
55 #include <asm/cpu_device_id.h>
56 #include <asm/uv/uv.h>
60 u32 elf_hwcap2 __read_mostly
;
62 /* all of these masks are initialized in setup_cpu_local_masks() */
63 cpumask_var_t cpu_initialized_mask
;
64 cpumask_var_t cpu_callout_mask
;
65 cpumask_var_t cpu_callin_mask
;
67 /* representing cpus for which sibling maps can be computed */
68 cpumask_var_t cpu_sibling_setup_mask
;
70 /* Number of siblings per CPU package */
71 int smp_num_siblings
= 1;
72 EXPORT_SYMBOL(smp_num_siblings
);
74 /* Last level cache ID of each logical CPU */
75 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
77 /* correctly size the local cpu masks */
78 void __init
setup_cpu_local_masks(void)
80 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
81 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
82 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
83 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
86 static void default_init(struct cpuinfo_x86
*c
)
89 cpu_detect_cache_sizes(c
);
91 /* Not much we can do here... */
92 /* Check if at least it has cpuid */
93 if (c
->cpuid_level
== -1) {
94 /* No cpuid. It must be an ancient CPU */
96 strcpy(c
->x86_model_id
, "486");
98 strcpy(c
->x86_model_id
, "386");
103 static const struct cpu_dev default_cpu
= {
104 .c_init
= default_init
,
105 .c_vendor
= "Unknown",
106 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
109 static const struct cpu_dev
*this_cpu
= &default_cpu
;
111 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
114 * We need valid kernel segments for data and code in long mode too
115 * IRET will check the segment types kkeil 2000/10/28
116 * Also sysret mandates a special GDT layout
118 * TLS descriptors are currently at a different place compared to i386.
119 * Hopefully nobody expects them at a fixed place (Wine?)
121 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
122 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
123 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
124 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
125 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
126 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
128 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
129 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
130 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
131 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
133 * Segments used for calling PnP BIOS have byte granularity.
134 * They code segments and data segments have fixed 64k limits,
135 * the transfer segment sizes are set at run time.
138 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
140 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
142 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
144 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
146 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
148 * The APM segments have byte granularity and their bases
149 * are set at run time. All have 64k limits.
152 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
154 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
156 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
158 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
159 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
160 GDT_STACK_CANARY_INIT
163 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
165 static int __init
x86_mpx_setup(char *s
)
167 /* require an exact match without trailing characters */
171 /* do not emit a message if the feature is not present */
172 if (!boot_cpu_has(X86_FEATURE_MPX
))
175 setup_clear_cpu_cap(X86_FEATURE_MPX
);
176 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
179 __setup("nompx", x86_mpx_setup
);
182 static int __init
x86_nopcid_setup(char *s
)
184 /* nopcid doesn't accept parameters */
188 /* do not emit a message if the feature is not present */
189 if (!boot_cpu_has(X86_FEATURE_PCID
))
192 setup_clear_cpu_cap(X86_FEATURE_PCID
);
193 pr_info("nopcid: PCID feature disabled\n");
196 early_param("nopcid", x86_nopcid_setup
);
199 static int __init
x86_noinvpcid_setup(char *s
)
201 /* noinvpcid doesn't accept parameters */
205 /* do not emit a message if the feature is not present */
206 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
209 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
210 pr_info("noinvpcid: INVPCID feature disabled\n");
213 early_param("noinvpcid", x86_noinvpcid_setup
);
216 static int cachesize_override
= -1;
217 static int disable_x86_serial_nr
= 1;
219 static int __init
cachesize_setup(char *str
)
221 get_option(&str
, &cachesize_override
);
224 __setup("cachesize=", cachesize_setup
);
226 static int __init
x86_sep_setup(char *s
)
228 setup_clear_cpu_cap(X86_FEATURE_SEP
);
231 __setup("nosep", x86_sep_setup
);
233 /* Standard macro to see if a specific flag is changeable */
234 static inline int flag_is_changeable_p(u32 flag
)
239 * Cyrix and IDT cpus allow disabling of CPUID
240 * so the code below may return different results
241 * when it is executed before and after enabling
242 * the CPUID. Add "volatile" to not allow gcc to
243 * optimize the subsequent calls to this function.
245 asm volatile ("pushfl \n\t"
256 : "=&r" (f1
), "=&r" (f2
)
259 return ((f1
^f2
) & flag
) != 0;
262 /* Probe for the CPUID instruction */
263 int have_cpuid_p(void)
265 return flag_is_changeable_p(X86_EFLAGS_ID
);
268 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
270 unsigned long lo
, hi
;
272 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
275 /* Disable processor serial number: */
277 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
279 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
281 pr_notice("CPU serial number disabled.\n");
282 clear_cpu_cap(c
, X86_FEATURE_PN
);
284 /* Disabling the serial number may affect the cpuid level */
285 c
->cpuid_level
= cpuid_eax(0);
288 static int __init
x86_serial_nr_setup(char *s
)
290 disable_x86_serial_nr
= 0;
293 __setup("serialnumber", x86_serial_nr_setup
);
295 static inline int flag_is_changeable_p(u32 flag
)
299 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
304 static __init
int setup_disable_smep(char *arg
)
306 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
307 /* Check for things that depend on SMEP being enabled: */
308 check_mpx_erratum(&boot_cpu_data
);
311 __setup("nosmep", setup_disable_smep
);
313 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
315 if (cpu_has(c
, X86_FEATURE_SMEP
))
316 cr4_set_bits(X86_CR4_SMEP
);
319 static __init
int setup_disable_smap(char *arg
)
321 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
324 __setup("nosmap", setup_disable_smap
);
326 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
328 unsigned long eflags
= native_save_fl();
330 /* This should have been cleared long ago */
331 BUG_ON(eflags
& X86_EFLAGS_AC
);
333 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
334 #ifdef CONFIG_X86_SMAP
335 cr4_set_bits(X86_CR4_SMAP
);
337 cr4_clear_bits(X86_CR4_SMAP
);
342 static __always_inline
void setup_umip(struct cpuinfo_x86
*c
)
344 /* Check the boot processor, plus build option for UMIP. */
345 if (!cpu_feature_enabled(X86_FEATURE_UMIP
))
348 /* Check the current processor's cpuid bits. */
349 if (!cpu_has(c
, X86_FEATURE_UMIP
))
352 cr4_set_bits(X86_CR4_UMIP
);
354 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
360 * Make sure UMIP is disabled in case it was enabled in a
361 * previous boot (e.g., via kexec).
363 cr4_clear_bits(X86_CR4_UMIP
);
366 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning
);
367 static unsigned long cr4_pinned_bits __ro_after_init
;
369 void native_write_cr0(unsigned long val
)
371 unsigned long bits_missing
= 0;
374 asm volatile("mov %0,%%cr0": "+r" (val
), "+m" (__force_order
));
376 if (static_branch_likely(&cr_pinning
)) {
377 if (unlikely((val
& X86_CR0_WP
) != X86_CR0_WP
)) {
378 bits_missing
= X86_CR0_WP
;
382 /* Warn after we've set the missing bits. */
383 WARN_ONCE(bits_missing
, "CR0 WP bit went missing!?\n");
386 EXPORT_SYMBOL(native_write_cr0
);
388 void native_write_cr4(unsigned long val
)
390 unsigned long bits_missing
= 0;
393 asm volatile("mov %0,%%cr4": "+r" (val
), "+m" (cr4_pinned_bits
));
395 if (static_branch_likely(&cr_pinning
)) {
396 if (unlikely((val
& cr4_pinned_bits
) != cr4_pinned_bits
)) {
397 bits_missing
= ~val
& cr4_pinned_bits
;
401 /* Warn after we've set the missing bits. */
402 WARN_ONCE(bits_missing
, "CR4 bits went missing: %lx!?\n",
406 EXPORT_SYMBOL(native_write_cr4
);
410 unsigned long cr4
= __read_cr4();
412 if (boot_cpu_has(X86_FEATURE_PCID
))
413 cr4
|= X86_CR4_PCIDE
;
414 if (static_branch_likely(&cr_pinning
))
415 cr4
|= cr4_pinned_bits
;
419 /* Initialize cr4 shadow for this CPU. */
420 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
424 * Once CPU feature detection is finished (and boot params have been
425 * parsed), record any of the sensitive CR bits that are set, and
428 static void __init
setup_cr_pinning(void)
432 mask
= (X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_UMIP
);
433 cr4_pinned_bits
= this_cpu_read(cpu_tlbstate
.cr4
) & mask
;
434 static_key_enable(&cr_pinning
.key
);
438 * Protection Keys are not available in 32-bit mode.
440 static bool pku_disabled
;
442 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
444 struct pkru_state
*pk
;
446 /* check the boot processor, plus compile options for PKU: */
447 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
449 /* checks the actual processor's cpuid bits: */
450 if (!cpu_has(c
, X86_FEATURE_PKU
))
455 cr4_set_bits(X86_CR4_PKE
);
456 pk
= get_xsave_addr(&init_fpstate
.xsave
, XFEATURE_PKRU
);
458 pk
->pkru
= init_pkru_value
;
460 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
461 * cpuid bit to be set. We need to ensure that we
462 * update that bit in this CPU's "cpu_info".
467 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
468 static __init
int setup_disable_pku(char *arg
)
471 * Do not clear the X86_FEATURE_PKU bit. All of the
472 * runtime checks are against OSPKE so clearing the
475 * This way, we will see "pku" in cpuinfo, but not
476 * "ospke", which is exactly what we want. It shows
477 * that the CPU has PKU, but the OS has not enabled it.
478 * This happens to be exactly how a system would look
479 * if we disabled the config option.
481 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
485 __setup("nopku", setup_disable_pku
);
486 #endif /* CONFIG_X86_64 */
489 * Some CPU features depend on higher CPUID levels, which may not always
490 * be available due to CPUID level capping or broken virtualization
491 * software. Add those features to this table to auto-disable them.
493 struct cpuid_dependent_feature
{
498 static const struct cpuid_dependent_feature
499 cpuid_dependent_features
[] = {
500 { X86_FEATURE_MWAIT
, 0x00000005 },
501 { X86_FEATURE_DCA
, 0x00000009 },
502 { X86_FEATURE_XSAVE
, 0x0000000d },
506 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
508 const struct cpuid_dependent_feature
*df
;
510 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
512 if (!cpu_has(c
, df
->feature
))
515 * Note: cpuid_level is set to -1 if unavailable, but
516 * extended_extended_level is set to 0 if unavailable
517 * and the legitimate extended levels are all negative
518 * when signed; hence the weird messing around with
521 if (!((s32
)df
->level
< 0 ?
522 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
523 (s32
)df
->level
> (s32
)c
->cpuid_level
))
526 clear_cpu_cap(c
, df
->feature
);
530 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
531 x86_cap_flag(df
->feature
), df
->level
);
536 * Naming convention should be: <Name> [(<Codename>)]
537 * This table only is used unless init_<vendor>() below doesn't set it;
538 * in particular, if CPUID levels 0x80000002..4 are supported, this
542 /* Look up CPU names by table lookup. */
543 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
546 const struct legacy_cpu_model_info
*info
;
548 if (c
->x86_model
>= 16)
549 return NULL
; /* Range check */
554 info
= this_cpu
->legacy_models
;
556 while (info
->family
) {
557 if (info
->family
== c
->x86
)
558 return info
->model_names
[c
->x86_model
];
562 return NULL
; /* Not found */
565 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
];
566 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
];
568 void load_percpu_segment(int cpu
)
571 loadsegment(fs
, __KERNEL_PERCPU
);
573 __loadsegment_simple(gs
, 0);
574 wrmsrl(MSR_GS_BASE
, cpu_kernelmode_gs_base(cpu
));
576 load_stack_canary_segment();
580 /* The 32-bit entry code needs to find cpu_entry_area. */
581 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
584 /* Load the original GDT from the per-cpu structure */
585 void load_direct_gdt(int cpu
)
587 struct desc_ptr gdt_descr
;
589 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
590 gdt_descr
.size
= GDT_SIZE
- 1;
591 load_gdt(&gdt_descr
);
593 EXPORT_SYMBOL_GPL(load_direct_gdt
);
595 /* Load a fixmap remapping of the per-cpu GDT */
596 void load_fixmap_gdt(int cpu
)
598 struct desc_ptr gdt_descr
;
600 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
601 gdt_descr
.size
= GDT_SIZE
- 1;
602 load_gdt(&gdt_descr
);
604 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
607 * Current gdt points %fs at the "master" per-cpu area: after this,
608 * it's on the real one.
610 void switch_to_new_gdt(int cpu
)
612 /* Load the original GDT */
613 load_direct_gdt(cpu
);
614 /* Reload the per-cpu base */
615 load_percpu_segment(cpu
);
618 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
620 static void get_model_name(struct cpuinfo_x86
*c
)
625 if (c
->extended_cpuid_level
< 0x80000004)
628 v
= (unsigned int *)c
->x86_model_id
;
629 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
630 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
631 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
632 c
->x86_model_id
[48] = 0;
634 /* Trim whitespace */
635 p
= q
= s
= &c
->x86_model_id
[0];
641 /* Note the last non-whitespace index */
651 void detect_num_cpu_cores(struct cpuinfo_x86
*c
)
653 unsigned int eax
, ebx
, ecx
, edx
;
655 c
->x86_max_cores
= 1;
656 if (!IS_ENABLED(CONFIG_SMP
) || c
->cpuid_level
< 4)
659 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
661 c
->x86_max_cores
= (eax
>> 26) + 1;
664 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
666 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
668 n
= c
->extended_cpuid_level
;
670 if (n
>= 0x80000005) {
671 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
672 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
674 /* On K8 L1 TLB is inclusive, so don't count it */
679 if (n
< 0x80000006) /* Some chips just has a large L1. */
682 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
686 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
688 /* do processor-specific cache resizing */
689 if (this_cpu
->legacy_cache_size
)
690 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
692 /* Allow user to override all this if necessary. */
693 if (cachesize_override
!= -1)
694 l2size
= cachesize_override
;
697 return; /* Again, no L2 cache is possible */
700 c
->x86_cache_size
= l2size
;
703 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
704 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
705 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
706 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
707 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
708 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
709 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
711 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
713 if (this_cpu
->c_detect_tlb
)
714 this_cpu
->c_detect_tlb(c
);
716 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
717 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
718 tlb_lli_4m
[ENTRIES
]);
720 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
721 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
722 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
725 int detect_ht_early(struct cpuinfo_x86
*c
)
728 u32 eax
, ebx
, ecx
, edx
;
730 if (!cpu_has(c
, X86_FEATURE_HT
))
733 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
736 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
739 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
741 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
742 if (smp_num_siblings
== 1)
743 pr_info_once("CPU0: Hyper-Threading is disabled\n");
748 void detect_ht(struct cpuinfo_x86
*c
)
751 int index_msb
, core_bits
;
753 if (detect_ht_early(c
) < 0)
756 index_msb
= get_count_order(smp_num_siblings
);
757 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
759 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
761 index_msb
= get_count_order(smp_num_siblings
);
763 core_bits
= get_count_order(c
->x86_max_cores
);
765 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
766 ((1 << core_bits
) - 1);
770 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
772 char *v
= c
->x86_vendor_id
;
775 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
779 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
780 (cpu_devs
[i
]->c_ident
[1] &&
781 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
783 this_cpu
= cpu_devs
[i
];
784 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
789 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
790 "CPU: Your system may be unstable.\n", v
);
792 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
793 this_cpu
= &default_cpu
;
796 void cpu_detect(struct cpuinfo_x86
*c
)
798 /* Get vendor name */
799 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
800 (unsigned int *)&c
->x86_vendor_id
[0],
801 (unsigned int *)&c
->x86_vendor_id
[8],
802 (unsigned int *)&c
->x86_vendor_id
[4]);
805 /* Intel-defined flags: level 0x00000001 */
806 if (c
->cpuid_level
>= 0x00000001) {
807 u32 junk
, tfms
, cap0
, misc
;
809 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
810 c
->x86
= x86_family(tfms
);
811 c
->x86_model
= x86_model(tfms
);
812 c
->x86_stepping
= x86_stepping(tfms
);
814 if (cap0
& (1<<19)) {
815 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
816 c
->x86_cache_alignment
= c
->x86_clflush_size
;
821 static void apply_forced_caps(struct cpuinfo_x86
*c
)
825 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
826 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
827 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
831 static void init_speculation_control(struct cpuinfo_x86
*c
)
834 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
835 * and they also have a different bit for STIBP support. Also,
836 * a hypervisor might have set the individual AMD bits even on
837 * Intel CPUs, for finer-grained selection of what's available.
839 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
840 set_cpu_cap(c
, X86_FEATURE_IBRS
);
841 set_cpu_cap(c
, X86_FEATURE_IBPB
);
842 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
845 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
846 set_cpu_cap(c
, X86_FEATURE_STIBP
);
848 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
849 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
850 set_cpu_cap(c
, X86_FEATURE_SSBD
);
852 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
853 set_cpu_cap(c
, X86_FEATURE_IBRS
);
854 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
857 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
858 set_cpu_cap(c
, X86_FEATURE_IBPB
);
860 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
861 set_cpu_cap(c
, X86_FEATURE_STIBP
);
862 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
865 if (cpu_has(c
, X86_FEATURE_AMD_SSBD
)) {
866 set_cpu_cap(c
, X86_FEATURE_SSBD
);
867 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
868 clear_cpu_cap(c
, X86_FEATURE_VIRT_SSBD
);
872 static void init_cqm(struct cpuinfo_x86
*c
)
874 if (!cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
875 c
->x86_cache_max_rmid
= -1;
876 c
->x86_cache_occ_scale
= -1;
880 /* will be overridden if occupancy monitoring exists */
881 c
->x86_cache_max_rmid
= cpuid_ebx(0xf);
883 if (cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
) ||
884 cpu_has(c
, X86_FEATURE_CQM_MBM_TOTAL
) ||
885 cpu_has(c
, X86_FEATURE_CQM_MBM_LOCAL
)) {
886 u32 eax
, ebx
, ecx
, edx
;
888 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
889 cpuid_count(0xf, 1, &eax
, &ebx
, &ecx
, &edx
);
891 c
->x86_cache_max_rmid
= ecx
;
892 c
->x86_cache_occ_scale
= ebx
;
896 void get_cpu_cap(struct cpuinfo_x86
*c
)
898 u32 eax
, ebx
, ecx
, edx
;
900 /* Intel-defined flags: level 0x00000001 */
901 if (c
->cpuid_level
>= 0x00000001) {
902 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
904 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
905 c
->x86_capability
[CPUID_1_EDX
] = edx
;
908 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
909 if (c
->cpuid_level
>= 0x00000006)
910 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
912 /* Additional Intel-defined flags: level 0x00000007 */
913 if (c
->cpuid_level
>= 0x00000007) {
914 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
915 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
916 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
917 c
->x86_capability
[CPUID_7_EDX
] = edx
;
919 /* Check valid sub-leaf index before accessing it */
921 cpuid_count(0x00000007, 1, &eax
, &ebx
, &ecx
, &edx
);
922 c
->x86_capability
[CPUID_7_1_EAX
] = eax
;
926 /* Extended state features: level 0x0000000d */
927 if (c
->cpuid_level
>= 0x0000000d) {
928 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
930 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
933 /* AMD-defined flags: level 0x80000001 */
934 eax
= cpuid_eax(0x80000000);
935 c
->extended_cpuid_level
= eax
;
937 if ((eax
& 0xffff0000) == 0x80000000) {
938 if (eax
>= 0x80000001) {
939 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
941 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
942 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
946 if (c
->extended_cpuid_level
>= 0x80000007) {
947 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
949 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
953 if (c
->extended_cpuid_level
>= 0x80000008) {
954 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
955 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
958 if (c
->extended_cpuid_level
>= 0x8000000a)
959 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
961 init_scattered_cpuid_features(c
);
962 init_speculation_control(c
);
966 * Clear/Set all flags overridden by options, after probe.
967 * This needs to happen each time we re-probe, which may happen
968 * several times during CPU initialization.
970 apply_forced_caps(c
);
973 void get_cpu_address_sizes(struct cpuinfo_x86
*c
)
975 u32 eax
, ebx
, ecx
, edx
;
977 if (c
->extended_cpuid_level
>= 0x80000008) {
978 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
980 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
981 c
->x86_phys_bits
= eax
& 0xff;
984 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
985 c
->x86_phys_bits
= 36;
987 c
->x86_cache_bits
= c
->x86_phys_bits
;
990 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
996 * First of all, decide if this is a 486 or higher
997 * It's a 486 if we can modify the AC flag
999 if (flag_is_changeable_p(X86_EFLAGS_AC
))
1004 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
1005 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
1006 c
->x86_vendor_id
[0] = 0;
1007 cpu_devs
[i
]->c_identify(c
);
1008 if (c
->x86_vendor_id
[0]) {
1016 #define NO_SPECULATION BIT(0)
1017 #define NO_MELTDOWN BIT(1)
1018 #define NO_SSB BIT(2)
1019 #define NO_L1TF BIT(3)
1020 #define NO_MDS BIT(4)
1021 #define MSBDS_ONLY BIT(5)
1022 #define NO_SWAPGS BIT(6)
1024 #define VULNWL(_vendor, _family, _model, _whitelist) \
1025 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
1027 #define VULNWL_INTEL(model, whitelist) \
1028 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1030 #define VULNWL_AMD(family, whitelist) \
1031 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1033 #define VULNWL_HYGON(family, whitelist) \
1034 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1036 static const __initconst
struct x86_cpu_id cpu_vuln_whitelist
[] = {
1037 VULNWL(ANY
, 4, X86_MODEL_ANY
, NO_SPECULATION
),
1038 VULNWL(CENTAUR
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1039 VULNWL(INTEL
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1040 VULNWL(NSC
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1042 /* Intel Family 6 */
1043 VULNWL_INTEL(ATOM_SALTWELL
, NO_SPECULATION
),
1044 VULNWL_INTEL(ATOM_SALTWELL_TABLET
, NO_SPECULATION
),
1045 VULNWL_INTEL(ATOM_SALTWELL_MID
, NO_SPECULATION
),
1046 VULNWL_INTEL(ATOM_BONNELL
, NO_SPECULATION
),
1047 VULNWL_INTEL(ATOM_BONNELL_MID
, NO_SPECULATION
),
1049 VULNWL_INTEL(ATOM_SILVERMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
),
1050 VULNWL_INTEL(ATOM_SILVERMONT_D
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
),
1051 VULNWL_INTEL(ATOM_SILVERMONT_MID
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
),
1052 VULNWL_INTEL(ATOM_AIRMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
),
1053 VULNWL_INTEL(XEON_PHI_KNL
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
),
1054 VULNWL_INTEL(XEON_PHI_KNM
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
),
1056 VULNWL_INTEL(CORE_YONAH
, NO_SSB
),
1058 VULNWL_INTEL(ATOM_AIRMONT_MID
, NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
),
1059 VULNWL_INTEL(ATOM_AIRMONT_NP
, NO_L1TF
| NO_SWAPGS
),
1061 VULNWL_INTEL(ATOM_GOLDMONT
, NO_MDS
| NO_L1TF
| NO_SWAPGS
),
1062 VULNWL_INTEL(ATOM_GOLDMONT_D
, NO_MDS
| NO_L1TF
| NO_SWAPGS
),
1063 VULNWL_INTEL(ATOM_GOLDMONT_PLUS
, NO_MDS
| NO_L1TF
| NO_SWAPGS
),
1066 * Technically, swapgs isn't serializing on AMD (despite it previously
1067 * being documented as such in the APM). But according to AMD, %gs is
1068 * updated non-speculatively, and the issuing of %gs-relative memory
1069 * operands will be blocked until the %gs update completes, which is
1070 * good enough for our purposes.
1073 /* AMD Family 0xf - 0x12 */
1074 VULNWL_AMD(0x0f, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
),
1075 VULNWL_AMD(0x10, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
),
1076 VULNWL_AMD(0x11, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
),
1077 VULNWL_AMD(0x12, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
),
1079 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1080 VULNWL_AMD(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
),
1081 VULNWL_HYGON(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
),
1085 static bool __init
cpu_matches(unsigned long which
)
1087 const struct x86_cpu_id
*m
= x86_match_cpu(cpu_vuln_whitelist
);
1089 return m
&& !!(m
->driver_data
& which
);
1092 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
1096 if (cpu_matches(NO_SPECULATION
))
1099 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
1100 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
1102 if (cpu_has(c
, X86_FEATURE_ARCH_CAPABILITIES
))
1103 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
1105 if (!cpu_matches(NO_SSB
) && !(ia32_cap
& ARCH_CAP_SSB_NO
) &&
1106 !cpu_has(c
, X86_FEATURE_AMD_SSB_NO
))
1107 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
1109 if (ia32_cap
& ARCH_CAP_IBRS_ALL
)
1110 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED
);
1112 if (!cpu_matches(NO_MDS
) && !(ia32_cap
& ARCH_CAP_MDS_NO
)) {
1113 setup_force_cpu_bug(X86_BUG_MDS
);
1114 if (cpu_matches(MSBDS_ONLY
))
1115 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY
);
1118 if (!cpu_matches(NO_SWAPGS
))
1119 setup_force_cpu_bug(X86_BUG_SWAPGS
);
1121 if (cpu_matches(NO_MELTDOWN
))
1124 /* Rogue Data Cache Load? No! */
1125 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
1128 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
1130 if (cpu_matches(NO_L1TF
))
1133 setup_force_cpu_bug(X86_BUG_L1TF
);
1137 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1138 * unfortunately, that's not true in practice because of early VIA
1139 * chips and (more importantly) broken virtualizers that are not easy
1140 * to detect. In the latter case it doesn't even *fail* reliably, so
1141 * probing for it doesn't even work. Disable it completely on 32-bit
1142 * unless we can find a reliable way to detect all the broken cases.
1143 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1145 static void detect_nopl(void)
1147 #ifdef CONFIG_X86_32
1148 setup_clear_cpu_cap(X86_FEATURE_NOPL
);
1150 setup_force_cpu_cap(X86_FEATURE_NOPL
);
1155 * Do minimum CPU detection early.
1156 * Fields really needed: vendor, cpuid_level, family, model, mask,
1158 * The others are not touched to avoid unwanted side effects.
1160 * WARNING: this function is only called on the boot CPU. Don't add code
1161 * here that is supposed to run on all CPUs.
1163 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
1165 #ifdef CONFIG_X86_64
1166 c
->x86_clflush_size
= 64;
1167 c
->x86_phys_bits
= 36;
1168 c
->x86_virt_bits
= 48;
1170 c
->x86_clflush_size
= 32;
1171 c
->x86_phys_bits
= 32;
1172 c
->x86_virt_bits
= 32;
1174 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1176 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1177 c
->extended_cpuid_level
= 0;
1179 if (!have_cpuid_p())
1180 identify_cpu_without_cpuid(c
);
1182 /* cyrix could have cpuid enabled via c_identify()*/
1183 if (have_cpuid_p()) {
1187 get_cpu_address_sizes(c
);
1188 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1190 if (this_cpu
->c_early_init
)
1191 this_cpu
->c_early_init(c
);
1194 filter_cpuid_features(c
, false);
1196 if (this_cpu
->c_bsp_init
)
1197 this_cpu
->c_bsp_init(c
);
1199 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1202 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1204 cpu_set_bug_bits(c
);
1206 fpu__init_system(c
);
1208 #ifdef CONFIG_X86_32
1210 * Regardless of whether PCID is enumerated, the SDM says
1211 * that it can't be enabled in 32-bit mode.
1213 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1217 * Later in the boot process pgtable_l5_enabled() relies on
1218 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1219 * enabled by this point we need to clear the feature bit to avoid
1220 * false-positives at the later stage.
1222 * pgtable_l5_enabled() can be false here for several reasons:
1223 * - 5-level paging is disabled compile-time;
1224 * - it's 32-bit kernel;
1225 * - machine doesn't support 5-level paging;
1226 * - user specified 'no5lvl' in kernel command line.
1228 if (!pgtable_l5_enabled())
1229 setup_clear_cpu_cap(X86_FEATURE_LA57
);
1234 void __init
early_cpu_init(void)
1236 const struct cpu_dev
*const *cdev
;
1239 #ifdef CONFIG_PROCESSOR_SELECT
1240 pr_info("KERNEL supported cpus:\n");
1243 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1244 const struct cpu_dev
*cpudev
= *cdev
;
1246 if (count
>= X86_VENDOR_NUM
)
1248 cpu_devs
[count
] = cpudev
;
1251 #ifdef CONFIG_PROCESSOR_SELECT
1255 for (j
= 0; j
< 2; j
++) {
1256 if (!cpudev
->c_ident
[j
])
1258 pr_info(" %s %s\n", cpudev
->c_vendor
,
1259 cpudev
->c_ident
[j
]);
1264 early_identify_cpu(&boot_cpu_data
);
1267 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
1269 #ifdef CONFIG_X86_64
1271 * Empirically, writing zero to a segment selector on AMD does
1272 * not clear the base, whereas writing zero to a segment
1273 * selector on Intel does clear the base. Intel's behavior
1274 * allows slightly faster context switches in the common case
1275 * where GS is unused by the prev and next threads.
1277 * Since neither vendor documents this anywhere that I can see,
1278 * detect it directly instead of hardcoding the choice by
1281 * I've designated AMD's behavior as the "bug" because it's
1282 * counterintuitive and less friendly.
1285 unsigned long old_base
, tmp
;
1286 rdmsrl(MSR_FS_BASE
, old_base
);
1287 wrmsrl(MSR_FS_BASE
, 1);
1289 rdmsrl(MSR_FS_BASE
, tmp
);
1291 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1292 wrmsrl(MSR_FS_BASE
, old_base
);
1296 static void generic_identify(struct cpuinfo_x86
*c
)
1298 c
->extended_cpuid_level
= 0;
1300 if (!have_cpuid_p())
1301 identify_cpu_without_cpuid(c
);
1303 /* cyrix could have cpuid enabled via c_identify()*/
1304 if (!have_cpuid_p())
1313 get_cpu_address_sizes(c
);
1315 if (c
->cpuid_level
>= 0x00000001) {
1316 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1317 #ifdef CONFIG_X86_32
1319 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1321 c
->apicid
= c
->initial_apicid
;
1324 c
->phys_proc_id
= c
->initial_apicid
;
1327 get_model_name(c
); /* Default name */
1329 detect_null_seg_behavior(c
);
1332 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1333 * systems that run Linux at CPL > 0 may or may not have the
1334 * issue, but, even if they have the issue, there's absolutely
1335 * nothing we can do about it because we can't use the real IRET
1338 * NB: For the time being, only 32-bit kernels support
1339 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1340 * whether to apply espfix using paravirt hooks. If any
1341 * non-paravirt system ever shows up that does *not* have the
1342 * ESPFIX issue, we can change this.
1344 #ifdef CONFIG_X86_32
1345 # ifdef CONFIG_PARAVIRT_XXL
1347 extern void native_iret(void);
1348 if (pv_ops
.cpu
.iret
== native_iret
)
1349 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1352 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1357 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
1360 * The heavy lifting of max_rmid and cache_occ_scale are handled
1361 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1362 * in case CQM bits really aren't there in this CPU.
1364 if (c
!= &boot_cpu_data
) {
1365 boot_cpu_data
.x86_cache_max_rmid
=
1366 min(boot_cpu_data
.x86_cache_max_rmid
,
1367 c
->x86_cache_max_rmid
);
1372 * Validate that ACPI/mptables have the same information about the
1373 * effective APIC id and update the package map.
1375 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1378 unsigned int apicid
, cpu
= smp_processor_id();
1380 apicid
= apic
->cpu_present_to_apicid(cpu
);
1382 if (apicid
!= c
->apicid
) {
1383 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1384 cpu
, apicid
, c
->initial_apicid
);
1386 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1387 BUG_ON(topology_update_die_map(c
->cpu_die_id
, cpu
));
1389 c
->logical_proc_id
= 0;
1394 * This does the hard work of actually picking apart the CPU stuff...
1396 static void identify_cpu(struct cpuinfo_x86
*c
)
1400 c
->loops_per_jiffy
= loops_per_jiffy
;
1401 c
->x86_cache_size
= 0;
1402 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1403 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1404 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1405 c
->x86_model_id
[0] = '\0'; /* Unset */
1406 c
->x86_max_cores
= 1;
1407 c
->x86_coreid_bits
= 0;
1409 #ifdef CONFIG_X86_64
1410 c
->x86_clflush_size
= 64;
1411 c
->x86_phys_bits
= 36;
1412 c
->x86_virt_bits
= 48;
1414 c
->cpuid_level
= -1; /* CPUID not detected */
1415 c
->x86_clflush_size
= 32;
1416 c
->x86_phys_bits
= 32;
1417 c
->x86_virt_bits
= 32;
1419 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1420 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1422 generic_identify(c
);
1424 if (this_cpu
->c_identify
)
1425 this_cpu
->c_identify(c
);
1427 /* Clear/Set all flags overridden by options, after probe */
1428 apply_forced_caps(c
);
1430 #ifdef CONFIG_X86_64
1431 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1435 * Vendor-specific initialization. In this section we
1436 * canonicalize the feature flags, meaning if there are
1437 * features a certain CPU supports which CPUID doesn't
1438 * tell us, CPUID claiming incorrect flags, or other bugs,
1439 * we handle them here.
1441 * At the end of this section, c->x86_capability better
1442 * indicate the features this CPU genuinely supports!
1444 if (this_cpu
->c_init
)
1445 this_cpu
->c_init(c
);
1447 /* Disable the PN if appropriate */
1448 squash_the_stupid_serial_number(c
);
1450 /* Set up SMEP/SMAP/UMIP */
1456 * The vendor-specific functions might have changed features.
1457 * Now we do "generic changes."
1460 /* Filter out anything that depends on CPUID levels we don't have */
1461 filter_cpuid_features(c
, true);
1463 /* If the model name is still unset, do table lookup. */
1464 if (!c
->x86_model_id
[0]) {
1466 p
= table_lookup_model(c
);
1468 strcpy(c
->x86_model_id
, p
);
1470 /* Last resort... */
1471 sprintf(c
->x86_model_id
, "%02x/%02x",
1472 c
->x86
, c
->x86_model
);
1475 #ifdef CONFIG_X86_64
1480 x86_init_cache_qos(c
);
1484 * Clear/Set all flags overridden by options, need do it
1485 * before following smp all cpus cap AND.
1487 apply_forced_caps(c
);
1490 * On SMP, boot_cpu_data holds the common feature set between
1491 * all CPUs; so make sure that we indicate which features are
1492 * common between the CPUs. The first time this routine gets
1493 * executed, c == &boot_cpu_data.
1495 if (c
!= &boot_cpu_data
) {
1496 /* AND the already accumulated flags with these */
1497 for (i
= 0; i
< NCAPINTS
; i
++)
1498 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1500 /* OR, i.e. replicate the bug flags */
1501 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1502 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1505 /* Init Machine Check Exception if available. */
1508 select_idle_routine(c
);
1511 numa_add_cpu(smp_processor_id());
1516 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1517 * on 32-bit kernels:
1519 #ifdef CONFIG_X86_32
1520 void enable_sep_cpu(void)
1522 struct tss_struct
*tss
;
1525 if (!boot_cpu_has(X86_FEATURE_SEP
))
1529 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1532 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1533 * see the big comment in struct x86_hw_tss's definition.
1536 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1537 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1538 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1539 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1545 void __init
identify_boot_cpu(void)
1547 identify_cpu(&boot_cpu_data
);
1548 #ifdef CONFIG_X86_32
1552 cpu_detect_tlb(&boot_cpu_data
);
1556 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1558 BUG_ON(c
== &boot_cpu_data
);
1560 #ifdef CONFIG_X86_32
1564 validate_apic_and_package_id(c
);
1565 x86_spec_ctrl_setup_ap();
1568 static __init
int setup_noclflush(char *arg
)
1570 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1571 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1574 __setup("noclflush", setup_noclflush
);
1576 void print_cpu_info(struct cpuinfo_x86
*c
)
1578 const char *vendor
= NULL
;
1580 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1581 vendor
= this_cpu
->c_vendor
;
1583 if (c
->cpuid_level
>= 0)
1584 vendor
= c
->x86_vendor_id
;
1587 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1588 pr_cont("%s ", vendor
);
1590 if (c
->x86_model_id
[0])
1591 pr_cont("%s", c
->x86_model_id
);
1593 pr_cont("%d86", c
->x86
);
1595 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1597 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
1598 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
1604 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1605 * But we need to keep a dummy __setup around otherwise it would
1606 * show up as an environment variable for init.
1608 static __init
int setup_clearcpuid(char *arg
)
1612 __setup("clearcpuid=", setup_clearcpuid
);
1614 #ifdef CONFIG_X86_64
1615 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data
,
1616 fixed_percpu_data
) __aligned(PAGE_SIZE
) __visible
;
1617 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data
);
1620 * The following percpu variables are hot. Align current_task to
1621 * cacheline size such that they fall in the same cacheline.
1623 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1625 EXPORT_PER_CPU_SYMBOL(current_task
);
1627 DEFINE_PER_CPU(struct irq_stack
*, hardirq_stack_ptr
);
1628 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1630 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1631 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1633 /* May not be marked __init: used by software suspend */
1634 void syscall_init(void)
1636 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1637 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1639 #ifdef CONFIG_IA32_EMULATION
1640 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1642 * This only works on Intel CPUs.
1643 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1644 * This does not cause SYSENTER to jump to the wrong location, because
1645 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1647 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1648 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
,
1649 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1650 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1652 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1653 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1654 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1655 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1658 /* Flags to clear on syscall */
1659 wrmsrl(MSR_SYSCALL_MASK
,
1660 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1661 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1664 DEFINE_PER_CPU(int, debug_stack_usage
);
1665 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1667 void debug_stack_set_zero(void)
1669 this_cpu_inc(debug_idt_ctr
);
1672 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1674 void debug_stack_reset(void)
1676 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1678 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1681 NOKPROBE_SYMBOL(debug_stack_reset
);
1683 #else /* CONFIG_X86_64 */
1685 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1686 EXPORT_PER_CPU_SYMBOL(current_task
);
1687 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1688 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1691 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1692 * the top of the kernel stack. Use an extra percpu variable to track the
1693 * top of the kernel stack directly.
1695 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1696 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1697 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1699 #ifdef CONFIG_STACKPROTECTOR
1700 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1703 #endif /* CONFIG_X86_64 */
1706 * Clear all 6 debug registers:
1708 static void clear_all_debug_regs(void)
1712 for (i
= 0; i
< 8; i
++) {
1713 /* Ignore db4, db5 */
1714 if ((i
== 4) || (i
== 5))
1723 * Restore debug regs if using kgdbwait and you have a kernel debugger
1724 * connection established.
1726 static void dbg_restore_debug_regs(void)
1728 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1729 arch_kgdb_ops
.correct_hw_break();
1731 #else /* ! CONFIG_KGDB */
1732 #define dbg_restore_debug_regs()
1733 #endif /* ! CONFIG_KGDB */
1735 static void wait_for_master_cpu(int cpu
)
1739 * wait for ACK from master CPU before continuing
1740 * with AP initialization
1742 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1743 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1748 #ifdef CONFIG_X86_64
1749 static inline void setup_getcpu(int cpu
)
1751 unsigned long cpudata
= vdso_encode_cpunode(cpu
, early_cpu_to_node(cpu
));
1752 struct desc_struct d
= { };
1754 if (boot_cpu_has(X86_FEATURE_RDTSCP
))
1755 write_rdtscp_aux(cpudata
);
1757 /* Store CPU and node number in limit. */
1759 d
.limit1
= cpudata
>> 16;
1761 d
.type
= 5; /* RO data, expand down, accessed */
1762 d
.dpl
= 3; /* Visible to user code */
1763 d
.s
= 1; /* Not a system segment */
1764 d
.p
= 1; /* Present */
1765 d
.d
= 1; /* 32-bit */
1767 write_gdt_entry(get_cpu_gdt_rw(cpu
), GDT_ENTRY_CPUNODE
, &d
, DESCTYPE_S
);
1770 static inline void ucode_cpu_init(int cpu
)
1776 static inline void tss_setup_ist(struct tss_struct
*tss
)
1778 /* Set up the per-CPU TSS IST stacks */
1779 tss
->x86_tss
.ist
[IST_INDEX_DF
] = __this_cpu_ist_top_va(DF
);
1780 tss
->x86_tss
.ist
[IST_INDEX_NMI
] = __this_cpu_ist_top_va(NMI
);
1781 tss
->x86_tss
.ist
[IST_INDEX_DB
] = __this_cpu_ist_top_va(DB
);
1782 tss
->x86_tss
.ist
[IST_INDEX_MCE
] = __this_cpu_ist_top_va(MCE
);
1785 static inline void gdt_setup_doublefault_tss(int cpu
) { }
1787 #else /* CONFIG_X86_64 */
1789 static inline void setup_getcpu(int cpu
) { }
1791 static inline void ucode_cpu_init(int cpu
)
1793 show_ucode_info_early();
1796 static inline void tss_setup_ist(struct tss_struct
*tss
) { }
1798 static inline void gdt_setup_doublefault_tss(int cpu
)
1800 #ifdef CONFIG_DOUBLEFAULT
1801 /* Set up the doublefault TSS pointer in the GDT */
1802 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1805 #endif /* !CONFIG_X86_64 */
1808 * cpu_init() initializes state that is per-CPU. Some data is already
1809 * initialized (naturally) in the bootstrap process, such as the GDT
1810 * and IDT. We reload them nevertheless, this function acts as a
1811 * 'CPU state barrier', nothing should get across.
1815 struct tss_struct
*tss
= this_cpu_ptr(&cpu_tss_rw
);
1816 struct task_struct
*cur
= current
;
1817 int cpu
= raw_smp_processor_id();
1819 wait_for_master_cpu(cpu
);
1821 ucode_cpu_init(cpu
);
1824 if (this_cpu_read(numa_node
) == 0 &&
1825 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1826 set_numa_node(early_cpu_to_node(cpu
));
1830 pr_debug("Initializing CPU#%d\n", cpu
);
1832 if (IS_ENABLED(CONFIG_X86_64
) || cpu_feature_enabled(X86_FEATURE_VME
) ||
1833 boot_cpu_has(X86_FEATURE_TSC
) || boot_cpu_has(X86_FEATURE_DE
))
1834 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1837 * Initialize the per-CPU GDT with the boot GDT,
1838 * and set up the GDT descriptor:
1840 switch_to_new_gdt(cpu
);
1843 if (IS_ENABLED(CONFIG_X86_64
)) {
1845 memset(cur
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1848 wrmsrl(MSR_FS_BASE
, 0);
1849 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1856 cur
->active_mm
= &init_mm
;
1858 initialize_tlbstate_and_flush();
1859 enter_lazy_tlb(&init_mm
, cur
);
1861 /* Initialize the TSS. */
1863 tss
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET_INVALID
;
1864 tss
->io_bitmap
.prev_max
= 0;
1865 tss
->io_bitmap
.prev_sequence
= 0;
1866 memset(tss
->io_bitmap
.bitmap
, 0xff, sizeof(tss
->io_bitmap
.bitmap
));
1868 * Invalidate the extra array entry past the end of the all
1869 * permission bitmap as required by the hardware.
1871 tss
->io_bitmap
.mapall
[IO_BITMAP_LONGS
] = ~0UL;
1872 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1876 * sp0 points to the entry trampoline stack regardless of what task
1879 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
1881 load_mm_ldt(&init_mm
);
1883 clear_all_debug_regs();
1884 dbg_restore_debug_regs();
1886 gdt_setup_doublefault_tss(cpu
);
1893 load_fixmap_gdt(cpu
);
1897 * The microcode loader calls this upon late microcode load to recheck features,
1898 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1901 void microcode_check(void)
1903 struct cpuinfo_x86 info
;
1905 perf_check_microcode();
1907 /* Reload CPUID max function as it might've changed. */
1908 info
.cpuid_level
= cpuid_eax(0);
1911 * Copy all capability leafs to pick up the synthetic ones so that
1912 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1913 * get overwritten in get_cpu_cap().
1915 memcpy(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
));
1919 if (!memcmp(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
)))
1922 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1923 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1927 * Invoked from core CPU hotplug code after hotplug operations
1929 void arch_smt_update(void)
1931 /* Handle the speculative execution misfeatures */
1932 cpu_bugs_smt_update();
1933 /* Check whether IPI broadcasting can be enabled */