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1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
15 #include <linux/io.h>
16 #include <linux/syscore_ops.h>
17
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
34 #include <asm/apic.h>
35 #include <asm/desc.h>
36 #include <asm/fpu/internal.h>
37 #include <asm/mtrr.h>
38 #include <linux/numa.h>
39 #include <asm/asm.h>
40 #include <asm/bugs.h>
41 #include <asm/cpu.h>
42 #include <asm/mce.h>
43 #include <asm/msr.h>
44 #include <asm/pat.h>
45 #include <asm/microcode.h>
46 #include <asm/microcode_intel.h>
47
48 #ifdef CONFIG_X86_LOCAL_APIC
49 #include <asm/uv/uv.h>
50 #endif
51
52 #include "cpu.h"
53
54 /* all of these masks are initialized in setup_cpu_local_masks() */
55 cpumask_var_t cpu_initialized_mask;
56 cpumask_var_t cpu_callout_mask;
57 cpumask_var_t cpu_callin_mask;
58
59 /* representing cpus for which sibling maps can be computed */
60 cpumask_var_t cpu_sibling_setup_mask;
61
62 /* correctly size the local cpu masks */
63 void __init setup_cpu_local_masks(void)
64 {
65 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
66 alloc_bootmem_cpumask_var(&cpu_callin_mask);
67 alloc_bootmem_cpumask_var(&cpu_callout_mask);
68 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
69 }
70
71 static void default_init(struct cpuinfo_x86 *c)
72 {
73 #ifdef CONFIG_X86_64
74 cpu_detect_cache_sizes(c);
75 #else
76 /* Not much we can do here... */
77 /* Check if at least it has cpuid */
78 if (c->cpuid_level == -1) {
79 /* No cpuid. It must be an ancient CPU */
80 if (c->x86 == 4)
81 strcpy(c->x86_model_id, "486");
82 else if (c->x86 == 3)
83 strcpy(c->x86_model_id, "386");
84 }
85 #endif
86 }
87
88 static const struct cpu_dev default_cpu = {
89 .c_init = default_init,
90 .c_vendor = "Unknown",
91 .c_x86_vendor = X86_VENDOR_UNKNOWN,
92 };
93
94 static const struct cpu_dev *this_cpu = &default_cpu;
95
96 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
97 #ifdef CONFIG_X86_64
98 /*
99 * We need valid kernel segments for data and code in long mode too
100 * IRET will check the segment types kkeil 2000/10/28
101 * Also sysret mandates a special GDT layout
102 *
103 * TLS descriptors are currently at a different place compared to i386.
104 * Hopefully nobody expects them at a fixed place (Wine?)
105 */
106 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
108 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
112 #else
113 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
117 /*
118 * Segments used for calling PnP BIOS have byte granularity.
119 * They code segments and data segments have fixed 64k limits,
120 * the transfer segment sizes are set at run time.
121 */
122 /* 32-bit code */
123 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
124 /* 16-bit code */
125 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
126 /* 16-bit data */
127 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
128 /* 16-bit data */
129 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
130 /* 16-bit data */
131 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 /*
133 * The APM segments have byte granularity and their bases
134 * are set at run time. All have 64k limits.
135 */
136 /* 32-bit code */
137 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
138 /* 16-bit code */
139 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
140 /* data */
141 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
142
143 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
145 GDT_STACK_CANARY_INIT
146 #endif
147 } };
148 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
149
150 static int __init x86_mpx_setup(char *s)
151 {
152 /* require an exact match without trailing characters */
153 if (strlen(s))
154 return 0;
155
156 /* do not emit a message if the feature is not present */
157 if (!boot_cpu_has(X86_FEATURE_MPX))
158 return 1;
159
160 setup_clear_cpu_cap(X86_FEATURE_MPX);
161 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
162 return 1;
163 }
164 __setup("nompx", x86_mpx_setup);
165
166 static int __init x86_noinvpcid_setup(char *s)
167 {
168 /* noinvpcid doesn't accept parameters */
169 if (s)
170 return -EINVAL;
171
172 /* do not emit a message if the feature is not present */
173 if (!boot_cpu_has(X86_FEATURE_INVPCID))
174 return 0;
175
176 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
177 pr_info("noinvpcid: INVPCID feature disabled\n");
178 return 0;
179 }
180 early_param("noinvpcid", x86_noinvpcid_setup);
181
182 #ifdef CONFIG_X86_32
183 static int cachesize_override = -1;
184 static int disable_x86_serial_nr = 1;
185
186 static int __init cachesize_setup(char *str)
187 {
188 get_option(&str, &cachesize_override);
189 return 1;
190 }
191 __setup("cachesize=", cachesize_setup);
192
193 static int __init x86_sep_setup(char *s)
194 {
195 setup_clear_cpu_cap(X86_FEATURE_SEP);
196 return 1;
197 }
198 __setup("nosep", x86_sep_setup);
199
200 /* Standard macro to see if a specific flag is changeable */
201 static inline int flag_is_changeable_p(u32 flag)
202 {
203 u32 f1, f2;
204
205 /*
206 * Cyrix and IDT cpus allow disabling of CPUID
207 * so the code below may return different results
208 * when it is executed before and after enabling
209 * the CPUID. Add "volatile" to not allow gcc to
210 * optimize the subsequent calls to this function.
211 */
212 asm volatile ("pushfl \n\t"
213 "pushfl \n\t"
214 "popl %0 \n\t"
215 "movl %0, %1 \n\t"
216 "xorl %2, %0 \n\t"
217 "pushl %0 \n\t"
218 "popfl \n\t"
219 "pushfl \n\t"
220 "popl %0 \n\t"
221 "popfl \n\t"
222
223 : "=&r" (f1), "=&r" (f2)
224 : "ir" (flag));
225
226 return ((f1^f2) & flag) != 0;
227 }
228
229 /* Probe for the CPUID instruction */
230 int have_cpuid_p(void)
231 {
232 return flag_is_changeable_p(X86_EFLAGS_ID);
233 }
234
235 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
236 {
237 unsigned long lo, hi;
238
239 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
240 return;
241
242 /* Disable processor serial number: */
243
244 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
245 lo |= 0x200000;
246 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
247
248 pr_notice("CPU serial number disabled.\n");
249 clear_cpu_cap(c, X86_FEATURE_PN);
250
251 /* Disabling the serial number may affect the cpuid level */
252 c->cpuid_level = cpuid_eax(0);
253 }
254
255 static int __init x86_serial_nr_setup(char *s)
256 {
257 disable_x86_serial_nr = 0;
258 return 1;
259 }
260 __setup("serialnumber", x86_serial_nr_setup);
261 #else
262 static inline int flag_is_changeable_p(u32 flag)
263 {
264 return 1;
265 }
266 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
267 {
268 }
269 #endif
270
271 static __init int setup_disable_smep(char *arg)
272 {
273 setup_clear_cpu_cap(X86_FEATURE_SMEP);
274 /* Check for things that depend on SMEP being enabled: */
275 check_mpx_erratum(&boot_cpu_data);
276 return 1;
277 }
278 __setup("nosmep", setup_disable_smep);
279
280 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
281 {
282 if (cpu_has(c, X86_FEATURE_SMEP))
283 cr4_set_bits(X86_CR4_SMEP);
284 }
285
286 static __init int setup_disable_smap(char *arg)
287 {
288 setup_clear_cpu_cap(X86_FEATURE_SMAP);
289 return 1;
290 }
291 __setup("nosmap", setup_disable_smap);
292
293 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
294 {
295 unsigned long eflags = native_save_fl();
296
297 /* This should have been cleared long ago */
298 BUG_ON(eflags & X86_EFLAGS_AC);
299
300 if (cpu_has(c, X86_FEATURE_SMAP)) {
301 #ifdef CONFIG_X86_SMAP
302 cr4_set_bits(X86_CR4_SMAP);
303 #else
304 cr4_clear_bits(X86_CR4_SMAP);
305 #endif
306 }
307 }
308
309 /*
310 * Protection Keys are not available in 32-bit mode.
311 */
312 static bool pku_disabled;
313
314 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
315 {
316 /* check the boot processor, plus compile options for PKU: */
317 if (!cpu_feature_enabled(X86_FEATURE_PKU))
318 return;
319 /* checks the actual processor's cpuid bits: */
320 if (!cpu_has(c, X86_FEATURE_PKU))
321 return;
322 if (pku_disabled)
323 return;
324
325 cr4_set_bits(X86_CR4_PKE);
326 /*
327 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
328 * cpuid bit to be set. We need to ensure that we
329 * update that bit in this CPU's "cpu_info".
330 */
331 get_cpu_cap(c);
332 }
333
334 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
335 static __init int setup_disable_pku(char *arg)
336 {
337 /*
338 * Do not clear the X86_FEATURE_PKU bit. All of the
339 * runtime checks are against OSPKE so clearing the
340 * bit does nothing.
341 *
342 * This way, we will see "pku" in cpuinfo, but not
343 * "ospke", which is exactly what we want. It shows
344 * that the CPU has PKU, but the OS has not enabled it.
345 * This happens to be exactly how a system would look
346 * if we disabled the config option.
347 */
348 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
349 pku_disabled = true;
350 return 1;
351 }
352 __setup("nopku", setup_disable_pku);
353 #endif /* CONFIG_X86_64 */
354
355 /*
356 * Some CPU features depend on higher CPUID levels, which may not always
357 * be available due to CPUID level capping or broken virtualization
358 * software. Add those features to this table to auto-disable them.
359 */
360 struct cpuid_dependent_feature {
361 u32 feature;
362 u32 level;
363 };
364
365 static const struct cpuid_dependent_feature
366 cpuid_dependent_features[] = {
367 { X86_FEATURE_MWAIT, 0x00000005 },
368 { X86_FEATURE_DCA, 0x00000009 },
369 { X86_FEATURE_XSAVE, 0x0000000d },
370 { 0, 0 }
371 };
372
373 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
374 {
375 const struct cpuid_dependent_feature *df;
376
377 for (df = cpuid_dependent_features; df->feature; df++) {
378
379 if (!cpu_has(c, df->feature))
380 continue;
381 /*
382 * Note: cpuid_level is set to -1 if unavailable, but
383 * extended_extended_level is set to 0 if unavailable
384 * and the legitimate extended levels are all negative
385 * when signed; hence the weird messing around with
386 * signs here...
387 */
388 if (!((s32)df->level < 0 ?
389 (u32)df->level > (u32)c->extended_cpuid_level :
390 (s32)df->level > (s32)c->cpuid_level))
391 continue;
392
393 clear_cpu_cap(c, df->feature);
394 if (!warn)
395 continue;
396
397 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
398 x86_cap_flag(df->feature), df->level);
399 }
400 }
401
402 /*
403 * Naming convention should be: <Name> [(<Codename>)]
404 * This table only is used unless init_<vendor>() below doesn't set it;
405 * in particular, if CPUID levels 0x80000002..4 are supported, this
406 * isn't used
407 */
408
409 /* Look up CPU names by table lookup. */
410 static const char *table_lookup_model(struct cpuinfo_x86 *c)
411 {
412 #ifdef CONFIG_X86_32
413 const struct legacy_cpu_model_info *info;
414
415 if (c->x86_model >= 16)
416 return NULL; /* Range check */
417
418 if (!this_cpu)
419 return NULL;
420
421 info = this_cpu->legacy_models;
422
423 while (info->family) {
424 if (info->family == c->x86)
425 return info->model_names[c->x86_model];
426 info++;
427 }
428 #endif
429 return NULL; /* Not found */
430 }
431
432 __u32 cpu_caps_cleared[NCAPINTS];
433 __u32 cpu_caps_set[NCAPINTS];
434
435 void load_percpu_segment(int cpu)
436 {
437 #ifdef CONFIG_X86_32
438 loadsegment(fs, __KERNEL_PERCPU);
439 #else
440 __loadsegment_simple(gs, 0);
441 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
442 #endif
443 load_stack_canary_segment();
444 }
445
446 /*
447 * Current gdt points %fs at the "master" per-cpu area: after this,
448 * it's on the real one.
449 */
450 void switch_to_new_gdt(int cpu)
451 {
452 struct desc_ptr gdt_descr;
453
454 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
455 gdt_descr.size = GDT_SIZE - 1;
456 load_gdt(&gdt_descr);
457 /* Reload the per-cpu base */
458
459 load_percpu_segment(cpu);
460 }
461
462 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
463
464 static void get_model_name(struct cpuinfo_x86 *c)
465 {
466 unsigned int *v;
467 char *p, *q, *s;
468
469 if (c->extended_cpuid_level < 0x80000004)
470 return;
471
472 v = (unsigned int *)c->x86_model_id;
473 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
474 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
475 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
476 c->x86_model_id[48] = 0;
477
478 /* Trim whitespace */
479 p = q = s = &c->x86_model_id[0];
480
481 while (*p == ' ')
482 p++;
483
484 while (*p) {
485 /* Note the last non-whitespace index */
486 if (!isspace(*p))
487 s = q;
488
489 *q++ = *p++;
490 }
491
492 *(s + 1) = '\0';
493 }
494
495 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
496 {
497 unsigned int n, dummy, ebx, ecx, edx, l2size;
498
499 n = c->extended_cpuid_level;
500
501 if (n >= 0x80000005) {
502 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
503 c->x86_cache_size = (ecx>>24) + (edx>>24);
504 #ifdef CONFIG_X86_64
505 /* On K8 L1 TLB is inclusive, so don't count it */
506 c->x86_tlbsize = 0;
507 #endif
508 }
509
510 if (n < 0x80000006) /* Some chips just has a large L1. */
511 return;
512
513 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
514 l2size = ecx >> 16;
515
516 #ifdef CONFIG_X86_64
517 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
518 #else
519 /* do processor-specific cache resizing */
520 if (this_cpu->legacy_cache_size)
521 l2size = this_cpu->legacy_cache_size(c, l2size);
522
523 /* Allow user to override all this if necessary. */
524 if (cachesize_override != -1)
525 l2size = cachesize_override;
526
527 if (l2size == 0)
528 return; /* Again, no L2 cache is possible */
529 #endif
530
531 c->x86_cache_size = l2size;
532 }
533
534 u16 __read_mostly tlb_lli_4k[NR_INFO];
535 u16 __read_mostly tlb_lli_2m[NR_INFO];
536 u16 __read_mostly tlb_lli_4m[NR_INFO];
537 u16 __read_mostly tlb_lld_4k[NR_INFO];
538 u16 __read_mostly tlb_lld_2m[NR_INFO];
539 u16 __read_mostly tlb_lld_4m[NR_INFO];
540 u16 __read_mostly tlb_lld_1g[NR_INFO];
541
542 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
543 {
544 if (this_cpu->c_detect_tlb)
545 this_cpu->c_detect_tlb(c);
546
547 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
548 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
549 tlb_lli_4m[ENTRIES]);
550
551 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
552 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
553 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
554 }
555
556 void detect_ht(struct cpuinfo_x86 *c)
557 {
558 #ifdef CONFIG_SMP
559 u32 eax, ebx, ecx, edx;
560 int index_msb, core_bits;
561 static bool printed;
562
563 if (!cpu_has(c, X86_FEATURE_HT))
564 return;
565
566 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
567 goto out;
568
569 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
570 return;
571
572 cpuid(1, &eax, &ebx, &ecx, &edx);
573
574 smp_num_siblings = (ebx & 0xff0000) >> 16;
575
576 if (smp_num_siblings == 1) {
577 pr_info_once("CPU0: Hyper-Threading is disabled\n");
578 goto out;
579 }
580
581 if (smp_num_siblings <= 1)
582 goto out;
583
584 index_msb = get_count_order(smp_num_siblings);
585 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
586
587 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
588
589 index_msb = get_count_order(smp_num_siblings);
590
591 core_bits = get_count_order(c->x86_max_cores);
592
593 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
594 ((1 << core_bits) - 1);
595
596 out:
597 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
598 pr_info("CPU: Physical Processor ID: %d\n",
599 c->phys_proc_id);
600 pr_info("CPU: Processor Core ID: %d\n",
601 c->cpu_core_id);
602 printed = 1;
603 }
604 #endif
605 }
606
607 static void get_cpu_vendor(struct cpuinfo_x86 *c)
608 {
609 char *v = c->x86_vendor_id;
610 int i;
611
612 for (i = 0; i < X86_VENDOR_NUM; i++) {
613 if (!cpu_devs[i])
614 break;
615
616 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
617 (cpu_devs[i]->c_ident[1] &&
618 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
619
620 this_cpu = cpu_devs[i];
621 c->x86_vendor = this_cpu->c_x86_vendor;
622 return;
623 }
624 }
625
626 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
627 "CPU: Your system may be unstable.\n", v);
628
629 c->x86_vendor = X86_VENDOR_UNKNOWN;
630 this_cpu = &default_cpu;
631 }
632
633 void cpu_detect(struct cpuinfo_x86 *c)
634 {
635 /* Get vendor name */
636 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
637 (unsigned int *)&c->x86_vendor_id[0],
638 (unsigned int *)&c->x86_vendor_id[8],
639 (unsigned int *)&c->x86_vendor_id[4]);
640
641 c->x86 = 4;
642 /* Intel-defined flags: level 0x00000001 */
643 if (c->cpuid_level >= 0x00000001) {
644 u32 junk, tfms, cap0, misc;
645
646 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
647 c->x86 = x86_family(tfms);
648 c->x86_model = x86_model(tfms);
649 c->x86_mask = x86_stepping(tfms);
650
651 if (cap0 & (1<<19)) {
652 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
653 c->x86_cache_alignment = c->x86_clflush_size;
654 }
655 }
656 }
657
658 void get_cpu_cap(struct cpuinfo_x86 *c)
659 {
660 u32 eax, ebx, ecx, edx;
661
662 /* Intel-defined flags: level 0x00000001 */
663 if (c->cpuid_level >= 0x00000001) {
664 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
665
666 c->x86_capability[CPUID_1_ECX] = ecx;
667 c->x86_capability[CPUID_1_EDX] = edx;
668 }
669
670 /* Additional Intel-defined flags: level 0x00000007 */
671 if (c->cpuid_level >= 0x00000007) {
672 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
673
674 c->x86_capability[CPUID_7_0_EBX] = ebx;
675
676 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
677 c->x86_capability[CPUID_7_ECX] = ecx;
678 }
679
680 /* Extended state features: level 0x0000000d */
681 if (c->cpuid_level >= 0x0000000d) {
682 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
683
684 c->x86_capability[CPUID_D_1_EAX] = eax;
685 }
686
687 /* Additional Intel-defined flags: level 0x0000000F */
688 if (c->cpuid_level >= 0x0000000F) {
689
690 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
691 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
692 c->x86_capability[CPUID_F_0_EDX] = edx;
693
694 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
695 /* will be overridden if occupancy monitoring exists */
696 c->x86_cache_max_rmid = ebx;
697
698 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
699 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
700 c->x86_capability[CPUID_F_1_EDX] = edx;
701
702 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
703 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
704 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
705 c->x86_cache_max_rmid = ecx;
706 c->x86_cache_occ_scale = ebx;
707 }
708 } else {
709 c->x86_cache_max_rmid = -1;
710 c->x86_cache_occ_scale = -1;
711 }
712 }
713
714 /* AMD-defined flags: level 0x80000001 */
715 eax = cpuid_eax(0x80000000);
716 c->extended_cpuid_level = eax;
717
718 if ((eax & 0xffff0000) == 0x80000000) {
719 if (eax >= 0x80000001) {
720 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
721
722 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
723 c->x86_capability[CPUID_8000_0001_EDX] = edx;
724 }
725 }
726
727 if (c->extended_cpuid_level >= 0x80000007) {
728 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
729
730 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
731 c->x86_power = edx;
732 }
733
734 if (c->extended_cpuid_level >= 0x80000008) {
735 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
736
737 c->x86_virt_bits = (eax >> 8) & 0xff;
738 c->x86_phys_bits = eax & 0xff;
739 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
740 }
741 #ifdef CONFIG_X86_32
742 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
743 c->x86_phys_bits = 36;
744 #endif
745
746 if (c->extended_cpuid_level >= 0x8000000a)
747 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
748
749 init_scattered_cpuid_features(c);
750 }
751
752 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
753 {
754 #ifdef CONFIG_X86_32
755 int i;
756
757 /*
758 * First of all, decide if this is a 486 or higher
759 * It's a 486 if we can modify the AC flag
760 */
761 if (flag_is_changeable_p(X86_EFLAGS_AC))
762 c->x86 = 4;
763 else
764 c->x86 = 3;
765
766 for (i = 0; i < X86_VENDOR_NUM; i++)
767 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
768 c->x86_vendor_id[0] = 0;
769 cpu_devs[i]->c_identify(c);
770 if (c->x86_vendor_id[0]) {
771 get_cpu_vendor(c);
772 break;
773 }
774 }
775 #endif
776 }
777
778 /*
779 * Do minimum CPU detection early.
780 * Fields really needed: vendor, cpuid_level, family, model, mask,
781 * cache alignment.
782 * The others are not touched to avoid unwanted side effects.
783 *
784 * WARNING: this function is only called on the BP. Don't add code here
785 * that is supposed to run on all CPUs.
786 */
787 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
788 {
789 #ifdef CONFIG_X86_64
790 c->x86_clflush_size = 64;
791 c->x86_phys_bits = 36;
792 c->x86_virt_bits = 48;
793 #else
794 c->x86_clflush_size = 32;
795 c->x86_phys_bits = 32;
796 c->x86_virt_bits = 32;
797 #endif
798 c->x86_cache_alignment = c->x86_clflush_size;
799
800 memset(&c->x86_capability, 0, sizeof c->x86_capability);
801 c->extended_cpuid_level = 0;
802
803 if (!have_cpuid_p())
804 identify_cpu_without_cpuid(c);
805
806 /* cyrix could have cpuid enabled via c_identify()*/
807 if (have_cpuid_p()) {
808 cpu_detect(c);
809 get_cpu_vendor(c);
810 get_cpu_cap(c);
811
812 if (this_cpu->c_early_init)
813 this_cpu->c_early_init(c);
814
815 c->cpu_index = 0;
816 filter_cpuid_features(c, false);
817
818 if (this_cpu->c_bsp_init)
819 this_cpu->c_bsp_init(c);
820 }
821
822 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
823 fpu__init_system(c);
824 }
825
826 void __init early_cpu_init(void)
827 {
828 const struct cpu_dev *const *cdev;
829 int count = 0;
830
831 #ifdef CONFIG_PROCESSOR_SELECT
832 pr_info("KERNEL supported cpus:\n");
833 #endif
834
835 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
836 const struct cpu_dev *cpudev = *cdev;
837
838 if (count >= X86_VENDOR_NUM)
839 break;
840 cpu_devs[count] = cpudev;
841 count++;
842
843 #ifdef CONFIG_PROCESSOR_SELECT
844 {
845 unsigned int j;
846
847 for (j = 0; j < 2; j++) {
848 if (!cpudev->c_ident[j])
849 continue;
850 pr_info(" %s %s\n", cpudev->c_vendor,
851 cpudev->c_ident[j]);
852 }
853 }
854 #endif
855 }
856 early_identify_cpu(&boot_cpu_data);
857 }
858
859 /*
860 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
861 * unfortunately, that's not true in practice because of early VIA
862 * chips and (more importantly) broken virtualizers that are not easy
863 * to detect. In the latter case it doesn't even *fail* reliably, so
864 * probing for it doesn't even work. Disable it completely on 32-bit
865 * unless we can find a reliable way to detect all the broken cases.
866 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
867 */
868 static void detect_nopl(struct cpuinfo_x86 *c)
869 {
870 #ifdef CONFIG_X86_32
871 clear_cpu_cap(c, X86_FEATURE_NOPL);
872 #else
873 set_cpu_cap(c, X86_FEATURE_NOPL);
874 #endif
875 }
876
877 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
878 {
879 #ifdef CONFIG_X86_64
880 /*
881 * Empirically, writing zero to a segment selector on AMD does
882 * not clear the base, whereas writing zero to a segment
883 * selector on Intel does clear the base. Intel's behavior
884 * allows slightly faster context switches in the common case
885 * where GS is unused by the prev and next threads.
886 *
887 * Since neither vendor documents this anywhere that I can see,
888 * detect it directly instead of hardcoding the choice by
889 * vendor.
890 *
891 * I've designated AMD's behavior as the "bug" because it's
892 * counterintuitive and less friendly.
893 */
894
895 unsigned long old_base, tmp;
896 rdmsrl(MSR_FS_BASE, old_base);
897 wrmsrl(MSR_FS_BASE, 1);
898 loadsegment(fs, 0);
899 rdmsrl(MSR_FS_BASE, tmp);
900 if (tmp != 0)
901 set_cpu_bug(c, X86_BUG_NULL_SEG);
902 wrmsrl(MSR_FS_BASE, old_base);
903 #endif
904 }
905
906 static void generic_identify(struct cpuinfo_x86 *c)
907 {
908 c->extended_cpuid_level = 0;
909
910 if (!have_cpuid_p())
911 identify_cpu_without_cpuid(c);
912
913 /* cyrix could have cpuid enabled via c_identify()*/
914 if (!have_cpuid_p())
915 return;
916
917 cpu_detect(c);
918
919 get_cpu_vendor(c);
920
921 get_cpu_cap(c);
922
923 if (c->cpuid_level >= 0x00000001) {
924 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
925 #ifdef CONFIG_X86_32
926 # ifdef CONFIG_SMP
927 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
928 # else
929 c->apicid = c->initial_apicid;
930 # endif
931 #endif
932 c->phys_proc_id = c->initial_apicid;
933 }
934
935 get_model_name(c); /* Default name */
936
937 detect_nopl(c);
938
939 detect_null_seg_behavior(c);
940
941 /*
942 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
943 * systems that run Linux at CPL > 0 may or may not have the
944 * issue, but, even if they have the issue, there's absolutely
945 * nothing we can do about it because we can't use the real IRET
946 * instruction.
947 *
948 * NB: For the time being, only 32-bit kernels support
949 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
950 * whether to apply espfix using paravirt hooks. If any
951 * non-paravirt system ever shows up that does *not* have the
952 * ESPFIX issue, we can change this.
953 */
954 #ifdef CONFIG_X86_32
955 # ifdef CONFIG_PARAVIRT
956 do {
957 extern void native_iret(void);
958 if (pv_cpu_ops.iret == native_iret)
959 set_cpu_bug(c, X86_BUG_ESPFIX);
960 } while (0);
961 # else
962 set_cpu_bug(c, X86_BUG_ESPFIX);
963 # endif
964 #endif
965 }
966
967 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
968 {
969 /*
970 * The heavy lifting of max_rmid and cache_occ_scale are handled
971 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
972 * in case CQM bits really aren't there in this CPU.
973 */
974 if (c != &boot_cpu_data) {
975 boot_cpu_data.x86_cache_max_rmid =
976 min(boot_cpu_data.x86_cache_max_rmid,
977 c->x86_cache_max_rmid);
978 }
979 }
980
981 /*
982 * This does the hard work of actually picking apart the CPU stuff...
983 */
984 static void identify_cpu(struct cpuinfo_x86 *c)
985 {
986 int i;
987
988 c->loops_per_jiffy = loops_per_jiffy;
989 c->x86_cache_size = -1;
990 c->x86_vendor = X86_VENDOR_UNKNOWN;
991 c->x86_model = c->x86_mask = 0; /* So far unknown... */
992 c->x86_vendor_id[0] = '\0'; /* Unset */
993 c->x86_model_id[0] = '\0'; /* Unset */
994 c->x86_max_cores = 1;
995 c->x86_coreid_bits = 0;
996 #ifdef CONFIG_X86_64
997 c->x86_clflush_size = 64;
998 c->x86_phys_bits = 36;
999 c->x86_virt_bits = 48;
1000 #else
1001 c->cpuid_level = -1; /* CPUID not detected */
1002 c->x86_clflush_size = 32;
1003 c->x86_phys_bits = 32;
1004 c->x86_virt_bits = 32;
1005 #endif
1006 c->x86_cache_alignment = c->x86_clflush_size;
1007 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1008
1009 generic_identify(c);
1010
1011 if (this_cpu->c_identify)
1012 this_cpu->c_identify(c);
1013
1014 /* Clear/Set all flags overridden by options, after probe */
1015 for (i = 0; i < NCAPINTS; i++) {
1016 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1017 c->x86_capability[i] |= cpu_caps_set[i];
1018 }
1019
1020 #ifdef CONFIG_X86_64
1021 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1022 #endif
1023
1024 /*
1025 * Vendor-specific initialization. In this section we
1026 * canonicalize the feature flags, meaning if there are
1027 * features a certain CPU supports which CPUID doesn't
1028 * tell us, CPUID claiming incorrect flags, or other bugs,
1029 * we handle them here.
1030 *
1031 * At the end of this section, c->x86_capability better
1032 * indicate the features this CPU genuinely supports!
1033 */
1034 if (this_cpu->c_init)
1035 this_cpu->c_init(c);
1036
1037 /* Disable the PN if appropriate */
1038 squash_the_stupid_serial_number(c);
1039
1040 /* Set up SMEP/SMAP */
1041 setup_smep(c);
1042 setup_smap(c);
1043
1044 /*
1045 * The vendor-specific functions might have changed features.
1046 * Now we do "generic changes."
1047 */
1048
1049 /* Filter out anything that depends on CPUID levels we don't have */
1050 filter_cpuid_features(c, true);
1051
1052 /* If the model name is still unset, do table lookup. */
1053 if (!c->x86_model_id[0]) {
1054 const char *p;
1055 p = table_lookup_model(c);
1056 if (p)
1057 strcpy(c->x86_model_id, p);
1058 else
1059 /* Last resort... */
1060 sprintf(c->x86_model_id, "%02x/%02x",
1061 c->x86, c->x86_model);
1062 }
1063
1064 #ifdef CONFIG_X86_64
1065 detect_ht(c);
1066 #endif
1067
1068 init_hypervisor(c);
1069 x86_init_rdrand(c);
1070 x86_init_cache_qos(c);
1071 setup_pku(c);
1072
1073 /*
1074 * Clear/Set all flags overridden by options, need do it
1075 * before following smp all cpus cap AND.
1076 */
1077 for (i = 0; i < NCAPINTS; i++) {
1078 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1079 c->x86_capability[i] |= cpu_caps_set[i];
1080 }
1081
1082 /*
1083 * On SMP, boot_cpu_data holds the common feature set between
1084 * all CPUs; so make sure that we indicate which features are
1085 * common between the CPUs. The first time this routine gets
1086 * executed, c == &boot_cpu_data.
1087 */
1088 if (c != &boot_cpu_data) {
1089 /* AND the already accumulated flags with these */
1090 for (i = 0; i < NCAPINTS; i++)
1091 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1092
1093 /* OR, i.e. replicate the bug flags */
1094 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1095 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1096 }
1097
1098 /* Init Machine Check Exception if available. */
1099 mcheck_cpu_init(c);
1100
1101 select_idle_routine(c);
1102
1103 #ifdef CONFIG_NUMA
1104 numa_add_cpu(smp_processor_id());
1105 #endif
1106 /* The boot/hotplug time assigment got cleared, restore it */
1107 c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
1108 }
1109
1110 /*
1111 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1112 * on 32-bit kernels:
1113 */
1114 #ifdef CONFIG_X86_32
1115 void enable_sep_cpu(void)
1116 {
1117 struct tss_struct *tss;
1118 int cpu;
1119
1120 if (!boot_cpu_has(X86_FEATURE_SEP))
1121 return;
1122
1123 cpu = get_cpu();
1124 tss = &per_cpu(cpu_tss, cpu);
1125
1126 /*
1127 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1128 * see the big comment in struct x86_hw_tss's definition.
1129 */
1130
1131 tss->x86_tss.ss1 = __KERNEL_CS;
1132 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1133
1134 wrmsr(MSR_IA32_SYSENTER_ESP,
1135 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1136 0);
1137
1138 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1139
1140 put_cpu();
1141 }
1142 #endif
1143
1144 void __init identify_boot_cpu(void)
1145 {
1146 identify_cpu(&boot_cpu_data);
1147 init_amd_e400_c1e_mask();
1148 #ifdef CONFIG_X86_32
1149 sysenter_setup();
1150 enable_sep_cpu();
1151 #endif
1152 cpu_detect_tlb(&boot_cpu_data);
1153 }
1154
1155 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1156 {
1157 BUG_ON(c == &boot_cpu_data);
1158 identify_cpu(c);
1159 #ifdef CONFIG_X86_32
1160 enable_sep_cpu();
1161 #endif
1162 mtrr_ap_init();
1163 }
1164
1165 struct msr_range {
1166 unsigned min;
1167 unsigned max;
1168 };
1169
1170 static const struct msr_range msr_range_array[] = {
1171 { 0x00000000, 0x00000418},
1172 { 0xc0000000, 0xc000040b},
1173 { 0xc0010000, 0xc0010142},
1174 { 0xc0011000, 0xc001103b},
1175 };
1176
1177 static void __print_cpu_msr(void)
1178 {
1179 unsigned index_min, index_max;
1180 unsigned index;
1181 u64 val;
1182 int i;
1183
1184 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1185 index_min = msr_range_array[i].min;
1186 index_max = msr_range_array[i].max;
1187
1188 for (index = index_min; index < index_max; index++) {
1189 if (rdmsrl_safe(index, &val))
1190 continue;
1191 pr_info(" MSR%08x: %016llx\n", index, val);
1192 }
1193 }
1194 }
1195
1196 static int show_msr;
1197
1198 static __init int setup_show_msr(char *arg)
1199 {
1200 int num;
1201
1202 get_option(&arg, &num);
1203
1204 if (num > 0)
1205 show_msr = num;
1206 return 1;
1207 }
1208 __setup("show_msr=", setup_show_msr);
1209
1210 static __init int setup_noclflush(char *arg)
1211 {
1212 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1213 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1214 return 1;
1215 }
1216 __setup("noclflush", setup_noclflush);
1217
1218 void print_cpu_info(struct cpuinfo_x86 *c)
1219 {
1220 const char *vendor = NULL;
1221
1222 if (c->x86_vendor < X86_VENDOR_NUM) {
1223 vendor = this_cpu->c_vendor;
1224 } else {
1225 if (c->cpuid_level >= 0)
1226 vendor = c->x86_vendor_id;
1227 }
1228
1229 if (vendor && !strstr(c->x86_model_id, vendor))
1230 pr_cont("%s ", vendor);
1231
1232 if (c->x86_model_id[0])
1233 pr_cont("%s", c->x86_model_id);
1234 else
1235 pr_cont("%d86", c->x86);
1236
1237 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1238
1239 if (c->x86_mask || c->cpuid_level >= 0)
1240 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1241 else
1242 pr_cont(")\n");
1243
1244 print_cpu_msr(c);
1245 }
1246
1247 void print_cpu_msr(struct cpuinfo_x86 *c)
1248 {
1249 if (c->cpu_index < show_msr)
1250 __print_cpu_msr();
1251 }
1252
1253 static __init int setup_disablecpuid(char *arg)
1254 {
1255 int bit;
1256
1257 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1258 setup_clear_cpu_cap(bit);
1259 else
1260 return 0;
1261
1262 return 1;
1263 }
1264 __setup("clearcpuid=", setup_disablecpuid);
1265
1266 #ifdef CONFIG_X86_64
1267 struct desc_ptr idt_descr __ro_after_init = {
1268 .size = NR_VECTORS * 16 - 1,
1269 .address = (unsigned long) idt_table,
1270 };
1271 const struct desc_ptr debug_idt_descr = {
1272 .size = NR_VECTORS * 16 - 1,
1273 .address = (unsigned long) debug_idt_table,
1274 };
1275
1276 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1277 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1278
1279 /*
1280 * The following percpu variables are hot. Align current_task to
1281 * cacheline size such that they fall in the same cacheline.
1282 */
1283 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1284 &init_task;
1285 EXPORT_PER_CPU_SYMBOL(current_task);
1286
1287 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1288 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1289
1290 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1291
1292 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1293 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1294
1295 /*
1296 * Special IST stacks which the CPU switches to when it calls
1297 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1298 * limit), all of them are 4K, except the debug stack which
1299 * is 8K.
1300 */
1301 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1302 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1303 [DEBUG_STACK - 1] = DEBUG_STKSZ
1304 };
1305
1306 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1307 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1308
1309 /* May not be marked __init: used by software suspend */
1310 void syscall_init(void)
1311 {
1312 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1313 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1314
1315 #ifdef CONFIG_IA32_EMULATION
1316 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1317 /*
1318 * This only works on Intel CPUs.
1319 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1320 * This does not cause SYSENTER to jump to the wrong location, because
1321 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1322 */
1323 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1324 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1325 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1326 #else
1327 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1328 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1329 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1330 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1331 #endif
1332
1333 /* Flags to clear on syscall */
1334 wrmsrl(MSR_SYSCALL_MASK,
1335 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1336 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1337 }
1338
1339 /*
1340 * Copies of the original ist values from the tss are only accessed during
1341 * debugging, no special alignment required.
1342 */
1343 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1344
1345 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1346 DEFINE_PER_CPU(int, debug_stack_usage);
1347
1348 int is_debug_stack(unsigned long addr)
1349 {
1350 return __this_cpu_read(debug_stack_usage) ||
1351 (addr <= __this_cpu_read(debug_stack_addr) &&
1352 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1353 }
1354 NOKPROBE_SYMBOL(is_debug_stack);
1355
1356 DEFINE_PER_CPU(u32, debug_idt_ctr);
1357
1358 void debug_stack_set_zero(void)
1359 {
1360 this_cpu_inc(debug_idt_ctr);
1361 load_current_idt();
1362 }
1363 NOKPROBE_SYMBOL(debug_stack_set_zero);
1364
1365 void debug_stack_reset(void)
1366 {
1367 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1368 return;
1369 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1370 load_current_idt();
1371 }
1372 NOKPROBE_SYMBOL(debug_stack_reset);
1373
1374 #else /* CONFIG_X86_64 */
1375
1376 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1377 EXPORT_PER_CPU_SYMBOL(current_task);
1378 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1379 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1380
1381 /*
1382 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1383 * the top of the kernel stack. Use an extra percpu variable to track the
1384 * top of the kernel stack directly.
1385 */
1386 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1387 (unsigned long)&init_thread_union + THREAD_SIZE;
1388 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1389
1390 #ifdef CONFIG_CC_STACKPROTECTOR
1391 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1392 #endif
1393
1394 #endif /* CONFIG_X86_64 */
1395
1396 /*
1397 * Clear all 6 debug registers:
1398 */
1399 static void clear_all_debug_regs(void)
1400 {
1401 int i;
1402
1403 for (i = 0; i < 8; i++) {
1404 /* Ignore db4, db5 */
1405 if ((i == 4) || (i == 5))
1406 continue;
1407
1408 set_debugreg(0, i);
1409 }
1410 }
1411
1412 #ifdef CONFIG_KGDB
1413 /*
1414 * Restore debug regs if using kgdbwait and you have a kernel debugger
1415 * connection established.
1416 */
1417 static void dbg_restore_debug_regs(void)
1418 {
1419 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1420 arch_kgdb_ops.correct_hw_break();
1421 }
1422 #else /* ! CONFIG_KGDB */
1423 #define dbg_restore_debug_regs()
1424 #endif /* ! CONFIG_KGDB */
1425
1426 static void wait_for_master_cpu(int cpu)
1427 {
1428 #ifdef CONFIG_SMP
1429 /*
1430 * wait for ACK from master CPU before continuing
1431 * with AP initialization
1432 */
1433 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1434 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1435 cpu_relax();
1436 #endif
1437 }
1438
1439 /*
1440 * cpu_init() initializes state that is per-CPU. Some data is already
1441 * initialized (naturally) in the bootstrap process, such as the GDT
1442 * and IDT. We reload them nevertheless, this function acts as a
1443 * 'CPU state barrier', nothing should get across.
1444 * A lot of state is already set up in PDA init for 64 bit
1445 */
1446 #ifdef CONFIG_X86_64
1447
1448 void cpu_init(void)
1449 {
1450 struct orig_ist *oist;
1451 struct task_struct *me;
1452 struct tss_struct *t;
1453 unsigned long v;
1454 int cpu = raw_smp_processor_id();
1455 int i;
1456
1457 wait_for_master_cpu(cpu);
1458
1459 /*
1460 * Initialize the CR4 shadow before doing anything that could
1461 * try to read it.
1462 */
1463 cr4_init_shadow();
1464
1465 /*
1466 * Load microcode on this cpu if a valid microcode is available.
1467 * This is early microcode loading procedure.
1468 */
1469 load_ucode_ap();
1470
1471 t = &per_cpu(cpu_tss, cpu);
1472 oist = &per_cpu(orig_ist, cpu);
1473
1474 #ifdef CONFIG_NUMA
1475 if (this_cpu_read(numa_node) == 0 &&
1476 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1477 set_numa_node(early_cpu_to_node(cpu));
1478 #endif
1479
1480 me = current;
1481
1482 pr_debug("Initializing CPU#%d\n", cpu);
1483
1484 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1485
1486 /*
1487 * Initialize the per-CPU GDT with the boot GDT,
1488 * and set up the GDT descriptor:
1489 */
1490
1491 switch_to_new_gdt(cpu);
1492 loadsegment(fs, 0);
1493
1494 load_current_idt();
1495
1496 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1497 syscall_init();
1498
1499 wrmsrl(MSR_FS_BASE, 0);
1500 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1501 barrier();
1502
1503 x86_configure_nx();
1504 x2apic_setup();
1505
1506 /*
1507 * set up and load the per-CPU TSS
1508 */
1509 if (!oist->ist[0]) {
1510 char *estacks = per_cpu(exception_stacks, cpu);
1511
1512 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1513 estacks += exception_stack_sizes[v];
1514 oist->ist[v] = t->x86_tss.ist[v] =
1515 (unsigned long)estacks;
1516 if (v == DEBUG_STACK-1)
1517 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1518 }
1519 }
1520
1521 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1522
1523 /*
1524 * <= is required because the CPU will access up to
1525 * 8 bits beyond the end of the IO permission bitmap.
1526 */
1527 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1528 t->io_bitmap[i] = ~0UL;
1529
1530 atomic_inc(&init_mm.mm_count);
1531 me->active_mm = &init_mm;
1532 BUG_ON(me->mm);
1533 enter_lazy_tlb(&init_mm, me);
1534
1535 load_sp0(t, &current->thread);
1536 set_tss_desc(cpu, t);
1537 load_TR_desc();
1538 load_mm_ldt(&init_mm);
1539
1540 clear_all_debug_regs();
1541 dbg_restore_debug_regs();
1542
1543 fpu__init_cpu();
1544
1545 if (is_uv_system())
1546 uv_cpu_init();
1547 }
1548
1549 #else
1550
1551 void cpu_init(void)
1552 {
1553 int cpu = smp_processor_id();
1554 struct task_struct *curr = current;
1555 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1556 struct thread_struct *thread = &curr->thread;
1557
1558 wait_for_master_cpu(cpu);
1559
1560 /*
1561 * Initialize the CR4 shadow before doing anything that could
1562 * try to read it.
1563 */
1564 cr4_init_shadow();
1565
1566 show_ucode_info_early();
1567
1568 pr_info("Initializing CPU#%d\n", cpu);
1569
1570 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1571 boot_cpu_has(X86_FEATURE_TSC) ||
1572 boot_cpu_has(X86_FEATURE_DE))
1573 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1574
1575 load_current_idt();
1576 switch_to_new_gdt(cpu);
1577
1578 /*
1579 * Set up and load the per-CPU TSS and LDT
1580 */
1581 atomic_inc(&init_mm.mm_count);
1582 curr->active_mm = &init_mm;
1583 BUG_ON(curr->mm);
1584 enter_lazy_tlb(&init_mm, curr);
1585
1586 load_sp0(t, thread);
1587 set_tss_desc(cpu, t);
1588 load_TR_desc();
1589 load_mm_ldt(&init_mm);
1590
1591 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1592
1593 #ifdef CONFIG_DOUBLEFAULT
1594 /* Set up doublefault TSS pointer in the GDT */
1595 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1596 #endif
1597
1598 clear_all_debug_regs();
1599 dbg_restore_debug_regs();
1600
1601 fpu__init_cpu();
1602 }
1603 #endif
1604
1605 static void bsp_resume(void)
1606 {
1607 if (this_cpu->c_bsp_resume)
1608 this_cpu->c_bsp_resume(&boot_cpu_data);
1609 }
1610
1611 static struct syscore_ops cpu_syscore_ops = {
1612 .resume = bsp_resume,
1613 };
1614
1615 static int __init init_cpu_syscore(void)
1616 {
1617 register_syscore_ops(&cpu_syscore_ops);
1618 return 0;
1619 }
1620 core_initcall(init_cpu_syscore);