1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/sched/clock.h>
12 #include <linux/init.h>
13 #include <linux/kprobes.h>
14 #include <linux/kgdb.h>
15 #include <linux/smp.h>
17 #include <linux/syscore_ops.h>
19 #include <asm/stackprotector.h>
20 #include <asm/perf_event.h>
21 #include <asm/mmu_context.h>
22 #include <asm/archrandom.h>
23 #include <asm/hypervisor.h>
24 #include <asm/processor.h>
25 #include <asm/tlbflush.h>
26 #include <asm/debugreg.h>
27 #include <asm/sections.h>
28 #include <asm/vsyscall.h>
29 #include <linux/topology.h>
30 #include <linux/cpumask.h>
31 #include <asm/pgtable.h>
32 #include <linux/atomic.h>
33 #include <asm/proto.h>
34 #include <asm/setup.h>
37 #include <asm/fpu/internal.h>
39 #include <asm/hwcap2.h>
40 #include <linux/numa.h>
47 #include <asm/microcode.h>
48 #include <asm/microcode_intel.h>
50 #ifdef CONFIG_X86_LOCAL_APIC
51 #include <asm/uv/uv.h>
56 u32 elf_hwcap2 __read_mostly
;
58 /* all of these masks are initialized in setup_cpu_local_masks() */
59 cpumask_var_t cpu_initialized_mask
;
60 cpumask_var_t cpu_callout_mask
;
61 cpumask_var_t cpu_callin_mask
;
63 /* representing cpus for which sibling maps can be computed */
64 cpumask_var_t cpu_sibling_setup_mask
;
66 /* correctly size the local cpu masks */
67 void __init
setup_cpu_local_masks(void)
69 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
70 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
71 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
72 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
75 static void default_init(struct cpuinfo_x86
*c
)
78 cpu_detect_cache_sizes(c
);
80 /* Not much we can do here... */
81 /* Check if at least it has cpuid */
82 if (c
->cpuid_level
== -1) {
83 /* No cpuid. It must be an ancient CPU */
85 strcpy(c
->x86_model_id
, "486");
87 strcpy(c
->x86_model_id
, "386");
90 clear_sched_clock_stable();
93 static const struct cpu_dev default_cpu
= {
94 .c_init
= default_init
,
95 .c_vendor
= "Unknown",
96 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
99 static const struct cpu_dev
*this_cpu
= &default_cpu
;
101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
104 * We need valid kernel segments for data and code in long mode too
105 * IRET will check the segment types kkeil 2000/10/28
106 * Also sysret mandates a special GDT layout
108 * TLS descriptors are currently at a different place compared to i386.
109 * Hopefully nobody expects them at a fixed place (Wine?)
111 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
118 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
119 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
120 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
121 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
123 * Segments used for calling PnP BIOS have byte granularity.
124 * They code segments and data segments have fixed 64k limits,
125 * the transfer segment sizes are set at run time.
128 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
130 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
132 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
134 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
136 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
138 * The APM segments have byte granularity and their bases
139 * are set at run time. All have 64k limits.
142 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
144 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
146 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
148 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
149 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
150 GDT_STACK_CANARY_INIT
153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
155 static int __init
x86_mpx_setup(char *s
)
157 /* require an exact match without trailing characters */
161 /* do not emit a message if the feature is not present */
162 if (!boot_cpu_has(X86_FEATURE_MPX
))
165 setup_clear_cpu_cap(X86_FEATURE_MPX
);
166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
169 __setup("nompx", x86_mpx_setup
);
171 static int __init
x86_noinvpcid_setup(char *s
)
173 /* noinvpcid doesn't accept parameters */
177 /* do not emit a message if the feature is not present */
178 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
181 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
182 pr_info("noinvpcid: INVPCID feature disabled\n");
185 early_param("noinvpcid", x86_noinvpcid_setup
);
188 static int cachesize_override
= -1;
189 static int disable_x86_serial_nr
= 1;
191 static int __init
cachesize_setup(char *str
)
193 get_option(&str
, &cachesize_override
);
196 __setup("cachesize=", cachesize_setup
);
198 static int __init
x86_sep_setup(char *s
)
200 setup_clear_cpu_cap(X86_FEATURE_SEP
);
203 __setup("nosep", x86_sep_setup
);
205 /* Standard macro to see if a specific flag is changeable */
206 static inline int flag_is_changeable_p(u32 flag
)
211 * Cyrix and IDT cpus allow disabling of CPUID
212 * so the code below may return different results
213 * when it is executed before and after enabling
214 * the CPUID. Add "volatile" to not allow gcc to
215 * optimize the subsequent calls to this function.
217 asm volatile ("pushfl \n\t"
228 : "=&r" (f1
), "=&r" (f2
)
231 return ((f1
^f2
) & flag
) != 0;
234 /* Probe for the CPUID instruction */
235 int have_cpuid_p(void)
237 return flag_is_changeable_p(X86_EFLAGS_ID
);
240 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
242 unsigned long lo
, hi
;
244 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
247 /* Disable processor serial number: */
249 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
251 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
253 pr_notice("CPU serial number disabled.\n");
254 clear_cpu_cap(c
, X86_FEATURE_PN
);
256 /* Disabling the serial number may affect the cpuid level */
257 c
->cpuid_level
= cpuid_eax(0);
260 static int __init
x86_serial_nr_setup(char *s
)
262 disable_x86_serial_nr
= 0;
265 __setup("serialnumber", x86_serial_nr_setup
);
267 static inline int flag_is_changeable_p(u32 flag
)
271 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
276 static __init
int setup_disable_smep(char *arg
)
278 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
279 /* Check for things that depend on SMEP being enabled: */
280 check_mpx_erratum(&boot_cpu_data
);
283 __setup("nosmep", setup_disable_smep
);
285 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
287 if (cpu_has(c
, X86_FEATURE_SMEP
))
288 cr4_set_bits(X86_CR4_SMEP
);
291 static __init
int setup_disable_smap(char *arg
)
293 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
296 __setup("nosmap", setup_disable_smap
);
298 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
300 unsigned long eflags
= native_save_fl();
302 /* This should have been cleared long ago */
303 BUG_ON(eflags
& X86_EFLAGS_AC
);
305 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
306 #ifdef CONFIG_X86_SMAP
307 cr4_set_bits(X86_CR4_SMAP
);
309 cr4_clear_bits(X86_CR4_SMAP
);
315 * Protection Keys are not available in 32-bit mode.
317 static bool pku_disabled
;
319 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
321 /* check the boot processor, plus compile options for PKU: */
322 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
324 /* checks the actual processor's cpuid bits: */
325 if (!cpu_has(c
, X86_FEATURE_PKU
))
330 cr4_set_bits(X86_CR4_PKE
);
332 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
333 * cpuid bit to be set. We need to ensure that we
334 * update that bit in this CPU's "cpu_info".
339 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
340 static __init
int setup_disable_pku(char *arg
)
343 * Do not clear the X86_FEATURE_PKU bit. All of the
344 * runtime checks are against OSPKE so clearing the
347 * This way, we will see "pku" in cpuinfo, but not
348 * "ospke", which is exactly what we want. It shows
349 * that the CPU has PKU, but the OS has not enabled it.
350 * This happens to be exactly how a system would look
351 * if we disabled the config option.
353 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
357 __setup("nopku", setup_disable_pku
);
358 #endif /* CONFIG_X86_64 */
361 * Some CPU features depend on higher CPUID levels, which may not always
362 * be available due to CPUID level capping or broken virtualization
363 * software. Add those features to this table to auto-disable them.
365 struct cpuid_dependent_feature
{
370 static const struct cpuid_dependent_feature
371 cpuid_dependent_features
[] = {
372 { X86_FEATURE_MWAIT
, 0x00000005 },
373 { X86_FEATURE_DCA
, 0x00000009 },
374 { X86_FEATURE_XSAVE
, 0x0000000d },
378 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
380 const struct cpuid_dependent_feature
*df
;
382 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
384 if (!cpu_has(c
, df
->feature
))
387 * Note: cpuid_level is set to -1 if unavailable, but
388 * extended_extended_level is set to 0 if unavailable
389 * and the legitimate extended levels are all negative
390 * when signed; hence the weird messing around with
393 if (!((s32
)df
->level
< 0 ?
394 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
395 (s32
)df
->level
> (s32
)c
->cpuid_level
))
398 clear_cpu_cap(c
, df
->feature
);
402 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
403 x86_cap_flag(df
->feature
), df
->level
);
408 * Naming convention should be: <Name> [(<Codename>)]
409 * This table only is used unless init_<vendor>() below doesn't set it;
410 * in particular, if CPUID levels 0x80000002..4 are supported, this
414 /* Look up CPU names by table lookup. */
415 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
418 const struct legacy_cpu_model_info
*info
;
420 if (c
->x86_model
>= 16)
421 return NULL
; /* Range check */
426 info
= this_cpu
->legacy_models
;
428 while (info
->family
) {
429 if (info
->family
== c
->x86
)
430 return info
->model_names
[c
->x86_model
];
434 return NULL
; /* Not found */
437 __u32 cpu_caps_cleared
[NCAPINTS
];
438 __u32 cpu_caps_set
[NCAPINTS
];
440 void load_percpu_segment(int cpu
)
443 loadsegment(fs
, __KERNEL_PERCPU
);
445 __loadsegment_simple(gs
, 0);
446 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
448 load_stack_canary_segment();
452 * Current gdt points %fs at the "master" per-cpu area: after this,
453 * it's on the real one.
455 void switch_to_new_gdt(int cpu
)
457 struct desc_ptr gdt_descr
;
459 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
460 gdt_descr
.size
= GDT_SIZE
- 1;
461 load_gdt(&gdt_descr
);
462 /* Reload the per-cpu base */
464 load_percpu_segment(cpu
);
467 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
469 static void get_model_name(struct cpuinfo_x86
*c
)
474 if (c
->extended_cpuid_level
< 0x80000004)
477 v
= (unsigned int *)c
->x86_model_id
;
478 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
479 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
480 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
481 c
->x86_model_id
[48] = 0;
483 /* Trim whitespace */
484 p
= q
= s
= &c
->x86_model_id
[0];
490 /* Note the last non-whitespace index */
500 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
502 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
504 n
= c
->extended_cpuid_level
;
506 if (n
>= 0x80000005) {
507 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
508 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
510 /* On K8 L1 TLB is inclusive, so don't count it */
515 if (n
< 0x80000006) /* Some chips just has a large L1. */
518 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
522 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
524 /* do processor-specific cache resizing */
525 if (this_cpu
->legacy_cache_size
)
526 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
528 /* Allow user to override all this if necessary. */
529 if (cachesize_override
!= -1)
530 l2size
= cachesize_override
;
533 return; /* Again, no L2 cache is possible */
536 c
->x86_cache_size
= l2size
;
539 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
540 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
541 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
542 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
543 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
544 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
545 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
547 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
549 if (this_cpu
->c_detect_tlb
)
550 this_cpu
->c_detect_tlb(c
);
552 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
553 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
554 tlb_lli_4m
[ENTRIES
]);
556 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
557 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
558 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
561 void detect_ht(struct cpuinfo_x86
*c
)
564 u32 eax
, ebx
, ecx
, edx
;
565 int index_msb
, core_bits
;
568 if (!cpu_has(c
, X86_FEATURE_HT
))
571 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
574 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
577 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
579 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
581 if (smp_num_siblings
== 1) {
582 pr_info_once("CPU0: Hyper-Threading is disabled\n");
586 if (smp_num_siblings
<= 1)
589 index_msb
= get_count_order(smp_num_siblings
);
590 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
592 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
594 index_msb
= get_count_order(smp_num_siblings
);
596 core_bits
= get_count_order(c
->x86_max_cores
);
598 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
599 ((1 << core_bits
) - 1);
602 if (!printed
&& (c
->x86_max_cores
* smp_num_siblings
) > 1) {
603 pr_info("CPU: Physical Processor ID: %d\n",
605 pr_info("CPU: Processor Core ID: %d\n",
612 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
614 char *v
= c
->x86_vendor_id
;
617 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
621 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
622 (cpu_devs
[i
]->c_ident
[1] &&
623 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
625 this_cpu
= cpu_devs
[i
];
626 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
631 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
632 "CPU: Your system may be unstable.\n", v
);
634 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
635 this_cpu
= &default_cpu
;
638 void cpu_detect(struct cpuinfo_x86
*c
)
640 /* Get vendor name */
641 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
642 (unsigned int *)&c
->x86_vendor_id
[0],
643 (unsigned int *)&c
->x86_vendor_id
[8],
644 (unsigned int *)&c
->x86_vendor_id
[4]);
647 /* Intel-defined flags: level 0x00000001 */
648 if (c
->cpuid_level
>= 0x00000001) {
649 u32 junk
, tfms
, cap0
, misc
;
651 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
652 c
->x86
= x86_family(tfms
);
653 c
->x86_model
= x86_model(tfms
);
654 c
->x86_mask
= x86_stepping(tfms
);
656 if (cap0
& (1<<19)) {
657 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
658 c
->x86_cache_alignment
= c
->x86_clflush_size
;
663 static void apply_forced_caps(struct cpuinfo_x86
*c
)
667 for (i
= 0; i
< NCAPINTS
; i
++) {
668 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
669 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
673 void get_cpu_cap(struct cpuinfo_x86
*c
)
675 u32 eax
, ebx
, ecx
, edx
;
677 /* Intel-defined flags: level 0x00000001 */
678 if (c
->cpuid_level
>= 0x00000001) {
679 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
681 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
682 c
->x86_capability
[CPUID_1_EDX
] = edx
;
685 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
686 if (c
->cpuid_level
>= 0x00000006)
687 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
689 /* Additional Intel-defined flags: level 0x00000007 */
690 if (c
->cpuid_level
>= 0x00000007) {
691 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
692 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
693 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
696 /* Extended state features: level 0x0000000d */
697 if (c
->cpuid_level
>= 0x0000000d) {
698 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
700 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
703 /* Additional Intel-defined flags: level 0x0000000F */
704 if (c
->cpuid_level
>= 0x0000000F) {
706 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
707 cpuid_count(0x0000000F, 0, &eax
, &ebx
, &ecx
, &edx
);
708 c
->x86_capability
[CPUID_F_0_EDX
] = edx
;
710 if (cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
711 /* will be overridden if occupancy monitoring exists */
712 c
->x86_cache_max_rmid
= ebx
;
714 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
715 cpuid_count(0x0000000F, 1, &eax
, &ebx
, &ecx
, &edx
);
716 c
->x86_capability
[CPUID_F_1_EDX
] = edx
;
718 if ((cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
)) ||
719 ((cpu_has(c
, X86_FEATURE_CQM_MBM_TOTAL
)) ||
720 (cpu_has(c
, X86_FEATURE_CQM_MBM_LOCAL
)))) {
721 c
->x86_cache_max_rmid
= ecx
;
722 c
->x86_cache_occ_scale
= ebx
;
725 c
->x86_cache_max_rmid
= -1;
726 c
->x86_cache_occ_scale
= -1;
730 /* AMD-defined flags: level 0x80000001 */
731 eax
= cpuid_eax(0x80000000);
732 c
->extended_cpuid_level
= eax
;
734 if ((eax
& 0xffff0000) == 0x80000000) {
735 if (eax
>= 0x80000001) {
736 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
738 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
739 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
743 if (c
->extended_cpuid_level
>= 0x80000007) {
744 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
746 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
750 if (c
->extended_cpuid_level
>= 0x80000008) {
751 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
753 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
754 c
->x86_phys_bits
= eax
& 0xff;
755 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
758 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
759 c
->x86_phys_bits
= 36;
762 if (c
->extended_cpuid_level
>= 0x8000000a)
763 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
765 init_scattered_cpuid_features(c
);
768 * Clear/Set all flags overridden by options, after probe.
769 * This needs to happen each time we re-probe, which may happen
770 * several times during CPU initialization.
772 apply_forced_caps(c
);
775 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
781 * First of all, decide if this is a 486 or higher
782 * It's a 486 if we can modify the AC flag
784 if (flag_is_changeable_p(X86_EFLAGS_AC
))
789 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
790 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
791 c
->x86_vendor_id
[0] = 0;
792 cpu_devs
[i
]->c_identify(c
);
793 if (c
->x86_vendor_id
[0]) {
802 * Do minimum CPU detection early.
803 * Fields really needed: vendor, cpuid_level, family, model, mask,
805 * The others are not touched to avoid unwanted side effects.
807 * WARNING: this function is only called on the BP. Don't add code here
808 * that is supposed to run on all CPUs.
810 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
813 c
->x86_clflush_size
= 64;
814 c
->x86_phys_bits
= 36;
815 c
->x86_virt_bits
= 48;
817 c
->x86_clflush_size
= 32;
818 c
->x86_phys_bits
= 32;
819 c
->x86_virt_bits
= 32;
821 c
->x86_cache_alignment
= c
->x86_clflush_size
;
823 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
824 c
->extended_cpuid_level
= 0;
826 /* cyrix could have cpuid enabled via c_identify()*/
827 if (have_cpuid_p()) {
831 setup_force_cpu_cap(X86_FEATURE_CPUID
);
833 if (this_cpu
->c_early_init
)
834 this_cpu
->c_early_init(c
);
837 filter_cpuid_features(c
, false);
839 if (this_cpu
->c_bsp_init
)
840 this_cpu
->c_bsp_init(c
);
842 identify_cpu_without_cpuid(c
);
843 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
846 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
850 void __init
early_cpu_init(void)
852 const struct cpu_dev
*const *cdev
;
855 #ifdef CONFIG_PROCESSOR_SELECT
856 pr_info("KERNEL supported cpus:\n");
859 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
860 const struct cpu_dev
*cpudev
= *cdev
;
862 if (count
>= X86_VENDOR_NUM
)
864 cpu_devs
[count
] = cpudev
;
867 #ifdef CONFIG_PROCESSOR_SELECT
871 for (j
= 0; j
< 2; j
++) {
872 if (!cpudev
->c_ident
[j
])
874 pr_info(" %s %s\n", cpudev
->c_vendor
,
880 early_identify_cpu(&boot_cpu_data
);
884 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
885 * unfortunately, that's not true in practice because of early VIA
886 * chips and (more importantly) broken virtualizers that are not easy
887 * to detect. In the latter case it doesn't even *fail* reliably, so
888 * probing for it doesn't even work. Disable it completely on 32-bit
889 * unless we can find a reliable way to detect all the broken cases.
890 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
892 static void detect_nopl(struct cpuinfo_x86
*c
)
895 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
897 set_cpu_cap(c
, X86_FEATURE_NOPL
);
901 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
905 * Empirically, writing zero to a segment selector on AMD does
906 * not clear the base, whereas writing zero to a segment
907 * selector on Intel does clear the base. Intel's behavior
908 * allows slightly faster context switches in the common case
909 * where GS is unused by the prev and next threads.
911 * Since neither vendor documents this anywhere that I can see,
912 * detect it directly instead of hardcoding the choice by
915 * I've designated AMD's behavior as the "bug" because it's
916 * counterintuitive and less friendly.
919 unsigned long old_base
, tmp
;
920 rdmsrl(MSR_FS_BASE
, old_base
);
921 wrmsrl(MSR_FS_BASE
, 1);
923 rdmsrl(MSR_FS_BASE
, tmp
);
925 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
926 wrmsrl(MSR_FS_BASE
, old_base
);
930 static void generic_identify(struct cpuinfo_x86
*c
)
932 c
->extended_cpuid_level
= 0;
935 identify_cpu_without_cpuid(c
);
937 /* cyrix could have cpuid enabled via c_identify()*/
947 if (c
->cpuid_level
>= 0x00000001) {
948 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
951 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
953 c
->apicid
= c
->initial_apicid
;
956 c
->phys_proc_id
= c
->initial_apicid
;
959 get_model_name(c
); /* Default name */
963 detect_null_seg_behavior(c
);
966 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
967 * systems that run Linux at CPL > 0 may or may not have the
968 * issue, but, even if they have the issue, there's absolutely
969 * nothing we can do about it because we can't use the real IRET
972 * NB: For the time being, only 32-bit kernels support
973 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
974 * whether to apply espfix using paravirt hooks. If any
975 * non-paravirt system ever shows up that does *not* have the
976 * ESPFIX issue, we can change this.
979 # ifdef CONFIG_PARAVIRT
981 extern void native_iret(void);
982 if (pv_cpu_ops
.iret
== native_iret
)
983 set_cpu_bug(c
, X86_BUG_ESPFIX
);
986 set_cpu_bug(c
, X86_BUG_ESPFIX
);
991 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
994 * The heavy lifting of max_rmid and cache_occ_scale are handled
995 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
996 * in case CQM bits really aren't there in this CPU.
998 if (c
!= &boot_cpu_data
) {
999 boot_cpu_data
.x86_cache_max_rmid
=
1000 min(boot_cpu_data
.x86_cache_max_rmid
,
1001 c
->x86_cache_max_rmid
);
1006 * Validate that ACPI/mptables have the same information about the
1007 * effective APIC id and update the package map.
1009 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1012 unsigned int apicid
, cpu
= smp_processor_id();
1014 apicid
= apic
->cpu_present_to_apicid(cpu
);
1016 if (apicid
!= c
->apicid
) {
1017 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1018 cpu
, apicid
, c
->initial_apicid
);
1020 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1022 c
->logical_proc_id
= 0;
1027 * This does the hard work of actually picking apart the CPU stuff...
1029 static void identify_cpu(struct cpuinfo_x86
*c
)
1033 c
->loops_per_jiffy
= loops_per_jiffy
;
1034 c
->x86_cache_size
= -1;
1035 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1036 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
1037 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1038 c
->x86_model_id
[0] = '\0'; /* Unset */
1039 c
->x86_max_cores
= 1;
1040 c
->x86_coreid_bits
= 0;
1042 #ifdef CONFIG_X86_64
1043 c
->x86_clflush_size
= 64;
1044 c
->x86_phys_bits
= 36;
1045 c
->x86_virt_bits
= 48;
1047 c
->cpuid_level
= -1; /* CPUID not detected */
1048 c
->x86_clflush_size
= 32;
1049 c
->x86_phys_bits
= 32;
1050 c
->x86_virt_bits
= 32;
1052 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1053 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
1055 generic_identify(c
);
1057 if (this_cpu
->c_identify
)
1058 this_cpu
->c_identify(c
);
1060 /* Clear/Set all flags overridden by options, after probe */
1061 apply_forced_caps(c
);
1063 #ifdef CONFIG_X86_64
1064 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1068 * Vendor-specific initialization. In this section we
1069 * canonicalize the feature flags, meaning if there are
1070 * features a certain CPU supports which CPUID doesn't
1071 * tell us, CPUID claiming incorrect flags, or other bugs,
1072 * we handle them here.
1074 * At the end of this section, c->x86_capability better
1075 * indicate the features this CPU genuinely supports!
1077 if (this_cpu
->c_init
)
1078 this_cpu
->c_init(c
);
1080 clear_sched_clock_stable();
1082 /* Disable the PN if appropriate */
1083 squash_the_stupid_serial_number(c
);
1085 /* Set up SMEP/SMAP */
1090 * The vendor-specific functions might have changed features.
1091 * Now we do "generic changes."
1094 /* Filter out anything that depends on CPUID levels we don't have */
1095 filter_cpuid_features(c
, true);
1097 /* If the model name is still unset, do table lookup. */
1098 if (!c
->x86_model_id
[0]) {
1100 p
= table_lookup_model(c
);
1102 strcpy(c
->x86_model_id
, p
);
1104 /* Last resort... */
1105 sprintf(c
->x86_model_id
, "%02x/%02x",
1106 c
->x86
, c
->x86_model
);
1109 #ifdef CONFIG_X86_64
1115 x86_init_cache_qos(c
);
1119 * Clear/Set all flags overridden by options, need do it
1120 * before following smp all cpus cap AND.
1122 apply_forced_caps(c
);
1125 * On SMP, boot_cpu_data holds the common feature set between
1126 * all CPUs; so make sure that we indicate which features are
1127 * common between the CPUs. The first time this routine gets
1128 * executed, c == &boot_cpu_data.
1130 if (c
!= &boot_cpu_data
) {
1131 /* AND the already accumulated flags with these */
1132 for (i
= 0; i
< NCAPINTS
; i
++)
1133 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1135 /* OR, i.e. replicate the bug flags */
1136 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1137 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1140 /* Init Machine Check Exception if available. */
1143 select_idle_routine(c
);
1146 numa_add_cpu(smp_processor_id());
1151 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1152 * on 32-bit kernels:
1154 #ifdef CONFIG_X86_32
1155 void enable_sep_cpu(void)
1157 struct tss_struct
*tss
;
1160 if (!boot_cpu_has(X86_FEATURE_SEP
))
1164 tss
= &per_cpu(cpu_tss
, cpu
);
1167 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1168 * see the big comment in struct x86_hw_tss's definition.
1171 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1172 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1174 wrmsr(MSR_IA32_SYSENTER_ESP
,
1175 (unsigned long)tss
+ offsetofend(struct tss_struct
, SYSENTER_stack
),
1178 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1184 void __init
identify_boot_cpu(void)
1186 identify_cpu(&boot_cpu_data
);
1187 #ifdef CONFIG_X86_32
1191 cpu_detect_tlb(&boot_cpu_data
);
1194 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1196 BUG_ON(c
== &boot_cpu_data
);
1198 #ifdef CONFIG_X86_32
1202 validate_apic_and_package_id(c
);
1205 static __init
int setup_noclflush(char *arg
)
1207 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1208 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1211 __setup("noclflush", setup_noclflush
);
1213 void print_cpu_info(struct cpuinfo_x86
*c
)
1215 const char *vendor
= NULL
;
1217 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1218 vendor
= this_cpu
->c_vendor
;
1220 if (c
->cpuid_level
>= 0)
1221 vendor
= c
->x86_vendor_id
;
1224 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1225 pr_cont("%s ", vendor
);
1227 if (c
->x86_model_id
[0])
1228 pr_cont("%s", c
->x86_model_id
);
1230 pr_cont("%d86", c
->x86
);
1232 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1234 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
1235 pr_cont(", stepping: 0x%x)\n", c
->x86_mask
);
1240 static __init
int setup_disablecpuid(char *arg
)
1244 if (get_option(&arg
, &bit
) && bit
>= 0 && bit
< NCAPINTS
* 32)
1245 setup_clear_cpu_cap(bit
);
1251 __setup("clearcpuid=", setup_disablecpuid
);
1253 #ifdef CONFIG_X86_64
1254 struct desc_ptr idt_descr __ro_after_init
= {
1255 .size
= NR_VECTORS
* 16 - 1,
1256 .address
= (unsigned long) idt_table
,
1258 const struct desc_ptr debug_idt_descr
= {
1259 .size
= NR_VECTORS
* 16 - 1,
1260 .address
= (unsigned long) debug_idt_table
,
1263 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
1264 irq_stack_union
) __aligned(PAGE_SIZE
) __visible
;
1267 * The following percpu variables are hot. Align current_task to
1268 * cacheline size such that they fall in the same cacheline.
1270 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1272 EXPORT_PER_CPU_SYMBOL(current_task
);
1274 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
1275 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
;
1277 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1279 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1280 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1283 * Special IST stacks which the CPU switches to when it calls
1284 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1285 * limit), all of them are 4K, except the debug stack which
1288 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
1289 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1290 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1293 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1294 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
]);
1296 /* May not be marked __init: used by software suspend */
1297 void syscall_init(void)
1299 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1300 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1302 #ifdef CONFIG_IA32_EMULATION
1303 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1305 * This only works on Intel CPUs.
1306 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1307 * This does not cause SYSENTER to jump to the wrong location, because
1308 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1310 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1311 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1312 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1314 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1315 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1316 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1317 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1320 /* Flags to clear on syscall */
1321 wrmsrl(MSR_SYSCALL_MASK
,
1322 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1323 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1327 * Copies of the original ist values from the tss are only accessed during
1328 * debugging, no special alignment required.
1330 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1332 static DEFINE_PER_CPU(unsigned long, debug_stack_addr
);
1333 DEFINE_PER_CPU(int, debug_stack_usage
);
1335 int is_debug_stack(unsigned long addr
)
1337 return __this_cpu_read(debug_stack_usage
) ||
1338 (addr
<= __this_cpu_read(debug_stack_addr
) &&
1339 addr
> (__this_cpu_read(debug_stack_addr
) - DEBUG_STKSZ
));
1341 NOKPROBE_SYMBOL(is_debug_stack
);
1343 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1345 void debug_stack_set_zero(void)
1347 this_cpu_inc(debug_idt_ctr
);
1350 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1352 void debug_stack_reset(void)
1354 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1356 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1359 NOKPROBE_SYMBOL(debug_stack_reset
);
1361 #else /* CONFIG_X86_64 */
1363 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1364 EXPORT_PER_CPU_SYMBOL(current_task
);
1365 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1366 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1369 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1370 * the top of the kernel stack. Use an extra percpu variable to track the
1371 * top of the kernel stack directly.
1373 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1374 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1375 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1377 #ifdef CONFIG_CC_STACKPROTECTOR
1378 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1381 #endif /* CONFIG_X86_64 */
1384 * Clear all 6 debug registers:
1386 static void clear_all_debug_regs(void)
1390 for (i
= 0; i
< 8; i
++) {
1391 /* Ignore db4, db5 */
1392 if ((i
== 4) || (i
== 5))
1401 * Restore debug regs if using kgdbwait and you have a kernel debugger
1402 * connection established.
1404 static void dbg_restore_debug_regs(void)
1406 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1407 arch_kgdb_ops
.correct_hw_break();
1409 #else /* ! CONFIG_KGDB */
1410 #define dbg_restore_debug_regs()
1411 #endif /* ! CONFIG_KGDB */
1413 static void wait_for_master_cpu(int cpu
)
1417 * wait for ACK from master CPU before continuing
1418 * with AP initialization
1420 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1421 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1427 * cpu_init() initializes state that is per-CPU. Some data is already
1428 * initialized (naturally) in the bootstrap process, such as the GDT
1429 * and IDT. We reload them nevertheless, this function acts as a
1430 * 'CPU state barrier', nothing should get across.
1431 * A lot of state is already set up in PDA init for 64 bit
1433 #ifdef CONFIG_X86_64
1437 struct orig_ist
*oist
;
1438 struct task_struct
*me
;
1439 struct tss_struct
*t
;
1441 int cpu
= raw_smp_processor_id();
1444 wait_for_master_cpu(cpu
);
1447 * Initialize the CR4 shadow before doing anything that could
1455 t
= &per_cpu(cpu_tss
, cpu
);
1456 oist
= &per_cpu(orig_ist
, cpu
);
1459 if (this_cpu_read(numa_node
) == 0 &&
1460 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1461 set_numa_node(early_cpu_to_node(cpu
));
1466 pr_debug("Initializing CPU#%d\n", cpu
);
1468 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1471 * Initialize the per-CPU GDT with the boot GDT,
1472 * and set up the GDT descriptor:
1475 switch_to_new_gdt(cpu
);
1480 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1483 wrmsrl(MSR_FS_BASE
, 0);
1484 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1491 * set up and load the per-CPU TSS
1493 if (!oist
->ist
[0]) {
1494 char *estacks
= per_cpu(exception_stacks
, cpu
);
1496 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1497 estacks
+= exception_stack_sizes
[v
];
1498 oist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1499 (unsigned long)estacks
;
1500 if (v
== DEBUG_STACK
-1)
1501 per_cpu(debug_stack_addr
, cpu
) = (unsigned long)estacks
;
1505 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1508 * <= is required because the CPU will access up to
1509 * 8 bits beyond the end of the IO permission bitmap.
1511 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1512 t
->io_bitmap
[i
] = ~0UL;
1515 me
->active_mm
= &init_mm
;
1517 enter_lazy_tlb(&init_mm
, me
);
1519 load_sp0(t
, ¤t
->thread
);
1520 set_tss_desc(cpu
, t
);
1522 load_mm_ldt(&init_mm
);
1524 clear_all_debug_regs();
1525 dbg_restore_debug_regs();
1537 int cpu
= smp_processor_id();
1538 struct task_struct
*curr
= current
;
1539 struct tss_struct
*t
= &per_cpu(cpu_tss
, cpu
);
1540 struct thread_struct
*thread
= &curr
->thread
;
1542 wait_for_master_cpu(cpu
);
1545 * Initialize the CR4 shadow before doing anything that could
1550 show_ucode_info_early();
1552 pr_info("Initializing CPU#%d\n", cpu
);
1554 if (cpu_feature_enabled(X86_FEATURE_VME
) ||
1555 boot_cpu_has(X86_FEATURE_TSC
) ||
1556 boot_cpu_has(X86_FEATURE_DE
))
1557 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1560 switch_to_new_gdt(cpu
);
1563 * Set up and load the per-CPU TSS and LDT
1566 curr
->active_mm
= &init_mm
;
1568 enter_lazy_tlb(&init_mm
, curr
);
1570 load_sp0(t
, thread
);
1571 set_tss_desc(cpu
, t
);
1573 load_mm_ldt(&init_mm
);
1575 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1577 #ifdef CONFIG_DOUBLEFAULT
1578 /* Set up doublefault TSS pointer in the GDT */
1579 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1582 clear_all_debug_regs();
1583 dbg_restore_debug_regs();
1589 static void bsp_resume(void)
1591 if (this_cpu
->c_bsp_resume
)
1592 this_cpu
->c_bsp_resume(&boot_cpu_data
);
1595 static struct syscore_ops cpu_syscore_ops
= {
1596 .resume
= bsp_resume
,
1599 static int __init
init_cpu_syscore(void)
1601 register_syscore_ops(&cpu_syscore_ops
);
1604 core_initcall(init_cpu_syscore
);