1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
25 #include <asm/stackprotector.h>
26 #include <asm/perf_event.h>
27 #include <asm/mmu_context.h>
28 #include <asm/doublefault.h>
29 #include <asm/archrandom.h>
30 #include <asm/hypervisor.h>
31 #include <asm/processor.h>
32 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/sections.h>
35 #include <asm/vsyscall.h>
36 #include <linux/topology.h>
37 #include <linux/cpumask.h>
38 #include <linux/pgtable.h>
39 #include <linux/atomic.h>
40 #include <asm/proto.h>
41 #include <asm/setup.h>
44 #include <asm/fpu/internal.h>
46 #include <asm/hwcap2.h>
47 #include <linux/numa.h>
53 #include <asm/memtype.h>
54 #include <asm/microcode.h>
55 #include <asm/microcode_intel.h>
56 #include <asm/intel-family.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/uv/uv.h>
62 u32 elf_hwcap2 __read_mostly
;
64 /* all of these masks are initialized in setup_cpu_local_masks() */
65 cpumask_var_t cpu_initialized_mask
;
66 cpumask_var_t cpu_callout_mask
;
67 cpumask_var_t cpu_callin_mask
;
69 /* representing cpus for which sibling maps can be computed */
70 cpumask_var_t cpu_sibling_setup_mask
;
72 /* Number of siblings per CPU package */
73 int smp_num_siblings
= 1;
74 EXPORT_SYMBOL(smp_num_siblings
);
76 /* Last level cache ID of each logical CPU */
77 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
79 /* correctly size the local cpu masks */
80 void __init
setup_cpu_local_masks(void)
82 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
83 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
84 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
88 static void default_init(struct cpuinfo_x86
*c
)
91 cpu_detect_cache_sizes(c
);
93 /* Not much we can do here... */
94 /* Check if at least it has cpuid */
95 if (c
->cpuid_level
== -1) {
96 /* No cpuid. It must be an ancient CPU */
98 strcpy(c
->x86_model_id
, "486");
100 strcpy(c
->x86_model_id
, "386");
105 static const struct cpu_dev default_cpu
= {
106 .c_init
= default_init
,
107 .c_vendor
= "Unknown",
108 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
111 static const struct cpu_dev
*this_cpu
= &default_cpu
;
113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
116 * We need valid kernel segments for data and code in long mode too
117 * IRET will check the segment types kkeil 2000/10/28
118 * Also sysret mandates a special GDT layout
120 * TLS descriptors are currently at a different place compared to i386.
121 * Hopefully nobody expects them at a fixed place (Wine?)
123 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
124 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
126 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
130 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
132 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
135 * Segments used for calling PnP BIOS have byte granularity.
136 * They code segments and data segments have fixed 64k limits,
137 * the transfer segment sizes are set at run time.
140 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
142 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
144 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
146 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
148 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
150 * The APM segments have byte granularity and their bases
151 * are set at run time. All have 64k limits.
154 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
156 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
158 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
160 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
161 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 GDT_STACK_CANARY_INIT
165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
168 static int __init
x86_nopcid_setup(char *s
)
170 /* nopcid doesn't accept parameters */
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_PCID
))
178 setup_clear_cpu_cap(X86_FEATURE_PCID
);
179 pr_info("nopcid: PCID feature disabled\n");
182 early_param("nopcid", x86_nopcid_setup
);
185 static int __init
x86_noinvpcid_setup(char *s
)
187 /* noinvpcid doesn't accept parameters */
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
195 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
196 pr_info("noinvpcid: INVPCID feature disabled\n");
199 early_param("noinvpcid", x86_noinvpcid_setup
);
202 static int cachesize_override
= -1;
203 static int disable_x86_serial_nr
= 1;
205 static int __init
cachesize_setup(char *str
)
207 get_option(&str
, &cachesize_override
);
210 __setup("cachesize=", cachesize_setup
);
212 static int __init
x86_sep_setup(char *s
)
214 setup_clear_cpu_cap(X86_FEATURE_SEP
);
217 __setup("nosep", x86_sep_setup
);
219 /* Standard macro to see if a specific flag is changeable */
220 static inline int flag_is_changeable_p(u32 flag
)
225 * Cyrix and IDT cpus allow disabling of CPUID
226 * so the code below may return different results
227 * when it is executed before and after enabling
228 * the CPUID. Add "volatile" to not allow gcc to
229 * optimize the subsequent calls to this function.
231 asm volatile ("pushfl \n\t"
242 : "=&r" (f1
), "=&r" (f2
)
245 return ((f1
^f2
) & flag
) != 0;
248 /* Probe for the CPUID instruction */
249 int have_cpuid_p(void)
251 return flag_is_changeable_p(X86_EFLAGS_ID
);
254 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
256 unsigned long lo
, hi
;
258 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
261 /* Disable processor serial number: */
263 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
265 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
267 pr_notice("CPU serial number disabled.\n");
268 clear_cpu_cap(c
, X86_FEATURE_PN
);
270 /* Disabling the serial number may affect the cpuid level */
271 c
->cpuid_level
= cpuid_eax(0);
274 static int __init
x86_serial_nr_setup(char *s
)
276 disable_x86_serial_nr
= 0;
279 __setup("serialnumber", x86_serial_nr_setup
);
281 static inline int flag_is_changeable_p(u32 flag
)
285 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
290 static __init
int setup_disable_smep(char *arg
)
292 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
295 __setup("nosmep", setup_disable_smep
);
297 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
299 if (cpu_has(c
, X86_FEATURE_SMEP
))
300 cr4_set_bits(X86_CR4_SMEP
);
303 static __init
int setup_disable_smap(char *arg
)
305 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
308 __setup("nosmap", setup_disable_smap
);
310 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
312 unsigned long eflags
= native_save_fl();
314 /* This should have been cleared long ago */
315 BUG_ON(eflags
& X86_EFLAGS_AC
);
317 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
318 #ifdef CONFIG_X86_SMAP
319 cr4_set_bits(X86_CR4_SMAP
);
321 cr4_clear_bits(X86_CR4_SMAP
);
326 static __always_inline
void setup_umip(struct cpuinfo_x86
*c
)
328 /* Check the boot processor, plus build option for UMIP. */
329 if (!cpu_feature_enabled(X86_FEATURE_UMIP
))
332 /* Check the current processor's cpuid bits. */
333 if (!cpu_has(c
, X86_FEATURE_UMIP
))
336 cr4_set_bits(X86_CR4_UMIP
);
338 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
344 * Make sure UMIP is disabled in case it was enabled in a
345 * previous boot (e.g., via kexec).
347 cr4_clear_bits(X86_CR4_UMIP
);
350 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning
);
351 static unsigned long cr4_pinned_bits __ro_after_init
;
353 void native_write_cr0(unsigned long val
)
355 unsigned long bits_missing
= 0;
358 asm volatile("mov %0,%%cr0": "+r" (val
), "+m" (__force_order
));
360 if (static_branch_likely(&cr_pinning
)) {
361 if (unlikely((val
& X86_CR0_WP
) != X86_CR0_WP
)) {
362 bits_missing
= X86_CR0_WP
;
366 /* Warn after we've set the missing bits. */
367 WARN_ONCE(bits_missing
, "CR0 WP bit went missing!?\n");
370 EXPORT_SYMBOL(native_write_cr0
);
372 void native_write_cr4(unsigned long val
)
374 unsigned long bits_missing
= 0;
377 asm volatile("mov %0,%%cr4": "+r" (val
), "+m" (cr4_pinned_bits
));
379 if (static_branch_likely(&cr_pinning
)) {
380 if (unlikely((val
& cr4_pinned_bits
) != cr4_pinned_bits
)) {
381 bits_missing
= ~val
& cr4_pinned_bits
;
385 /* Warn after we've set the missing bits. */
386 WARN_ONCE(bits_missing
, "CR4 bits went missing: %lx!?\n",
390 #if IS_MODULE(CONFIG_LKDTM)
391 EXPORT_SYMBOL_GPL(native_write_cr4
);
394 void cr4_update_irqsoff(unsigned long set
, unsigned long clear
)
396 unsigned long newval
, cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
398 lockdep_assert_irqs_disabled();
400 newval
= (cr4
& ~clear
) | set
;
402 this_cpu_write(cpu_tlbstate
.cr4
, newval
);
406 EXPORT_SYMBOL(cr4_update_irqsoff
);
408 /* Read the CR4 shadow. */
409 unsigned long cr4_read_shadow(void)
411 return this_cpu_read(cpu_tlbstate
.cr4
);
413 EXPORT_SYMBOL_GPL(cr4_read_shadow
);
417 unsigned long cr4
= __read_cr4();
419 if (boot_cpu_has(X86_FEATURE_PCID
))
420 cr4
|= X86_CR4_PCIDE
;
421 if (static_branch_likely(&cr_pinning
))
422 cr4
|= cr4_pinned_bits
;
426 /* Initialize cr4 shadow for this CPU. */
427 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
431 * Once CPU feature detection is finished (and boot params have been
432 * parsed), record any of the sensitive CR bits that are set, and
435 static void __init
setup_cr_pinning(void)
439 mask
= (X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_UMIP
);
440 cr4_pinned_bits
= this_cpu_read(cpu_tlbstate
.cr4
) & mask
;
441 static_key_enable(&cr_pinning
.key
);
445 * Protection Keys are not available in 32-bit mode.
447 static bool pku_disabled
;
449 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
451 struct pkru_state
*pk
;
453 /* check the boot processor, plus compile options for PKU: */
454 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
456 /* checks the actual processor's cpuid bits: */
457 if (!cpu_has(c
, X86_FEATURE_PKU
))
462 cr4_set_bits(X86_CR4_PKE
);
463 pk
= get_xsave_addr(&init_fpstate
.xsave
, XFEATURE_PKRU
);
465 pk
->pkru
= init_pkru_value
;
467 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
468 * cpuid bit to be set. We need to ensure that we
469 * update that bit in this CPU's "cpu_info".
471 set_cpu_cap(c
, X86_FEATURE_OSPKE
);
474 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
475 static __init
int setup_disable_pku(char *arg
)
478 * Do not clear the X86_FEATURE_PKU bit. All of the
479 * runtime checks are against OSPKE so clearing the
482 * This way, we will see "pku" in cpuinfo, but not
483 * "ospke", which is exactly what we want. It shows
484 * that the CPU has PKU, but the OS has not enabled it.
485 * This happens to be exactly how a system would look
486 * if we disabled the config option.
488 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
492 __setup("nopku", setup_disable_pku
);
493 #endif /* CONFIG_X86_64 */
496 * Some CPU features depend on higher CPUID levels, which may not always
497 * be available due to CPUID level capping or broken virtualization
498 * software. Add those features to this table to auto-disable them.
500 struct cpuid_dependent_feature
{
505 static const struct cpuid_dependent_feature
506 cpuid_dependent_features
[] = {
507 { X86_FEATURE_MWAIT
, 0x00000005 },
508 { X86_FEATURE_DCA
, 0x00000009 },
509 { X86_FEATURE_XSAVE
, 0x0000000d },
513 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
515 const struct cpuid_dependent_feature
*df
;
517 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
519 if (!cpu_has(c
, df
->feature
))
522 * Note: cpuid_level is set to -1 if unavailable, but
523 * extended_extended_level is set to 0 if unavailable
524 * and the legitimate extended levels are all negative
525 * when signed; hence the weird messing around with
528 if (!((s32
)df
->level
< 0 ?
529 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
530 (s32
)df
->level
> (s32
)c
->cpuid_level
))
533 clear_cpu_cap(c
, df
->feature
);
537 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
538 x86_cap_flag(df
->feature
), df
->level
);
543 * Naming convention should be: <Name> [(<Codename>)]
544 * This table only is used unless init_<vendor>() below doesn't set it;
545 * in particular, if CPUID levels 0x80000002..4 are supported, this
549 /* Look up CPU names by table lookup. */
550 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
553 const struct legacy_cpu_model_info
*info
;
555 if (c
->x86_model
>= 16)
556 return NULL
; /* Range check */
561 info
= this_cpu
->legacy_models
;
563 while (info
->family
) {
564 if (info
->family
== c
->x86
)
565 return info
->model_names
[c
->x86_model
];
569 return NULL
; /* Not found */
572 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
573 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
574 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
576 void load_percpu_segment(int cpu
)
579 loadsegment(fs
, __KERNEL_PERCPU
);
581 __loadsegment_simple(gs
, 0);
582 wrmsrl(MSR_GS_BASE
, cpu_kernelmode_gs_base(cpu
));
584 load_stack_canary_segment();
588 /* The 32-bit entry code needs to find cpu_entry_area. */
589 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
592 /* Load the original GDT from the per-cpu structure */
593 void load_direct_gdt(int cpu
)
595 struct desc_ptr gdt_descr
;
597 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
598 gdt_descr
.size
= GDT_SIZE
- 1;
599 load_gdt(&gdt_descr
);
601 EXPORT_SYMBOL_GPL(load_direct_gdt
);
603 /* Load a fixmap remapping of the per-cpu GDT */
604 void load_fixmap_gdt(int cpu
)
606 struct desc_ptr gdt_descr
;
608 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
609 gdt_descr
.size
= GDT_SIZE
- 1;
610 load_gdt(&gdt_descr
);
612 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
615 * Current gdt points %fs at the "master" per-cpu area: after this,
616 * it's on the real one.
618 void switch_to_new_gdt(int cpu
)
620 /* Load the original GDT */
621 load_direct_gdt(cpu
);
622 /* Reload the per-cpu base */
623 load_percpu_segment(cpu
);
626 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
628 static void get_model_name(struct cpuinfo_x86
*c
)
633 if (c
->extended_cpuid_level
< 0x80000004)
636 v
= (unsigned int *)c
->x86_model_id
;
637 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
638 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
639 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
640 c
->x86_model_id
[48] = 0;
642 /* Trim whitespace */
643 p
= q
= s
= &c
->x86_model_id
[0];
649 /* Note the last non-whitespace index */
659 void detect_num_cpu_cores(struct cpuinfo_x86
*c
)
661 unsigned int eax
, ebx
, ecx
, edx
;
663 c
->x86_max_cores
= 1;
664 if (!IS_ENABLED(CONFIG_SMP
) || c
->cpuid_level
< 4)
667 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
669 c
->x86_max_cores
= (eax
>> 26) + 1;
672 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
674 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
676 n
= c
->extended_cpuid_level
;
678 if (n
>= 0x80000005) {
679 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
680 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
682 /* On K8 L1 TLB is inclusive, so don't count it */
687 if (n
< 0x80000006) /* Some chips just has a large L1. */
690 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
694 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
696 /* do processor-specific cache resizing */
697 if (this_cpu
->legacy_cache_size
)
698 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
700 /* Allow user to override all this if necessary. */
701 if (cachesize_override
!= -1)
702 l2size
= cachesize_override
;
705 return; /* Again, no L2 cache is possible */
708 c
->x86_cache_size
= l2size
;
711 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
712 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
713 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
714 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
715 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
716 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
717 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
719 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
721 if (this_cpu
->c_detect_tlb
)
722 this_cpu
->c_detect_tlb(c
);
724 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
725 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
726 tlb_lli_4m
[ENTRIES
]);
728 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
729 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
730 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
733 int detect_ht_early(struct cpuinfo_x86
*c
)
736 u32 eax
, ebx
, ecx
, edx
;
738 if (!cpu_has(c
, X86_FEATURE_HT
))
741 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
744 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
747 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
749 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
750 if (smp_num_siblings
== 1)
751 pr_info_once("CPU0: Hyper-Threading is disabled\n");
756 void detect_ht(struct cpuinfo_x86
*c
)
759 int index_msb
, core_bits
;
761 if (detect_ht_early(c
) < 0)
764 index_msb
= get_count_order(smp_num_siblings
);
765 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
767 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
769 index_msb
= get_count_order(smp_num_siblings
);
771 core_bits
= get_count_order(c
->x86_max_cores
);
773 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
774 ((1 << core_bits
) - 1);
778 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
780 char *v
= c
->x86_vendor_id
;
783 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
787 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
788 (cpu_devs
[i
]->c_ident
[1] &&
789 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
791 this_cpu
= cpu_devs
[i
];
792 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
797 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
798 "CPU: Your system may be unstable.\n", v
);
800 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
801 this_cpu
= &default_cpu
;
804 void cpu_detect(struct cpuinfo_x86
*c
)
806 /* Get vendor name */
807 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
808 (unsigned int *)&c
->x86_vendor_id
[0],
809 (unsigned int *)&c
->x86_vendor_id
[8],
810 (unsigned int *)&c
->x86_vendor_id
[4]);
813 /* Intel-defined flags: level 0x00000001 */
814 if (c
->cpuid_level
>= 0x00000001) {
815 u32 junk
, tfms
, cap0
, misc
;
817 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
818 c
->x86
= x86_family(tfms
);
819 c
->x86_model
= x86_model(tfms
);
820 c
->x86_stepping
= x86_stepping(tfms
);
822 if (cap0
& (1<<19)) {
823 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
824 c
->x86_cache_alignment
= c
->x86_clflush_size
;
829 static void apply_forced_caps(struct cpuinfo_x86
*c
)
833 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
834 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
835 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
839 static void init_speculation_control(struct cpuinfo_x86
*c
)
842 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
843 * and they also have a different bit for STIBP support. Also,
844 * a hypervisor might have set the individual AMD bits even on
845 * Intel CPUs, for finer-grained selection of what's available.
847 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
848 set_cpu_cap(c
, X86_FEATURE_IBRS
);
849 set_cpu_cap(c
, X86_FEATURE_IBPB
);
850 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
853 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
854 set_cpu_cap(c
, X86_FEATURE_STIBP
);
856 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
857 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
858 set_cpu_cap(c
, X86_FEATURE_SSBD
);
860 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
861 set_cpu_cap(c
, X86_FEATURE_IBRS
);
862 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
865 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
866 set_cpu_cap(c
, X86_FEATURE_IBPB
);
868 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
869 set_cpu_cap(c
, X86_FEATURE_STIBP
);
870 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
873 if (cpu_has(c
, X86_FEATURE_AMD_SSBD
)) {
874 set_cpu_cap(c
, X86_FEATURE_SSBD
);
875 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
876 clear_cpu_cap(c
, X86_FEATURE_VIRT_SSBD
);
880 void get_cpu_cap(struct cpuinfo_x86
*c
)
882 u32 eax
, ebx
, ecx
, edx
;
884 /* Intel-defined flags: level 0x00000001 */
885 if (c
->cpuid_level
>= 0x00000001) {
886 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
888 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
889 c
->x86_capability
[CPUID_1_EDX
] = edx
;
892 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
893 if (c
->cpuid_level
>= 0x00000006)
894 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
896 /* Additional Intel-defined flags: level 0x00000007 */
897 if (c
->cpuid_level
>= 0x00000007) {
898 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
899 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
900 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
901 c
->x86_capability
[CPUID_7_EDX
] = edx
;
903 /* Check valid sub-leaf index before accessing it */
905 cpuid_count(0x00000007, 1, &eax
, &ebx
, &ecx
, &edx
);
906 c
->x86_capability
[CPUID_7_1_EAX
] = eax
;
910 /* Extended state features: level 0x0000000d */
911 if (c
->cpuid_level
>= 0x0000000d) {
912 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
914 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
917 /* AMD-defined flags: level 0x80000001 */
918 eax
= cpuid_eax(0x80000000);
919 c
->extended_cpuid_level
= eax
;
921 if ((eax
& 0xffff0000) == 0x80000000) {
922 if (eax
>= 0x80000001) {
923 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
925 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
926 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
930 if (c
->extended_cpuid_level
>= 0x80000007) {
931 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
933 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
937 if (c
->extended_cpuid_level
>= 0x80000008) {
938 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
939 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
942 if (c
->extended_cpuid_level
>= 0x8000000a)
943 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
945 init_scattered_cpuid_features(c
);
946 init_speculation_control(c
);
949 * Clear/Set all flags overridden by options, after probe.
950 * This needs to happen each time we re-probe, which may happen
951 * several times during CPU initialization.
953 apply_forced_caps(c
);
956 void get_cpu_address_sizes(struct cpuinfo_x86
*c
)
958 u32 eax
, ebx
, ecx
, edx
;
960 if (c
->extended_cpuid_level
>= 0x80000008) {
961 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
963 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
964 c
->x86_phys_bits
= eax
& 0xff;
967 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
968 c
->x86_phys_bits
= 36;
970 c
->x86_cache_bits
= c
->x86_phys_bits
;
973 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
979 * First of all, decide if this is a 486 or higher
980 * It's a 486 if we can modify the AC flag
982 if (flag_is_changeable_p(X86_EFLAGS_AC
))
987 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
988 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
989 c
->x86_vendor_id
[0] = 0;
990 cpu_devs
[i
]->c_identify(c
);
991 if (c
->x86_vendor_id
[0]) {
999 #define NO_SPECULATION BIT(0)
1000 #define NO_MELTDOWN BIT(1)
1001 #define NO_SSB BIT(2)
1002 #define NO_L1TF BIT(3)
1003 #define NO_MDS BIT(4)
1004 #define MSBDS_ONLY BIT(5)
1005 #define NO_SWAPGS BIT(6)
1006 #define NO_ITLB_MULTIHIT BIT(7)
1007 #define NO_SPECTRE_V2 BIT(8)
1009 #define VULNWL(vendor, family, model, whitelist) \
1010 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1012 #define VULNWL_INTEL(model, whitelist) \
1013 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1015 #define VULNWL_AMD(family, whitelist) \
1016 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1018 #define VULNWL_HYGON(family, whitelist) \
1019 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1021 static const __initconst
struct x86_cpu_id cpu_vuln_whitelist
[] = {
1022 VULNWL(ANY
, 4, X86_MODEL_ANY
, NO_SPECULATION
),
1023 VULNWL(CENTAUR
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1024 VULNWL(INTEL
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1025 VULNWL(NSC
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1027 /* Intel Family 6 */
1028 VULNWL_INTEL(ATOM_SALTWELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1029 VULNWL_INTEL(ATOM_SALTWELL_TABLET
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1030 VULNWL_INTEL(ATOM_SALTWELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1031 VULNWL_INTEL(ATOM_BONNELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1032 VULNWL_INTEL(ATOM_BONNELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1034 VULNWL_INTEL(ATOM_SILVERMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1035 VULNWL_INTEL(ATOM_SILVERMONT_D
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1036 VULNWL_INTEL(ATOM_SILVERMONT_MID
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1037 VULNWL_INTEL(ATOM_AIRMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1038 VULNWL_INTEL(XEON_PHI_KNL
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1039 VULNWL_INTEL(XEON_PHI_KNM
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1041 VULNWL_INTEL(CORE_YONAH
, NO_SSB
),
1043 VULNWL_INTEL(ATOM_AIRMONT_MID
, NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1044 VULNWL_INTEL(ATOM_AIRMONT_NP
, NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1046 VULNWL_INTEL(ATOM_GOLDMONT
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1047 VULNWL_INTEL(ATOM_GOLDMONT_D
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1048 VULNWL_INTEL(ATOM_GOLDMONT_PLUS
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1051 * Technically, swapgs isn't serializing on AMD (despite it previously
1052 * being documented as such in the APM). But according to AMD, %gs is
1053 * updated non-speculatively, and the issuing of %gs-relative memory
1054 * operands will be blocked until the %gs update completes, which is
1055 * good enough for our purposes.
1058 VULNWL_INTEL(ATOM_TREMONT_D
, NO_ITLB_MULTIHIT
),
1060 /* AMD Family 0xf - 0x12 */
1061 VULNWL_AMD(0x0f, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1062 VULNWL_AMD(0x10, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1063 VULNWL_AMD(0x11, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1064 VULNWL_AMD(0x12, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1066 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1067 VULNWL_AMD(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1068 VULNWL_HYGON(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1070 /* Zhaoxin Family 7 */
1071 VULNWL(CENTAUR
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
),
1072 VULNWL(ZHAOXIN
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
),
1076 static bool __init
cpu_matches(unsigned long which
)
1078 const struct x86_cpu_id
*m
= x86_match_cpu(cpu_vuln_whitelist
);
1080 return m
&& !!(m
->driver_data
& which
);
1083 u64
x86_read_arch_cap_msr(void)
1087 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
1088 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
1093 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
1095 u64 ia32_cap
= x86_read_arch_cap_msr();
1097 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1098 if (!cpu_matches(NO_ITLB_MULTIHIT
) && !(ia32_cap
& ARCH_CAP_PSCHANGE_MC_NO
))
1099 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT
);
1101 if (cpu_matches(NO_SPECULATION
))
1104 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
1106 if (!cpu_matches(NO_SPECTRE_V2
))
1107 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
1109 if (!cpu_matches(NO_SSB
) && !(ia32_cap
& ARCH_CAP_SSB_NO
) &&
1110 !cpu_has(c
, X86_FEATURE_AMD_SSB_NO
))
1111 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
1113 if (ia32_cap
& ARCH_CAP_IBRS_ALL
)
1114 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED
);
1116 if (!cpu_matches(NO_MDS
) && !(ia32_cap
& ARCH_CAP_MDS_NO
)) {
1117 setup_force_cpu_bug(X86_BUG_MDS
);
1118 if (cpu_matches(MSBDS_ONLY
))
1119 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY
);
1122 if (!cpu_matches(NO_SWAPGS
))
1123 setup_force_cpu_bug(X86_BUG_SWAPGS
);
1126 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1127 * - TSX is supported or
1128 * - TSX_CTRL is present
1130 * TSX_CTRL check is needed for cases when TSX could be disabled before
1131 * the kernel boot e.g. kexec.
1132 * TSX_CTRL check alone is not sufficient for cases when the microcode
1133 * update is not present or running as guest that don't get TSX_CTRL.
1135 if (!(ia32_cap
& ARCH_CAP_TAA_NO
) &&
1136 (cpu_has(c
, X86_FEATURE_RTM
) ||
1137 (ia32_cap
& ARCH_CAP_TSX_CTRL_MSR
)))
1138 setup_force_cpu_bug(X86_BUG_TAA
);
1140 if (cpu_matches(NO_MELTDOWN
))
1143 /* Rogue Data Cache Load? No! */
1144 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
1147 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
1149 if (cpu_matches(NO_L1TF
))
1152 setup_force_cpu_bug(X86_BUG_L1TF
);
1156 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1157 * unfortunately, that's not true in practice because of early VIA
1158 * chips and (more importantly) broken virtualizers that are not easy
1159 * to detect. In the latter case it doesn't even *fail* reliably, so
1160 * probing for it doesn't even work. Disable it completely on 32-bit
1161 * unless we can find a reliable way to detect all the broken cases.
1162 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1164 static void detect_nopl(void)
1166 #ifdef CONFIG_X86_32
1167 setup_clear_cpu_cap(X86_FEATURE_NOPL
);
1169 setup_force_cpu_cap(X86_FEATURE_NOPL
);
1174 * Do minimum CPU detection early.
1175 * Fields really needed: vendor, cpuid_level, family, model, mask,
1177 * The others are not touched to avoid unwanted side effects.
1179 * WARNING: this function is only called on the boot CPU. Don't add code
1180 * here that is supposed to run on all CPUs.
1182 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
1184 #ifdef CONFIG_X86_64
1185 c
->x86_clflush_size
= 64;
1186 c
->x86_phys_bits
= 36;
1187 c
->x86_virt_bits
= 48;
1189 c
->x86_clflush_size
= 32;
1190 c
->x86_phys_bits
= 32;
1191 c
->x86_virt_bits
= 32;
1193 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1195 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1196 c
->extended_cpuid_level
= 0;
1198 if (!have_cpuid_p())
1199 identify_cpu_without_cpuid(c
);
1201 /* cyrix could have cpuid enabled via c_identify()*/
1202 if (have_cpuid_p()) {
1206 get_cpu_address_sizes(c
);
1207 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1209 if (this_cpu
->c_early_init
)
1210 this_cpu
->c_early_init(c
);
1213 filter_cpuid_features(c
, false);
1215 if (this_cpu
->c_bsp_init
)
1216 this_cpu
->c_bsp_init(c
);
1218 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1221 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1223 cpu_set_bug_bits(c
);
1225 cpu_set_core_cap_bits(c
);
1227 fpu__init_system(c
);
1229 #ifdef CONFIG_X86_32
1231 * Regardless of whether PCID is enumerated, the SDM says
1232 * that it can't be enabled in 32-bit mode.
1234 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1238 * Later in the boot process pgtable_l5_enabled() relies on
1239 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1240 * enabled by this point we need to clear the feature bit to avoid
1241 * false-positives at the later stage.
1243 * pgtable_l5_enabled() can be false here for several reasons:
1244 * - 5-level paging is disabled compile-time;
1245 * - it's 32-bit kernel;
1246 * - machine doesn't support 5-level paging;
1247 * - user specified 'no5lvl' in kernel command line.
1249 if (!pgtable_l5_enabled())
1250 setup_clear_cpu_cap(X86_FEATURE_LA57
);
1255 void __init
early_cpu_init(void)
1257 const struct cpu_dev
*const *cdev
;
1260 #ifdef CONFIG_PROCESSOR_SELECT
1261 pr_info("KERNEL supported cpus:\n");
1264 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1265 const struct cpu_dev
*cpudev
= *cdev
;
1267 if (count
>= X86_VENDOR_NUM
)
1269 cpu_devs
[count
] = cpudev
;
1272 #ifdef CONFIG_PROCESSOR_SELECT
1276 for (j
= 0; j
< 2; j
++) {
1277 if (!cpudev
->c_ident
[j
])
1279 pr_info(" %s %s\n", cpudev
->c_vendor
,
1280 cpudev
->c_ident
[j
]);
1285 early_identify_cpu(&boot_cpu_data
);
1288 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
1290 #ifdef CONFIG_X86_64
1292 * Empirically, writing zero to a segment selector on AMD does
1293 * not clear the base, whereas writing zero to a segment
1294 * selector on Intel does clear the base. Intel's behavior
1295 * allows slightly faster context switches in the common case
1296 * where GS is unused by the prev and next threads.
1298 * Since neither vendor documents this anywhere that I can see,
1299 * detect it directly instead of hardcoding the choice by
1302 * I've designated AMD's behavior as the "bug" because it's
1303 * counterintuitive and less friendly.
1306 unsigned long old_base
, tmp
;
1307 rdmsrl(MSR_FS_BASE
, old_base
);
1308 wrmsrl(MSR_FS_BASE
, 1);
1310 rdmsrl(MSR_FS_BASE
, tmp
);
1312 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1313 wrmsrl(MSR_FS_BASE
, old_base
);
1317 static void generic_identify(struct cpuinfo_x86
*c
)
1319 c
->extended_cpuid_level
= 0;
1321 if (!have_cpuid_p())
1322 identify_cpu_without_cpuid(c
);
1324 /* cyrix could have cpuid enabled via c_identify()*/
1325 if (!have_cpuid_p())
1334 get_cpu_address_sizes(c
);
1336 if (c
->cpuid_level
>= 0x00000001) {
1337 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1338 #ifdef CONFIG_X86_32
1340 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1342 c
->apicid
= c
->initial_apicid
;
1345 c
->phys_proc_id
= c
->initial_apicid
;
1348 get_model_name(c
); /* Default name */
1350 detect_null_seg_behavior(c
);
1353 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1354 * systems that run Linux at CPL > 0 may or may not have the
1355 * issue, but, even if they have the issue, there's absolutely
1356 * nothing we can do about it because we can't use the real IRET
1359 * NB: For the time being, only 32-bit kernels support
1360 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1361 * whether to apply espfix using paravirt hooks. If any
1362 * non-paravirt system ever shows up that does *not* have the
1363 * ESPFIX issue, we can change this.
1365 #ifdef CONFIG_X86_32
1366 # ifdef CONFIG_PARAVIRT_XXL
1368 extern void native_iret(void);
1369 if (pv_ops
.cpu
.iret
== native_iret
)
1370 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1373 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1379 * Validate that ACPI/mptables have the same information about the
1380 * effective APIC id and update the package map.
1382 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1385 unsigned int apicid
, cpu
= smp_processor_id();
1387 apicid
= apic
->cpu_present_to_apicid(cpu
);
1389 if (apicid
!= c
->apicid
) {
1390 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1391 cpu
, apicid
, c
->initial_apicid
);
1393 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1394 BUG_ON(topology_update_die_map(c
->cpu_die_id
, cpu
));
1396 c
->logical_proc_id
= 0;
1401 * This does the hard work of actually picking apart the CPU stuff...
1403 static void identify_cpu(struct cpuinfo_x86
*c
)
1407 c
->loops_per_jiffy
= loops_per_jiffy
;
1408 c
->x86_cache_size
= 0;
1409 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1410 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1411 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1412 c
->x86_model_id
[0] = '\0'; /* Unset */
1413 c
->x86_max_cores
= 1;
1414 c
->x86_coreid_bits
= 0;
1416 #ifdef CONFIG_X86_64
1417 c
->x86_clflush_size
= 64;
1418 c
->x86_phys_bits
= 36;
1419 c
->x86_virt_bits
= 48;
1421 c
->cpuid_level
= -1; /* CPUID not detected */
1422 c
->x86_clflush_size
= 32;
1423 c
->x86_phys_bits
= 32;
1424 c
->x86_virt_bits
= 32;
1426 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1427 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1428 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1429 memset(&c
->vmx_capability
, 0, sizeof(c
->vmx_capability
));
1432 generic_identify(c
);
1434 if (this_cpu
->c_identify
)
1435 this_cpu
->c_identify(c
);
1437 /* Clear/Set all flags overridden by options, after probe */
1438 apply_forced_caps(c
);
1440 #ifdef CONFIG_X86_64
1441 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1445 * Vendor-specific initialization. In this section we
1446 * canonicalize the feature flags, meaning if there are
1447 * features a certain CPU supports which CPUID doesn't
1448 * tell us, CPUID claiming incorrect flags, or other bugs,
1449 * we handle them here.
1451 * At the end of this section, c->x86_capability better
1452 * indicate the features this CPU genuinely supports!
1454 if (this_cpu
->c_init
)
1455 this_cpu
->c_init(c
);
1457 /* Disable the PN if appropriate */
1458 squash_the_stupid_serial_number(c
);
1460 /* Set up SMEP/SMAP/UMIP */
1466 * The vendor-specific functions might have changed features.
1467 * Now we do "generic changes."
1470 /* Filter out anything that depends on CPUID levels we don't have */
1471 filter_cpuid_features(c
, true);
1473 /* If the model name is still unset, do table lookup. */
1474 if (!c
->x86_model_id
[0]) {
1476 p
= table_lookup_model(c
);
1478 strcpy(c
->x86_model_id
, p
);
1480 /* Last resort... */
1481 sprintf(c
->x86_model_id
, "%02x/%02x",
1482 c
->x86
, c
->x86_model
);
1485 #ifdef CONFIG_X86_64
1493 * Clear/Set all flags overridden by options, need do it
1494 * before following smp all cpus cap AND.
1496 apply_forced_caps(c
);
1499 * On SMP, boot_cpu_data holds the common feature set between
1500 * all CPUs; so make sure that we indicate which features are
1501 * common between the CPUs. The first time this routine gets
1502 * executed, c == &boot_cpu_data.
1504 if (c
!= &boot_cpu_data
) {
1505 /* AND the already accumulated flags with these */
1506 for (i
= 0; i
< NCAPINTS
; i
++)
1507 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1509 /* OR, i.e. replicate the bug flags */
1510 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1511 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1514 /* Init Machine Check Exception if available. */
1517 select_idle_routine(c
);
1520 numa_add_cpu(smp_processor_id());
1525 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1526 * on 32-bit kernels:
1528 #ifdef CONFIG_X86_32
1529 void enable_sep_cpu(void)
1531 struct tss_struct
*tss
;
1534 if (!boot_cpu_has(X86_FEATURE_SEP
))
1538 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1541 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1542 * see the big comment in struct x86_hw_tss's definition.
1545 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1546 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1547 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1548 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1554 void __init
identify_boot_cpu(void)
1556 identify_cpu(&boot_cpu_data
);
1557 #ifdef CONFIG_X86_32
1561 cpu_detect_tlb(&boot_cpu_data
);
1567 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1569 BUG_ON(c
== &boot_cpu_data
);
1571 #ifdef CONFIG_X86_32
1575 validate_apic_and_package_id(c
);
1576 x86_spec_ctrl_setup_ap();
1579 static __init
int setup_noclflush(char *arg
)
1581 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1582 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1585 __setup("noclflush", setup_noclflush
);
1587 void print_cpu_info(struct cpuinfo_x86
*c
)
1589 const char *vendor
= NULL
;
1591 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1592 vendor
= this_cpu
->c_vendor
;
1594 if (c
->cpuid_level
>= 0)
1595 vendor
= c
->x86_vendor_id
;
1598 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1599 pr_cont("%s ", vendor
);
1601 if (c
->x86_model_id
[0])
1602 pr_cont("%s", c
->x86_model_id
);
1604 pr_cont("%d86", c
->x86
);
1606 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1608 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
1609 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
1615 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1616 * But we need to keep a dummy __setup around otherwise it would
1617 * show up as an environment variable for init.
1619 static __init
int setup_clearcpuid(char *arg
)
1623 __setup("clearcpuid=", setup_clearcpuid
);
1625 #ifdef CONFIG_X86_64
1626 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data
,
1627 fixed_percpu_data
) __aligned(PAGE_SIZE
) __visible
;
1628 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data
);
1631 * The following percpu variables are hot. Align current_task to
1632 * cacheline size such that they fall in the same cacheline.
1634 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1636 EXPORT_PER_CPU_SYMBOL(current_task
);
1638 DEFINE_PER_CPU(struct irq_stack
*, hardirq_stack_ptr
);
1639 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1641 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1642 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1644 /* May not be marked __init: used by software suspend */
1645 void syscall_init(void)
1647 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1648 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1650 #ifdef CONFIG_IA32_EMULATION
1651 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1653 * This only works on Intel CPUs.
1654 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1655 * This does not cause SYSENTER to jump to the wrong location, because
1656 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1658 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1659 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
,
1660 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1661 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1663 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1664 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1665 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1666 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1669 /* Flags to clear on syscall */
1670 wrmsrl(MSR_SYSCALL_MASK
,
1671 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1672 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1675 DEFINE_PER_CPU(int, debug_stack_usage
);
1676 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1678 void debug_stack_set_zero(void)
1680 this_cpu_inc(debug_idt_ctr
);
1683 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1685 void debug_stack_reset(void)
1687 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1689 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1692 NOKPROBE_SYMBOL(debug_stack_reset
);
1694 #else /* CONFIG_X86_64 */
1696 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1697 EXPORT_PER_CPU_SYMBOL(current_task
);
1698 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1699 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1702 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1703 * the top of the kernel stack. Use an extra percpu variable to track the
1704 * top of the kernel stack directly.
1706 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1707 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1708 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1710 #ifdef CONFIG_STACKPROTECTOR
1711 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1714 #endif /* CONFIG_X86_64 */
1717 * Clear all 6 debug registers:
1719 static void clear_all_debug_regs(void)
1723 for (i
= 0; i
< 8; i
++) {
1724 /* Ignore db4, db5 */
1725 if ((i
== 4) || (i
== 5))
1734 * Restore debug regs if using kgdbwait and you have a kernel debugger
1735 * connection established.
1737 static void dbg_restore_debug_regs(void)
1739 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1740 arch_kgdb_ops
.correct_hw_break();
1742 #else /* ! CONFIG_KGDB */
1743 #define dbg_restore_debug_regs()
1744 #endif /* ! CONFIG_KGDB */
1746 static void wait_for_master_cpu(int cpu
)
1750 * wait for ACK from master CPU before continuing
1751 * with AP initialization
1753 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1754 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1759 #ifdef CONFIG_X86_64
1760 static inline void setup_getcpu(int cpu
)
1762 unsigned long cpudata
= vdso_encode_cpunode(cpu
, early_cpu_to_node(cpu
));
1763 struct desc_struct d
= { };
1765 if (boot_cpu_has(X86_FEATURE_RDTSCP
))
1766 write_rdtscp_aux(cpudata
);
1768 /* Store CPU and node number in limit. */
1770 d
.limit1
= cpudata
>> 16;
1772 d
.type
= 5; /* RO data, expand down, accessed */
1773 d
.dpl
= 3; /* Visible to user code */
1774 d
.s
= 1; /* Not a system segment */
1775 d
.p
= 1; /* Present */
1776 d
.d
= 1; /* 32-bit */
1778 write_gdt_entry(get_cpu_gdt_rw(cpu
), GDT_ENTRY_CPUNODE
, &d
, DESCTYPE_S
);
1781 static inline void ucode_cpu_init(int cpu
)
1787 static inline void tss_setup_ist(struct tss_struct
*tss
)
1789 /* Set up the per-CPU TSS IST stacks */
1790 tss
->x86_tss
.ist
[IST_INDEX_DF
] = __this_cpu_ist_top_va(DF
);
1791 tss
->x86_tss
.ist
[IST_INDEX_NMI
] = __this_cpu_ist_top_va(NMI
);
1792 tss
->x86_tss
.ist
[IST_INDEX_DB
] = __this_cpu_ist_top_va(DB
);
1793 tss
->x86_tss
.ist
[IST_INDEX_MCE
] = __this_cpu_ist_top_va(MCE
);
1796 #else /* CONFIG_X86_64 */
1798 static inline void setup_getcpu(int cpu
) { }
1800 static inline void ucode_cpu_init(int cpu
)
1802 show_ucode_info_early();
1805 static inline void tss_setup_ist(struct tss_struct
*tss
) { }
1807 #endif /* !CONFIG_X86_64 */
1809 static inline void tss_setup_io_bitmap(struct tss_struct
*tss
)
1811 tss
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET_INVALID
;
1813 #ifdef CONFIG_X86_IOPL_IOPERM
1814 tss
->io_bitmap
.prev_max
= 0;
1815 tss
->io_bitmap
.prev_sequence
= 0;
1816 memset(tss
->io_bitmap
.bitmap
, 0xff, sizeof(tss
->io_bitmap
.bitmap
));
1818 * Invalidate the extra array entry past the end of the all
1819 * permission bitmap as required by the hardware.
1821 tss
->io_bitmap
.mapall
[IO_BITMAP_LONGS
] = ~0UL;
1826 * cpu_init() initializes state that is per-CPU. Some data is already
1827 * initialized (naturally) in the bootstrap process, such as the GDT
1828 * and IDT. We reload them nevertheless, this function acts as a
1829 * 'CPU state barrier', nothing should get across.
1833 struct tss_struct
*tss
= this_cpu_ptr(&cpu_tss_rw
);
1834 struct task_struct
*cur
= current
;
1835 int cpu
= raw_smp_processor_id();
1837 wait_for_master_cpu(cpu
);
1839 ucode_cpu_init(cpu
);
1842 if (this_cpu_read(numa_node
) == 0 &&
1843 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1844 set_numa_node(early_cpu_to_node(cpu
));
1848 pr_debug("Initializing CPU#%d\n", cpu
);
1850 if (IS_ENABLED(CONFIG_X86_64
) || cpu_feature_enabled(X86_FEATURE_VME
) ||
1851 boot_cpu_has(X86_FEATURE_TSC
) || boot_cpu_has(X86_FEATURE_DE
))
1852 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1855 * Initialize the per-CPU GDT with the boot GDT,
1856 * and set up the GDT descriptor:
1858 switch_to_new_gdt(cpu
);
1861 if (IS_ENABLED(CONFIG_X86_64
)) {
1863 memset(cur
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1866 wrmsrl(MSR_FS_BASE
, 0);
1867 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1874 cur
->active_mm
= &init_mm
;
1876 initialize_tlbstate_and_flush();
1877 enter_lazy_tlb(&init_mm
, cur
);
1879 /* Initialize the TSS. */
1881 tss_setup_io_bitmap(tss
);
1882 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1886 * sp0 points to the entry trampoline stack regardless of what task
1889 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
1891 load_mm_ldt(&init_mm
);
1893 clear_all_debug_regs();
1894 dbg_restore_debug_regs();
1896 doublefault_init_cpu_tss();
1903 load_fixmap_gdt(cpu
);
1907 * The microcode loader calls this upon late microcode load to recheck features,
1908 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1911 void microcode_check(void)
1913 struct cpuinfo_x86 info
;
1915 perf_check_microcode();
1917 /* Reload CPUID max function as it might've changed. */
1918 info
.cpuid_level
= cpuid_eax(0);
1921 * Copy all capability leafs to pick up the synthetic ones so that
1922 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1923 * get overwritten in get_cpu_cap().
1925 memcpy(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
));
1929 if (!memcmp(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
)))
1932 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1933 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1937 * Invoked from core CPU hotplug code after hotplug operations
1939 void arch_smt_update(void)
1941 /* Handle the speculative execution misfeatures */
1942 cpu_bugs_smt_update();
1943 /* Check whether IPI broadcasting can be enabled */