1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/sched/clock.h>
12 #include <linux/sched/task.h>
13 #include <linux/init.h>
14 #include <linux/kprobes.h>
15 #include <linux/kgdb.h>
16 #include <linux/smp.h>
18 #include <linux/syscore_ops.h>
20 #include <asm/stackprotector.h>
21 #include <asm/perf_event.h>
22 #include <asm/mmu_context.h>
23 #include <asm/archrandom.h>
24 #include <asm/hypervisor.h>
25 #include <asm/processor.h>
26 #include <asm/tlbflush.h>
27 #include <asm/debugreg.h>
28 #include <asm/sections.h>
29 #include <asm/vsyscall.h>
30 #include <linux/topology.h>
31 #include <linux/cpumask.h>
32 #include <asm/pgtable.h>
33 #include <linux/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/setup.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/hwcap2.h>
41 #include <linux/numa.h>
48 #include <asm/microcode.h>
49 #include <asm/microcode_intel.h>
51 #ifdef CONFIG_X86_LOCAL_APIC
52 #include <asm/uv/uv.h>
57 u32 elf_hwcap2 __read_mostly
;
59 /* all of these masks are initialized in setup_cpu_local_masks() */
60 cpumask_var_t cpu_initialized_mask
;
61 cpumask_var_t cpu_callout_mask
;
62 cpumask_var_t cpu_callin_mask
;
64 /* representing cpus for which sibling maps can be computed */
65 cpumask_var_t cpu_sibling_setup_mask
;
67 /* correctly size the local cpu masks */
68 void __init
setup_cpu_local_masks(void)
70 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
71 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
72 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
76 static void default_init(struct cpuinfo_x86
*c
)
79 cpu_detect_cache_sizes(c
);
81 /* Not much we can do here... */
82 /* Check if at least it has cpuid */
83 if (c
->cpuid_level
== -1) {
84 /* No cpuid. It must be an ancient CPU */
86 strcpy(c
->x86_model_id
, "486");
88 strcpy(c
->x86_model_id
, "386");
91 clear_sched_clock_stable();
94 static const struct cpu_dev default_cpu
= {
95 .c_init
= default_init
,
96 .c_vendor
= "Unknown",
97 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
100 static const struct cpu_dev
*this_cpu
= &default_cpu
;
102 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
105 * We need valid kernel segments for data and code in long mode too
106 * IRET will check the segment types kkeil 2000/10/28
107 * Also sysret mandates a special GDT layout
109 * TLS descriptors are currently at a different place compared to i386.
110 * Hopefully nobody expects them at a fixed place (Wine?)
112 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
119 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
120 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
121 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
122 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
124 * Segments used for calling PnP BIOS have byte granularity.
125 * They code segments and data segments have fixed 64k limits,
126 * the transfer segment sizes are set at run time.
129 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
131 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
133 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
135 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
137 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
139 * The APM segments have byte granularity and their bases
140 * are set at run time. All have 64k limits.
143 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
145 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
147 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
149 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
150 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
151 GDT_STACK_CANARY_INIT
154 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
156 static int __init
x86_mpx_setup(char *s
)
158 /* require an exact match without trailing characters */
162 /* do not emit a message if the feature is not present */
163 if (!boot_cpu_has(X86_FEATURE_MPX
))
166 setup_clear_cpu_cap(X86_FEATURE_MPX
);
167 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
170 __setup("nompx", x86_mpx_setup
);
172 static int __init
x86_noinvpcid_setup(char *s
)
174 /* noinvpcid doesn't accept parameters */
178 /* do not emit a message if the feature is not present */
179 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
182 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
183 pr_info("noinvpcid: INVPCID feature disabled\n");
186 early_param("noinvpcid", x86_noinvpcid_setup
);
189 static int cachesize_override
= -1;
190 static int disable_x86_serial_nr
= 1;
192 static int __init
cachesize_setup(char *str
)
194 get_option(&str
, &cachesize_override
);
197 __setup("cachesize=", cachesize_setup
);
199 static int __init
x86_sep_setup(char *s
)
201 setup_clear_cpu_cap(X86_FEATURE_SEP
);
204 __setup("nosep", x86_sep_setup
);
206 /* Standard macro to see if a specific flag is changeable */
207 static inline int flag_is_changeable_p(u32 flag
)
212 * Cyrix and IDT cpus allow disabling of CPUID
213 * so the code below may return different results
214 * when it is executed before and after enabling
215 * the CPUID. Add "volatile" to not allow gcc to
216 * optimize the subsequent calls to this function.
218 asm volatile ("pushfl \n\t"
229 : "=&r" (f1
), "=&r" (f2
)
232 return ((f1
^f2
) & flag
) != 0;
235 /* Probe for the CPUID instruction */
236 int have_cpuid_p(void)
238 return flag_is_changeable_p(X86_EFLAGS_ID
);
241 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
243 unsigned long lo
, hi
;
245 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
248 /* Disable processor serial number: */
250 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
252 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
254 pr_notice("CPU serial number disabled.\n");
255 clear_cpu_cap(c
, X86_FEATURE_PN
);
257 /* Disabling the serial number may affect the cpuid level */
258 c
->cpuid_level
= cpuid_eax(0);
261 static int __init
x86_serial_nr_setup(char *s
)
263 disable_x86_serial_nr
= 0;
266 __setup("serialnumber", x86_serial_nr_setup
);
268 static inline int flag_is_changeable_p(u32 flag
)
272 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
277 static __init
int setup_disable_smep(char *arg
)
279 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
280 /* Check for things that depend on SMEP being enabled: */
281 check_mpx_erratum(&boot_cpu_data
);
284 __setup("nosmep", setup_disable_smep
);
286 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
288 if (cpu_has(c
, X86_FEATURE_SMEP
))
289 cr4_set_bits(X86_CR4_SMEP
);
292 static __init
int setup_disable_smap(char *arg
)
294 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
297 __setup("nosmap", setup_disable_smap
);
299 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
301 unsigned long eflags
= native_save_fl();
303 /* This should have been cleared long ago */
304 BUG_ON(eflags
& X86_EFLAGS_AC
);
306 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
307 #ifdef CONFIG_X86_SMAP
308 cr4_set_bits(X86_CR4_SMAP
);
310 cr4_clear_bits(X86_CR4_SMAP
);
316 * Protection Keys are not available in 32-bit mode.
318 static bool pku_disabled
;
320 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
322 /* check the boot processor, plus compile options for PKU: */
323 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
325 /* checks the actual processor's cpuid bits: */
326 if (!cpu_has(c
, X86_FEATURE_PKU
))
331 cr4_set_bits(X86_CR4_PKE
);
333 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
334 * cpuid bit to be set. We need to ensure that we
335 * update that bit in this CPU's "cpu_info".
340 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
341 static __init
int setup_disable_pku(char *arg
)
344 * Do not clear the X86_FEATURE_PKU bit. All of the
345 * runtime checks are against OSPKE so clearing the
348 * This way, we will see "pku" in cpuinfo, but not
349 * "ospke", which is exactly what we want. It shows
350 * that the CPU has PKU, but the OS has not enabled it.
351 * This happens to be exactly how a system would look
352 * if we disabled the config option.
354 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
358 __setup("nopku", setup_disable_pku
);
359 #endif /* CONFIG_X86_64 */
362 * Some CPU features depend on higher CPUID levels, which may not always
363 * be available due to CPUID level capping or broken virtualization
364 * software. Add those features to this table to auto-disable them.
366 struct cpuid_dependent_feature
{
371 static const struct cpuid_dependent_feature
372 cpuid_dependent_features
[] = {
373 { X86_FEATURE_MWAIT
, 0x00000005 },
374 { X86_FEATURE_DCA
, 0x00000009 },
375 { X86_FEATURE_XSAVE
, 0x0000000d },
379 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
381 const struct cpuid_dependent_feature
*df
;
383 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
385 if (!cpu_has(c
, df
->feature
))
388 * Note: cpuid_level is set to -1 if unavailable, but
389 * extended_extended_level is set to 0 if unavailable
390 * and the legitimate extended levels are all negative
391 * when signed; hence the weird messing around with
394 if (!((s32
)df
->level
< 0 ?
395 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
396 (s32
)df
->level
> (s32
)c
->cpuid_level
))
399 clear_cpu_cap(c
, df
->feature
);
403 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
404 x86_cap_flag(df
->feature
), df
->level
);
409 * Naming convention should be: <Name> [(<Codename>)]
410 * This table only is used unless init_<vendor>() below doesn't set it;
411 * in particular, if CPUID levels 0x80000002..4 are supported, this
415 /* Look up CPU names by table lookup. */
416 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
419 const struct legacy_cpu_model_info
*info
;
421 if (c
->x86_model
>= 16)
422 return NULL
; /* Range check */
427 info
= this_cpu
->legacy_models
;
429 while (info
->family
) {
430 if (info
->family
== c
->x86
)
431 return info
->model_names
[c
->x86_model
];
435 return NULL
; /* Not found */
438 __u32 cpu_caps_cleared
[NCAPINTS
];
439 __u32 cpu_caps_set
[NCAPINTS
];
441 void load_percpu_segment(int cpu
)
444 loadsegment(fs
, __KERNEL_PERCPU
);
446 __loadsegment_simple(gs
, 0);
447 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
449 load_stack_canary_segment();
453 * Current gdt points %fs at the "master" per-cpu area: after this,
454 * it's on the real one.
456 void switch_to_new_gdt(int cpu
)
458 struct desc_ptr gdt_descr
;
460 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
461 gdt_descr
.size
= GDT_SIZE
- 1;
462 load_gdt(&gdt_descr
);
463 /* Reload the per-cpu base */
465 load_percpu_segment(cpu
);
468 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
470 static void get_model_name(struct cpuinfo_x86
*c
)
475 if (c
->extended_cpuid_level
< 0x80000004)
478 v
= (unsigned int *)c
->x86_model_id
;
479 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
480 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
481 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
482 c
->x86_model_id
[48] = 0;
484 /* Trim whitespace */
485 p
= q
= s
= &c
->x86_model_id
[0];
491 /* Note the last non-whitespace index */
501 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
503 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
505 n
= c
->extended_cpuid_level
;
507 if (n
>= 0x80000005) {
508 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
509 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
511 /* On K8 L1 TLB is inclusive, so don't count it */
516 if (n
< 0x80000006) /* Some chips just has a large L1. */
519 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
523 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
525 /* do processor-specific cache resizing */
526 if (this_cpu
->legacy_cache_size
)
527 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
529 /* Allow user to override all this if necessary. */
530 if (cachesize_override
!= -1)
531 l2size
= cachesize_override
;
534 return; /* Again, no L2 cache is possible */
537 c
->x86_cache_size
= l2size
;
540 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
541 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
542 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
543 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
544 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
545 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
546 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
548 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
550 if (this_cpu
->c_detect_tlb
)
551 this_cpu
->c_detect_tlb(c
);
553 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
554 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
555 tlb_lli_4m
[ENTRIES
]);
557 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
558 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
559 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
562 void detect_ht(struct cpuinfo_x86
*c
)
565 u32 eax
, ebx
, ecx
, edx
;
566 int index_msb
, core_bits
;
569 if (!cpu_has(c
, X86_FEATURE_HT
))
572 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
575 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
578 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
580 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
582 if (smp_num_siblings
== 1) {
583 pr_info_once("CPU0: Hyper-Threading is disabled\n");
587 if (smp_num_siblings
<= 1)
590 index_msb
= get_count_order(smp_num_siblings
);
591 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
593 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
595 index_msb
= get_count_order(smp_num_siblings
);
597 core_bits
= get_count_order(c
->x86_max_cores
);
599 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
600 ((1 << core_bits
) - 1);
603 if (!printed
&& (c
->x86_max_cores
* smp_num_siblings
) > 1) {
604 pr_info("CPU: Physical Processor ID: %d\n",
606 pr_info("CPU: Processor Core ID: %d\n",
613 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
615 char *v
= c
->x86_vendor_id
;
618 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
622 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
623 (cpu_devs
[i
]->c_ident
[1] &&
624 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
626 this_cpu
= cpu_devs
[i
];
627 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
632 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
633 "CPU: Your system may be unstable.\n", v
);
635 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
636 this_cpu
= &default_cpu
;
639 void cpu_detect(struct cpuinfo_x86
*c
)
641 /* Get vendor name */
642 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
643 (unsigned int *)&c
->x86_vendor_id
[0],
644 (unsigned int *)&c
->x86_vendor_id
[8],
645 (unsigned int *)&c
->x86_vendor_id
[4]);
648 /* Intel-defined flags: level 0x00000001 */
649 if (c
->cpuid_level
>= 0x00000001) {
650 u32 junk
, tfms
, cap0
, misc
;
652 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
653 c
->x86
= x86_family(tfms
);
654 c
->x86_model
= x86_model(tfms
);
655 c
->x86_mask
= x86_stepping(tfms
);
657 if (cap0
& (1<<19)) {
658 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
659 c
->x86_cache_alignment
= c
->x86_clflush_size
;
664 static void apply_forced_caps(struct cpuinfo_x86
*c
)
668 for (i
= 0; i
< NCAPINTS
; i
++) {
669 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
670 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
674 void get_cpu_cap(struct cpuinfo_x86
*c
)
676 u32 eax
, ebx
, ecx
, edx
;
678 /* Intel-defined flags: level 0x00000001 */
679 if (c
->cpuid_level
>= 0x00000001) {
680 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
682 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
683 c
->x86_capability
[CPUID_1_EDX
] = edx
;
686 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
687 if (c
->cpuid_level
>= 0x00000006)
688 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
690 /* Additional Intel-defined flags: level 0x00000007 */
691 if (c
->cpuid_level
>= 0x00000007) {
692 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
693 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
694 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
697 /* Extended state features: level 0x0000000d */
698 if (c
->cpuid_level
>= 0x0000000d) {
699 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
701 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
704 /* Additional Intel-defined flags: level 0x0000000F */
705 if (c
->cpuid_level
>= 0x0000000F) {
707 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
708 cpuid_count(0x0000000F, 0, &eax
, &ebx
, &ecx
, &edx
);
709 c
->x86_capability
[CPUID_F_0_EDX
] = edx
;
711 if (cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
712 /* will be overridden if occupancy monitoring exists */
713 c
->x86_cache_max_rmid
= ebx
;
715 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
716 cpuid_count(0x0000000F, 1, &eax
, &ebx
, &ecx
, &edx
);
717 c
->x86_capability
[CPUID_F_1_EDX
] = edx
;
719 if ((cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
)) ||
720 ((cpu_has(c
, X86_FEATURE_CQM_MBM_TOTAL
)) ||
721 (cpu_has(c
, X86_FEATURE_CQM_MBM_LOCAL
)))) {
722 c
->x86_cache_max_rmid
= ecx
;
723 c
->x86_cache_occ_scale
= ebx
;
726 c
->x86_cache_max_rmid
= -1;
727 c
->x86_cache_occ_scale
= -1;
731 /* AMD-defined flags: level 0x80000001 */
732 eax
= cpuid_eax(0x80000000);
733 c
->extended_cpuid_level
= eax
;
735 if ((eax
& 0xffff0000) == 0x80000000) {
736 if (eax
>= 0x80000001) {
737 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
739 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
740 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
744 if (c
->extended_cpuid_level
>= 0x80000007) {
745 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
747 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
751 if (c
->extended_cpuid_level
>= 0x80000008) {
752 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
754 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
755 c
->x86_phys_bits
= eax
& 0xff;
756 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
759 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
760 c
->x86_phys_bits
= 36;
763 if (c
->extended_cpuid_level
>= 0x8000000a)
764 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
766 init_scattered_cpuid_features(c
);
769 * Clear/Set all flags overridden by options, after probe.
770 * This needs to happen each time we re-probe, which may happen
771 * several times during CPU initialization.
773 apply_forced_caps(c
);
776 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
782 * First of all, decide if this is a 486 or higher
783 * It's a 486 if we can modify the AC flag
785 if (flag_is_changeable_p(X86_EFLAGS_AC
))
790 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
791 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
792 c
->x86_vendor_id
[0] = 0;
793 cpu_devs
[i
]->c_identify(c
);
794 if (c
->x86_vendor_id
[0]) {
803 * Do minimum CPU detection early.
804 * Fields really needed: vendor, cpuid_level, family, model, mask,
806 * The others are not touched to avoid unwanted side effects.
808 * WARNING: this function is only called on the BP. Don't add code here
809 * that is supposed to run on all CPUs.
811 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
814 c
->x86_clflush_size
= 64;
815 c
->x86_phys_bits
= 36;
816 c
->x86_virt_bits
= 48;
818 c
->x86_clflush_size
= 32;
819 c
->x86_phys_bits
= 32;
820 c
->x86_virt_bits
= 32;
822 c
->x86_cache_alignment
= c
->x86_clflush_size
;
824 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
825 c
->extended_cpuid_level
= 0;
827 /* cyrix could have cpuid enabled via c_identify()*/
828 if (have_cpuid_p()) {
832 setup_force_cpu_cap(X86_FEATURE_CPUID
);
834 if (this_cpu
->c_early_init
)
835 this_cpu
->c_early_init(c
);
838 filter_cpuid_features(c
, false);
840 if (this_cpu
->c_bsp_init
)
841 this_cpu
->c_bsp_init(c
);
843 identify_cpu_without_cpuid(c
);
844 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
847 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
851 void __init
early_cpu_init(void)
853 const struct cpu_dev
*const *cdev
;
856 #ifdef CONFIG_PROCESSOR_SELECT
857 pr_info("KERNEL supported cpus:\n");
860 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
861 const struct cpu_dev
*cpudev
= *cdev
;
863 if (count
>= X86_VENDOR_NUM
)
865 cpu_devs
[count
] = cpudev
;
868 #ifdef CONFIG_PROCESSOR_SELECT
872 for (j
= 0; j
< 2; j
++) {
873 if (!cpudev
->c_ident
[j
])
875 pr_info(" %s %s\n", cpudev
->c_vendor
,
881 early_identify_cpu(&boot_cpu_data
);
885 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
886 * unfortunately, that's not true in practice because of early VIA
887 * chips and (more importantly) broken virtualizers that are not easy
888 * to detect. In the latter case it doesn't even *fail* reliably, so
889 * probing for it doesn't even work. Disable it completely on 32-bit
890 * unless we can find a reliable way to detect all the broken cases.
891 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
893 static void detect_nopl(struct cpuinfo_x86
*c
)
896 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
898 set_cpu_cap(c
, X86_FEATURE_NOPL
);
902 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
906 * Empirically, writing zero to a segment selector on AMD does
907 * not clear the base, whereas writing zero to a segment
908 * selector on Intel does clear the base. Intel's behavior
909 * allows slightly faster context switches in the common case
910 * where GS is unused by the prev and next threads.
912 * Since neither vendor documents this anywhere that I can see,
913 * detect it directly instead of hardcoding the choice by
916 * I've designated AMD's behavior as the "bug" because it's
917 * counterintuitive and less friendly.
920 unsigned long old_base
, tmp
;
921 rdmsrl(MSR_FS_BASE
, old_base
);
922 wrmsrl(MSR_FS_BASE
, 1);
924 rdmsrl(MSR_FS_BASE
, tmp
);
926 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
927 wrmsrl(MSR_FS_BASE
, old_base
);
931 static void generic_identify(struct cpuinfo_x86
*c
)
933 c
->extended_cpuid_level
= 0;
936 identify_cpu_without_cpuid(c
);
938 /* cyrix could have cpuid enabled via c_identify()*/
948 if (c
->cpuid_level
>= 0x00000001) {
949 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
952 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
954 c
->apicid
= c
->initial_apicid
;
957 c
->phys_proc_id
= c
->initial_apicid
;
960 get_model_name(c
); /* Default name */
964 detect_null_seg_behavior(c
);
967 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
968 * systems that run Linux at CPL > 0 may or may not have the
969 * issue, but, even if they have the issue, there's absolutely
970 * nothing we can do about it because we can't use the real IRET
973 * NB: For the time being, only 32-bit kernels support
974 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
975 * whether to apply espfix using paravirt hooks. If any
976 * non-paravirt system ever shows up that does *not* have the
977 * ESPFIX issue, we can change this.
980 # ifdef CONFIG_PARAVIRT
982 extern void native_iret(void);
983 if (pv_cpu_ops
.iret
== native_iret
)
984 set_cpu_bug(c
, X86_BUG_ESPFIX
);
987 set_cpu_bug(c
, X86_BUG_ESPFIX
);
992 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
995 * The heavy lifting of max_rmid and cache_occ_scale are handled
996 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
997 * in case CQM bits really aren't there in this CPU.
999 if (c
!= &boot_cpu_data
) {
1000 boot_cpu_data
.x86_cache_max_rmid
=
1001 min(boot_cpu_data
.x86_cache_max_rmid
,
1002 c
->x86_cache_max_rmid
);
1007 * Validate that ACPI/mptables have the same information about the
1008 * effective APIC id and update the package map.
1010 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1013 unsigned int apicid
, cpu
= smp_processor_id();
1015 apicid
= apic
->cpu_present_to_apicid(cpu
);
1017 if (apicid
!= c
->apicid
) {
1018 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1019 cpu
, apicid
, c
->initial_apicid
);
1021 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1023 c
->logical_proc_id
= 0;
1028 * This does the hard work of actually picking apart the CPU stuff...
1030 static void identify_cpu(struct cpuinfo_x86
*c
)
1034 c
->loops_per_jiffy
= loops_per_jiffy
;
1035 c
->x86_cache_size
= -1;
1036 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1037 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
1038 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1039 c
->x86_model_id
[0] = '\0'; /* Unset */
1040 c
->x86_max_cores
= 1;
1041 c
->x86_coreid_bits
= 0;
1043 #ifdef CONFIG_X86_64
1044 c
->x86_clflush_size
= 64;
1045 c
->x86_phys_bits
= 36;
1046 c
->x86_virt_bits
= 48;
1048 c
->cpuid_level
= -1; /* CPUID not detected */
1049 c
->x86_clflush_size
= 32;
1050 c
->x86_phys_bits
= 32;
1051 c
->x86_virt_bits
= 32;
1053 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1054 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
1056 generic_identify(c
);
1058 if (this_cpu
->c_identify
)
1059 this_cpu
->c_identify(c
);
1061 /* Clear/Set all flags overridden by options, after probe */
1062 apply_forced_caps(c
);
1064 #ifdef CONFIG_X86_64
1065 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1069 * Vendor-specific initialization. In this section we
1070 * canonicalize the feature flags, meaning if there are
1071 * features a certain CPU supports which CPUID doesn't
1072 * tell us, CPUID claiming incorrect flags, or other bugs,
1073 * we handle them here.
1075 * At the end of this section, c->x86_capability better
1076 * indicate the features this CPU genuinely supports!
1078 if (this_cpu
->c_init
)
1079 this_cpu
->c_init(c
);
1081 clear_sched_clock_stable();
1083 /* Disable the PN if appropriate */
1084 squash_the_stupid_serial_number(c
);
1086 /* Set up SMEP/SMAP */
1091 * The vendor-specific functions might have changed features.
1092 * Now we do "generic changes."
1095 /* Filter out anything that depends on CPUID levels we don't have */
1096 filter_cpuid_features(c
, true);
1098 /* If the model name is still unset, do table lookup. */
1099 if (!c
->x86_model_id
[0]) {
1101 p
= table_lookup_model(c
);
1103 strcpy(c
->x86_model_id
, p
);
1105 /* Last resort... */
1106 sprintf(c
->x86_model_id
, "%02x/%02x",
1107 c
->x86
, c
->x86_model
);
1110 #ifdef CONFIG_X86_64
1116 x86_init_cache_qos(c
);
1120 * Clear/Set all flags overridden by options, need do it
1121 * before following smp all cpus cap AND.
1123 apply_forced_caps(c
);
1126 * On SMP, boot_cpu_data holds the common feature set between
1127 * all CPUs; so make sure that we indicate which features are
1128 * common between the CPUs. The first time this routine gets
1129 * executed, c == &boot_cpu_data.
1131 if (c
!= &boot_cpu_data
) {
1132 /* AND the already accumulated flags with these */
1133 for (i
= 0; i
< NCAPINTS
; i
++)
1134 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1136 /* OR, i.e. replicate the bug flags */
1137 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1138 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1141 /* Init Machine Check Exception if available. */
1144 select_idle_routine(c
);
1147 numa_add_cpu(smp_processor_id());
1152 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1153 * on 32-bit kernels:
1155 #ifdef CONFIG_X86_32
1156 void enable_sep_cpu(void)
1158 struct tss_struct
*tss
;
1161 if (!boot_cpu_has(X86_FEATURE_SEP
))
1165 tss
= &per_cpu(cpu_tss
, cpu
);
1168 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1169 * see the big comment in struct x86_hw_tss's definition.
1172 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1173 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1175 wrmsr(MSR_IA32_SYSENTER_ESP
,
1176 (unsigned long)tss
+ offsetofend(struct tss_struct
, SYSENTER_stack
),
1179 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1185 void __init
identify_boot_cpu(void)
1187 identify_cpu(&boot_cpu_data
);
1188 #ifdef CONFIG_X86_32
1192 cpu_detect_tlb(&boot_cpu_data
);
1195 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1197 BUG_ON(c
== &boot_cpu_data
);
1199 #ifdef CONFIG_X86_32
1203 validate_apic_and_package_id(c
);
1206 static __init
int setup_noclflush(char *arg
)
1208 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1209 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1212 __setup("noclflush", setup_noclflush
);
1214 void print_cpu_info(struct cpuinfo_x86
*c
)
1216 const char *vendor
= NULL
;
1218 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1219 vendor
= this_cpu
->c_vendor
;
1221 if (c
->cpuid_level
>= 0)
1222 vendor
= c
->x86_vendor_id
;
1225 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1226 pr_cont("%s ", vendor
);
1228 if (c
->x86_model_id
[0])
1229 pr_cont("%s", c
->x86_model_id
);
1231 pr_cont("%d86", c
->x86
);
1233 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1235 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
1236 pr_cont(", stepping: 0x%x)\n", c
->x86_mask
);
1241 static __init
int setup_disablecpuid(char *arg
)
1245 if (get_option(&arg
, &bit
) && bit
>= 0 && bit
< NCAPINTS
* 32)
1246 setup_clear_cpu_cap(bit
);
1252 __setup("clearcpuid=", setup_disablecpuid
);
1254 #ifdef CONFIG_X86_64
1255 struct desc_ptr idt_descr __ro_after_init
= {
1256 .size
= NR_VECTORS
* 16 - 1,
1257 .address
= (unsigned long) idt_table
,
1259 const struct desc_ptr debug_idt_descr
= {
1260 .size
= NR_VECTORS
* 16 - 1,
1261 .address
= (unsigned long) debug_idt_table
,
1264 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
1265 irq_stack_union
) __aligned(PAGE_SIZE
) __visible
;
1268 * The following percpu variables are hot. Align current_task to
1269 * cacheline size such that they fall in the same cacheline.
1271 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1273 EXPORT_PER_CPU_SYMBOL(current_task
);
1275 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
1276 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
;
1278 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1280 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1281 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1284 * Special IST stacks which the CPU switches to when it calls
1285 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1286 * limit), all of them are 4K, except the debug stack which
1289 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
1290 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1291 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1294 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1295 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
]);
1297 /* May not be marked __init: used by software suspend */
1298 void syscall_init(void)
1300 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1301 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1303 #ifdef CONFIG_IA32_EMULATION
1304 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1306 * This only works on Intel CPUs.
1307 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1308 * This does not cause SYSENTER to jump to the wrong location, because
1309 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1311 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1312 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1313 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1315 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1316 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1317 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1318 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1321 /* Flags to clear on syscall */
1322 wrmsrl(MSR_SYSCALL_MASK
,
1323 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1324 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1328 * Copies of the original ist values from the tss are only accessed during
1329 * debugging, no special alignment required.
1331 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1333 static DEFINE_PER_CPU(unsigned long, debug_stack_addr
);
1334 DEFINE_PER_CPU(int, debug_stack_usage
);
1336 int is_debug_stack(unsigned long addr
)
1338 return __this_cpu_read(debug_stack_usage
) ||
1339 (addr
<= __this_cpu_read(debug_stack_addr
) &&
1340 addr
> (__this_cpu_read(debug_stack_addr
) - DEBUG_STKSZ
));
1342 NOKPROBE_SYMBOL(is_debug_stack
);
1344 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1346 void debug_stack_set_zero(void)
1348 this_cpu_inc(debug_idt_ctr
);
1351 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1353 void debug_stack_reset(void)
1355 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1357 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1360 NOKPROBE_SYMBOL(debug_stack_reset
);
1362 #else /* CONFIG_X86_64 */
1364 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1365 EXPORT_PER_CPU_SYMBOL(current_task
);
1366 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1367 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1370 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1371 * the top of the kernel stack. Use an extra percpu variable to track the
1372 * top of the kernel stack directly.
1374 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1375 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1376 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1378 #ifdef CONFIG_CC_STACKPROTECTOR
1379 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1382 #endif /* CONFIG_X86_64 */
1385 * Clear all 6 debug registers:
1387 static void clear_all_debug_regs(void)
1391 for (i
= 0; i
< 8; i
++) {
1392 /* Ignore db4, db5 */
1393 if ((i
== 4) || (i
== 5))
1402 * Restore debug regs if using kgdbwait and you have a kernel debugger
1403 * connection established.
1405 static void dbg_restore_debug_regs(void)
1407 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1408 arch_kgdb_ops
.correct_hw_break();
1410 #else /* ! CONFIG_KGDB */
1411 #define dbg_restore_debug_regs()
1412 #endif /* ! CONFIG_KGDB */
1414 static void wait_for_master_cpu(int cpu
)
1418 * wait for ACK from master CPU before continuing
1419 * with AP initialization
1421 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1422 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1428 * cpu_init() initializes state that is per-CPU. Some data is already
1429 * initialized (naturally) in the bootstrap process, such as the GDT
1430 * and IDT. We reload them nevertheless, this function acts as a
1431 * 'CPU state barrier', nothing should get across.
1432 * A lot of state is already set up in PDA init for 64 bit
1434 #ifdef CONFIG_X86_64
1438 struct orig_ist
*oist
;
1439 struct task_struct
*me
;
1440 struct tss_struct
*t
;
1442 int cpu
= raw_smp_processor_id();
1445 wait_for_master_cpu(cpu
);
1448 * Initialize the CR4 shadow before doing anything that could
1456 t
= &per_cpu(cpu_tss
, cpu
);
1457 oist
= &per_cpu(orig_ist
, cpu
);
1460 if (this_cpu_read(numa_node
) == 0 &&
1461 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1462 set_numa_node(early_cpu_to_node(cpu
));
1467 pr_debug("Initializing CPU#%d\n", cpu
);
1469 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1472 * Initialize the per-CPU GDT with the boot GDT,
1473 * and set up the GDT descriptor:
1476 switch_to_new_gdt(cpu
);
1481 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1484 wrmsrl(MSR_FS_BASE
, 0);
1485 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1492 * set up and load the per-CPU TSS
1494 if (!oist
->ist
[0]) {
1495 char *estacks
= per_cpu(exception_stacks
, cpu
);
1497 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1498 estacks
+= exception_stack_sizes
[v
];
1499 oist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1500 (unsigned long)estacks
;
1501 if (v
== DEBUG_STACK
-1)
1502 per_cpu(debug_stack_addr
, cpu
) = (unsigned long)estacks
;
1506 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1509 * <= is required because the CPU will access up to
1510 * 8 bits beyond the end of the IO permission bitmap.
1512 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1513 t
->io_bitmap
[i
] = ~0UL;
1516 me
->active_mm
= &init_mm
;
1518 enter_lazy_tlb(&init_mm
, me
);
1520 load_sp0(t
, ¤t
->thread
);
1521 set_tss_desc(cpu
, t
);
1523 load_mm_ldt(&init_mm
);
1525 clear_all_debug_regs();
1526 dbg_restore_debug_regs();
1538 int cpu
= smp_processor_id();
1539 struct task_struct
*curr
= current
;
1540 struct tss_struct
*t
= &per_cpu(cpu_tss
, cpu
);
1541 struct thread_struct
*thread
= &curr
->thread
;
1543 wait_for_master_cpu(cpu
);
1546 * Initialize the CR4 shadow before doing anything that could
1551 show_ucode_info_early();
1553 pr_info("Initializing CPU#%d\n", cpu
);
1555 if (cpu_feature_enabled(X86_FEATURE_VME
) ||
1556 boot_cpu_has(X86_FEATURE_TSC
) ||
1557 boot_cpu_has(X86_FEATURE_DE
))
1558 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1561 switch_to_new_gdt(cpu
);
1564 * Set up and load the per-CPU TSS and LDT
1567 curr
->active_mm
= &init_mm
;
1569 enter_lazy_tlb(&init_mm
, curr
);
1571 load_sp0(t
, thread
);
1572 set_tss_desc(cpu
, t
);
1574 load_mm_ldt(&init_mm
);
1576 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1578 #ifdef CONFIG_DOUBLEFAULT
1579 /* Set up doublefault TSS pointer in the GDT */
1580 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1583 clear_all_debug_regs();
1584 dbg_restore_debug_regs();
1590 static void bsp_resume(void)
1592 if (this_cpu
->c_bsp_resume
)
1593 this_cpu
->c_bsp_resume(&boot_cpu_data
);
1596 static struct syscore_ops cpu_syscore_ops
= {
1597 .resume
= bsp_resume
,
1600 static int __init
init_cpu_syscore(void)
1602 register_syscore_ops(&cpu_syscore_ops
);
1605 core_initcall(init_cpu_syscore
);