1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
24 #ifdef CONFIG_X86_LOCAL_APIC
25 #include <asm/mpspec.h>
27 #include <mach_apic.h>
28 #include <asm/genapic.h>
32 #include <asm/pgtable.h>
33 #include <asm/processor.h>
35 #include <asm/atomic.h>
36 #include <asm/proto.h>
37 #include <asm/sections.h>
38 #include <asm/setup.h>
39 #include <asm/hypervisor.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_callin_mask
;
47 cpumask_var_t cpu_callout_mask
;
48 cpumask_var_t cpu_initialized_mask
;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask
;
53 #else /* CONFIG_X86_32 */
55 cpumask_t cpu_callin_map
;
56 cpumask_t cpu_callout_map
;
57 cpumask_t cpu_initialized
;
58 cpumask_t cpu_sibling_setup_map
;
60 #endif /* CONFIG_X86_32 */
63 static struct cpu_dev
*this_cpu __cpuinitdata
;
66 /* We need valid kernel segments for data and code in long mode too
67 * IRET will check the segment types kkeil 2000/10/28
68 * Also sysret mandates a special GDT layout
70 /* The TLS descriptors are currently at a different place compared to i386.
71 Hopefully nobody expects them at a fixed place (Wine?) */
72 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
73 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
74 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
75 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
76 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
77 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
78 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
81 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
82 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
83 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
84 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
85 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
87 * Segments used for calling PnP BIOS have byte granularity.
88 * They code segments and data segments have fixed 64k limits,
89 * the transfer segment sizes are set at run time.
92 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
94 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
96 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
98 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
100 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
102 * The APM segments have byte granularity and their bases
103 * are set at run time. All have 64k limits.
106 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
108 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
110 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
112 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
113 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
116 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
119 static int cachesize_override __cpuinitdata
= -1;
120 static int disable_x86_serial_nr __cpuinitdata
= 1;
122 static int __init
cachesize_setup(char *str
)
124 get_option(&str
, &cachesize_override
);
127 __setup("cachesize=", cachesize_setup
);
129 static int __init
x86_fxsr_setup(char *s
)
131 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
132 setup_clear_cpu_cap(X86_FEATURE_XMM
);
135 __setup("nofxsr", x86_fxsr_setup
);
137 static int __init
x86_sep_setup(char *s
)
139 setup_clear_cpu_cap(X86_FEATURE_SEP
);
142 __setup("nosep", x86_sep_setup
);
144 /* Standard macro to see if a specific flag is changeable */
145 static inline int flag_is_changeable_p(u32 flag
)
150 * Cyrix and IDT cpus allow disabling of CPUID
151 * so the code below may return different results
152 * when it is executed before and after enabling
153 * the CPUID. Add "volatile" to not allow gcc to
154 * optimize the subsequent calls to this function.
156 asm volatile ("pushfl\n\t"
166 : "=&r" (f1
), "=&r" (f2
)
169 return ((f1
^f2
) & flag
) != 0;
172 /* Probe for the CPUID instruction */
173 static int __cpuinit
have_cpuid_p(void)
175 return flag_is_changeable_p(X86_EFLAGS_ID
);
178 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
180 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
181 /* Disable processor serial number */
182 unsigned long lo
, hi
;
183 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
185 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
186 printk(KERN_NOTICE
"CPU serial number disabled.\n");
187 clear_cpu_cap(c
, X86_FEATURE_PN
);
189 /* Disabling the serial number may affect the cpuid level */
190 c
->cpuid_level
= cpuid_eax(0);
194 static int __init
x86_serial_nr_setup(char *s
)
196 disable_x86_serial_nr
= 0;
199 __setup("serialnumber", x86_serial_nr_setup
);
201 static inline int flag_is_changeable_p(u32 flag
)
205 /* Probe for the CPUID instruction */
206 static inline int have_cpuid_p(void)
210 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
216 * Naming convention should be: <Name> [(<Codename>)]
217 * This table only is used unless init_<vendor>() below doesn't set it;
218 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
222 /* Look up CPU names by table lookup. */
223 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
225 struct cpu_model_info
*info
;
227 if (c
->x86_model
>= 16)
228 return NULL
; /* Range check */
233 info
= this_cpu
->c_models
;
235 while (info
&& info
->family
) {
236 if (info
->family
== c
->x86
)
237 return info
->model_names
[c
->x86_model
];
240 return NULL
; /* Not found */
243 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
245 /* Current gdt points %fs at the "master" per-cpu area: after this,
246 * it's on the real one. */
247 void switch_to_new_gdt(void)
249 struct desc_ptr gdt_descr
;
251 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
252 gdt_descr
.size
= GDT_SIZE
- 1;
253 load_gdt(&gdt_descr
);
255 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU
) : "memory");
259 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
261 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
264 display_cacheinfo(c
);
266 /* Not much we can do here... */
267 /* Check if at least it has cpuid */
268 if (c
->cpuid_level
== -1) {
269 /* No cpuid. It must be an ancient CPU */
271 strcpy(c
->x86_model_id
, "486");
272 else if (c
->x86
== 3)
273 strcpy(c
->x86_model_id
, "386");
278 static struct cpu_dev __cpuinitdata default_cpu
= {
279 .c_init
= default_init
,
280 .c_vendor
= "Unknown",
281 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
284 static void __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
289 if (c
->extended_cpuid_level
< 0x80000004)
292 v
= (unsigned int *) c
->x86_model_id
;
293 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
294 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
295 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
296 c
->x86_model_id
[48] = 0;
298 /* Intel chips right-justify this string for some dumb reason;
299 undo that brain damage */
300 p
= q
= &c
->x86_model_id
[0];
306 while (q
<= &c
->x86_model_id
[48])
307 *q
++ = '\0'; /* Zero-pad the rest */
311 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
313 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
315 n
= c
->extended_cpuid_level
;
317 if (n
>= 0x80000005) {
318 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
319 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
320 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
321 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
323 /* On K8 L1 TLB is inclusive, so don't count it */
328 if (n
< 0x80000006) /* Some chips just has a large L1. */
331 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
335 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
337 /* do processor-specific cache resizing */
338 if (this_cpu
->c_size_cache
)
339 l2size
= this_cpu
->c_size_cache(c
, l2size
);
341 /* Allow user to override all this if necessary. */
342 if (cachesize_override
!= -1)
343 l2size
= cachesize_override
;
346 return; /* Again, no L2 cache is possible */
349 c
->x86_cache_size
= l2size
;
351 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
355 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
358 u32 eax
, ebx
, ecx
, edx
;
359 int index_msb
, core_bits
;
361 if (!cpu_has(c
, X86_FEATURE_HT
))
364 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
367 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
370 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
372 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
374 if (smp_num_siblings
== 1) {
375 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
376 } else if (smp_num_siblings
> 1) {
378 if (smp_num_siblings
> nr_cpu_ids
) {
379 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
381 smp_num_siblings
= 1;
385 index_msb
= get_count_order(smp_num_siblings
);
387 c
->phys_proc_id
= phys_pkg_id(index_msb
);
389 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
392 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
394 index_msb
= get_count_order(smp_num_siblings
);
396 core_bits
= get_count_order(c
->x86_max_cores
);
399 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
400 ((1 << core_bits
) - 1);
402 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
403 ((1 << core_bits
) - 1);
408 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
409 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
411 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
417 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
419 char *v
= c
->x86_vendor_id
;
423 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
427 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
428 (cpu_devs
[i
]->c_ident
[1] &&
429 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
430 this_cpu
= cpu_devs
[i
];
431 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
438 printk(KERN_ERR
"CPU: vendor_id '%s' unknown, using generic init.\n", v
);
439 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
442 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
443 this_cpu
= &default_cpu
;
446 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
448 /* Get vendor name */
449 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
450 (unsigned int *)&c
->x86_vendor_id
[0],
451 (unsigned int *)&c
->x86_vendor_id
[8],
452 (unsigned int *)&c
->x86_vendor_id
[4]);
455 /* Intel-defined flags: level 0x00000001 */
456 if (c
->cpuid_level
>= 0x00000001) {
457 u32 junk
, tfms
, cap0
, misc
;
458 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
459 c
->x86
= (tfms
>> 8) & 0xf;
460 c
->x86_model
= (tfms
>> 4) & 0xf;
461 c
->x86_mask
= tfms
& 0xf;
463 c
->x86
+= (tfms
>> 20) & 0xff;
465 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
466 if (cap0
& (1<<19)) {
467 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
468 c
->x86_cache_alignment
= c
->x86_clflush_size
;
473 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
478 /* Intel-defined flags: level 0x00000001 */
479 if (c
->cpuid_level
>= 0x00000001) {
480 u32 capability
, excap
;
481 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
482 c
->x86_capability
[0] = capability
;
483 c
->x86_capability
[4] = excap
;
486 /* AMD-defined flags: level 0x80000001 */
487 xlvl
= cpuid_eax(0x80000000);
488 c
->extended_cpuid_level
= xlvl
;
489 if ((xlvl
& 0xffff0000) == 0x80000000) {
490 if (xlvl
>= 0x80000001) {
491 c
->x86_capability
[1] = cpuid_edx(0x80000001);
492 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
497 if (c
->extended_cpuid_level
>= 0x80000008) {
498 u32 eax
= cpuid_eax(0x80000008);
500 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
501 c
->x86_phys_bits
= eax
& 0xff;
505 if (c
->extended_cpuid_level
>= 0x80000007)
506 c
->x86_power
= cpuid_edx(0x80000007);
510 static void __cpuinit
identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
516 * First of all, decide if this is a 486 or higher
517 * It's a 486 if we can modify the AC flag
519 if (flag_is_changeable_p(X86_EFLAGS_AC
))
524 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
525 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
526 c
->x86_vendor_id
[0] = 0;
527 cpu_devs
[i
]->c_identify(c
);
528 if (c
->x86_vendor_id
[0]) {
537 * Do minimum CPU detection early.
538 * Fields really needed: vendor, cpuid_level, family, model, mask,
540 * The others are not touched to avoid unwanted side effects.
542 * WARNING: this function is only called on the BP. Don't add code here
543 * that is supposed to run on all CPUs.
545 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
548 c
->x86_clflush_size
= 64;
550 c
->x86_clflush_size
= 32;
552 c
->x86_cache_alignment
= c
->x86_clflush_size
;
554 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
555 c
->extended_cpuid_level
= 0;
558 identify_cpu_without_cpuid(c
);
560 /* cyrix could have cpuid enabled via c_identify()*/
570 if (this_cpu
->c_early_init
)
571 this_cpu
->c_early_init(c
);
573 validate_pat_support(c
);
576 c
->cpu_index
= boot_cpu_id
;
580 void __init
early_cpu_init(void)
582 struct cpu_dev
**cdev
;
585 printk("KERNEL supported cpus:\n");
586 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
587 struct cpu_dev
*cpudev
= *cdev
;
590 if (count
>= X86_VENDOR_NUM
)
592 cpu_devs
[count
] = cpudev
;
595 for (j
= 0; j
< 2; j
++) {
596 if (!cpudev
->c_ident
[j
])
598 printk(" %s %s\n", cpudev
->c_vendor
,
603 early_identify_cpu(&boot_cpu_data
);
607 * The NOPL instruction is supposed to exist on all CPUs with
608 * family >= 6; unfortunately, that's not true in practice because
609 * of early VIA chips and (more importantly) broken virtualizers that
610 * are not easy to detect. In the latter case it doesn't even *fail*
611 * reliably, so probing for it doesn't even work. Disable it completely
612 * unless we can find a reliable way to detect all the broken cases.
614 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
616 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
619 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
621 c
->extended_cpuid_level
= 0;
624 identify_cpu_without_cpuid(c
);
626 /* cyrix could have cpuid enabled via c_identify()*/
636 if (c
->cpuid_level
>= 0x00000001) {
637 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
639 # ifdef CONFIG_X86_HT
640 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
642 c
->apicid
= c
->initial_apicid
;
647 c
->phys_proc_id
= c
->initial_apicid
;
651 get_model_name(c
); /* Default name */
653 init_scattered_cpuid_features(c
);
658 * This does the hard work of actually picking apart the CPU stuff...
660 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
664 c
->loops_per_jiffy
= loops_per_jiffy
;
665 c
->x86_cache_size
= -1;
666 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
667 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
668 c
->x86_vendor_id
[0] = '\0'; /* Unset */
669 c
->x86_model_id
[0] = '\0'; /* Unset */
670 c
->x86_max_cores
= 1;
671 c
->x86_coreid_bits
= 0;
673 c
->x86_clflush_size
= 64;
675 c
->cpuid_level
= -1; /* CPUID not detected */
676 c
->x86_clflush_size
= 32;
678 c
->x86_cache_alignment
= c
->x86_clflush_size
;
679 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
683 if (this_cpu
->c_identify
)
684 this_cpu
->c_identify(c
);
687 c
->apicid
= phys_pkg_id(0);
691 * Vendor-specific initialization. In this section we
692 * canonicalize the feature flags, meaning if there are
693 * features a certain CPU supports which CPUID doesn't
694 * tell us, CPUID claiming incorrect flags, or other bugs,
695 * we handle them here.
697 * At the end of this section, c->x86_capability better
698 * indicate the features this CPU genuinely supports!
700 if (this_cpu
->c_init
)
703 /* Disable the PN if appropriate */
704 squash_the_stupid_serial_number(c
);
707 * The vendor-specific functions might have changed features. Now
708 * we do "generic changes."
711 /* If the model name is still unset, do table lookup. */
712 if (!c
->x86_model_id
[0]) {
714 p
= table_lookup_model(c
);
716 strcpy(c
->x86_model_id
, p
);
719 sprintf(c
->x86_model_id
, "%02x/%02x",
720 c
->x86
, c
->x86_model
);
729 * On SMP, boot_cpu_data holds the common feature set between
730 * all CPUs; so make sure that we indicate which features are
731 * common between the CPUs. The first time this routine gets
732 * executed, c == &boot_cpu_data.
734 if (c
!= &boot_cpu_data
) {
735 /* AND the already accumulated flags with these */
736 for (i
= 0; i
< NCAPINTS
; i
++)
737 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
740 /* Clear all flags overriden by options */
741 for (i
= 0; i
< NCAPINTS
; i
++)
742 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
744 #ifdef CONFIG_X86_MCE
745 /* Init Machine Check Exception if available. */
749 select_idle_routine(c
);
751 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
752 numa_add_cpu(smp_processor_id());
757 static void vgetcpu_set_mode(void)
759 if (cpu_has(&boot_cpu_data
, X86_FEATURE_RDTSCP
))
760 vgetcpu_mode
= VGETCPU_RDTSCP
;
762 vgetcpu_mode
= VGETCPU_LSL
;
766 void __init
identify_boot_cpu(void)
768 identify_cpu(&boot_cpu_data
);
777 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
779 BUG_ON(c
== &boot_cpu_data
);
792 static struct msr_range msr_range_array
[] __cpuinitdata
= {
793 { 0x00000000, 0x00000418},
794 { 0xc0000000, 0xc000040b},
795 { 0xc0010000, 0xc0010142},
796 { 0xc0011000, 0xc001103b},
799 static void __cpuinit
print_cpu_msr(void)
804 unsigned index_min
, index_max
;
806 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
807 index_min
= msr_range_array
[i
].min
;
808 index_max
= msr_range_array
[i
].max
;
809 for (index
= index_min
; index
< index_max
; index
++) {
810 if (rdmsrl_amd_safe(index
, &val
))
812 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
817 static int show_msr __cpuinitdata
;
818 static __init
int setup_show_msr(char *arg
)
822 get_option(&arg
, &num
);
828 __setup("show_msr=", setup_show_msr
);
830 static __init
int setup_noclflush(char *arg
)
832 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
835 __setup("noclflush", setup_noclflush
);
837 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
841 if (c
->x86_vendor
< X86_VENDOR_NUM
)
842 vendor
= this_cpu
->c_vendor
;
843 else if (c
->cpuid_level
>= 0)
844 vendor
= c
->x86_vendor_id
;
846 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
847 printk(KERN_CONT
"%s ", vendor
);
849 if (c
->x86_model_id
[0])
850 printk(KERN_CONT
"%s", c
->x86_model_id
);
852 printk(KERN_CONT
"%d86", c
->x86
);
854 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
855 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
857 printk(KERN_CONT
"\n");
860 if (c
->cpu_index
< show_msr
)
868 static __init
int setup_disablecpuid(char *arg
)
871 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
872 setup_clear_cpu_cap(bit
);
877 __setup("clearcpuid=", setup_disablecpuid
);
880 struct x8664_pda
**_cpu_pda __read_mostly
;
881 EXPORT_SYMBOL(_cpu_pda
);
883 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
885 static char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
887 void __cpuinit
pda_init(int cpu
)
889 struct x8664_pda
*pda
= cpu_pda(cpu
);
891 /* Setup up data that may be needed in __get_free_pages early */
894 /* Memory clobbers used to order PDA accessed */
896 wrmsrl(MSR_GS_BASE
, pda
);
899 pda
->cpunumber
= cpu
;
901 pda
->kernelstack
= (unsigned long)stack_thread_info() -
902 PDA_STACKOFFSET
+ THREAD_SIZE
;
903 pda
->active_mm
= &init_mm
;
907 /* others are initialized in smpboot.c */
908 pda
->pcurrent
= &init_task
;
909 pda
->irqstackptr
= boot_cpu_stack
;
910 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
912 if (!pda
->irqstackptr
) {
913 pda
->irqstackptr
= (char *)
914 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
915 if (!pda
->irqstackptr
)
916 panic("cannot allocate irqstack for cpu %d",
918 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
921 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
922 pda
->nodenumber
= cpu_to_node(cpu
);
926 static char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
927 DEBUG_STKSZ
] __page_aligned_bss
;
929 extern asmlinkage
void ignore_sysret(void);
931 /* May not be marked __init: used by software suspend */
932 void syscall_init(void)
935 * LSTAR and STAR live in a bit strange symbiosis.
936 * They both write to the same internal register. STAR allows to
937 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
939 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
940 wrmsrl(MSR_LSTAR
, system_call
);
941 wrmsrl(MSR_CSTAR
, ignore_sysret
);
943 #ifdef CONFIG_IA32_EMULATION
944 syscall32_cpu_init();
947 /* Flags to clear on syscall */
948 wrmsrl(MSR_SYSCALL_MASK
,
949 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
952 unsigned long kernel_eflags
;
955 * Copies of the original ist values from the tss are only accessed during
956 * debugging, no special alignment required.
958 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
962 /* Make sure %fs is initialized properly in idle threads */
963 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
965 memset(regs
, 0, sizeof(struct pt_regs
));
966 regs
->fs
= __KERNEL_PERCPU
;
972 * cpu_init() initializes state that is per-CPU. Some data is already
973 * initialized (naturally) in the bootstrap process, such as the GDT
974 * and IDT. We reload them nevertheless, this function acts as a
975 * 'CPU state barrier', nothing should get across.
976 * A lot of state is already set up in PDA init for 64 bit
979 void __cpuinit
cpu_init(void)
981 int cpu
= stack_smp_processor_id();
982 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
983 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
985 char *estacks
= NULL
;
986 struct task_struct
*me
;
989 /* CPU 0 is initialised in head64.c */
993 estacks
= boot_exception_stacks
;
997 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
))
998 panic("CPU#%d already initialized!\n", cpu
);
1000 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1002 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1005 * Initialize the per-CPU GDT with the boot GDT,
1006 * and set up the GDT descriptor:
1009 switch_to_new_gdt();
1010 load_idt((const struct desc_ptr
*)&idt_descr
);
1012 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1015 wrmsrl(MSR_FS_BASE
, 0);
1016 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1020 if (cpu
!= 0 && x2apic
)
1024 * set up and load the per-CPU TSS
1026 if (!orig_ist
->ist
[0]) {
1027 static const unsigned int order
[N_EXCEPTION_STACKS
] = {
1028 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STACK_ORDER
,
1029 [DEBUG_STACK
- 1] = DEBUG_STACK_ORDER
1031 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1033 estacks
= (char *)__get_free_pages(GFP_ATOMIC
, order
[v
]);
1035 panic("Cannot allocate exception "
1036 "stack %ld %d\n", v
, cpu
);
1038 estacks
+= PAGE_SIZE
<< order
[v
];
1039 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1040 (unsigned long)estacks
;
1044 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1046 * <= is required because the CPU will access up to
1047 * 8 bits beyond the end of the IO permission bitmap.
1049 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1050 t
->io_bitmap
[i
] = ~0UL;
1052 atomic_inc(&init_mm
.mm_count
);
1053 me
->active_mm
= &init_mm
;
1056 enter_lazy_tlb(&init_mm
, me
);
1058 load_sp0(t
, ¤t
->thread
);
1059 set_tss_desc(cpu
, t
);
1061 load_LDT(&init_mm
.context
);
1065 * If the kgdb is connected no debug regs should be altered. This
1066 * is only applicable when KGDB and a KGDB I/O module are built
1067 * into the kernel and you are using early debugging with
1068 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1070 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
1071 arch_kgdb_ops
.correct_hw_break();
1075 * Clear all 6 debug registers:
1078 set_debugreg(0UL, 0);
1079 set_debugreg(0UL, 1);
1080 set_debugreg(0UL, 2);
1081 set_debugreg(0UL, 3);
1082 set_debugreg(0UL, 6);
1083 set_debugreg(0UL, 7);
1085 /* If the kgdb is connected no debug regs should be altered. */
1091 raw_local_save_flags(kernel_eflags
);
1099 void __cpuinit
cpu_init(void)
1101 int cpu
= smp_processor_id();
1102 struct task_struct
*curr
= current
;
1103 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1104 struct thread_struct
*thread
= &curr
->thread
;
1106 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
)) {
1107 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1108 for (;;) local_irq_enable();
1111 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1113 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1114 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1116 load_idt(&idt_descr
);
1117 switch_to_new_gdt();
1120 * Set up and load the per-CPU TSS and LDT
1122 atomic_inc(&init_mm
.mm_count
);
1123 curr
->active_mm
= &init_mm
;
1126 enter_lazy_tlb(&init_mm
, curr
);
1128 load_sp0(t
, thread
);
1129 set_tss_desc(cpu
, t
);
1131 load_LDT(&init_mm
.context
);
1133 #ifdef CONFIG_DOUBLEFAULT
1134 /* Set up doublefault TSS pointer in the GDT */
1135 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1139 asm volatile ("mov %0, %%gs" : : "r" (0));
1141 /* Clear all 6 debug registers: */
1150 * Force FPU initialization:
1153 current_thread_info()->status
= TS_XSAVE
;
1155 current_thread_info()->status
= 0;
1157 mxcsr_feature_mask_init();
1160 * Boot processor to setup the FP and extended state context info.
1162 if (smp_processor_id() == boot_cpu_id
)
1163 init_thread_xstate();