1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
25 #include <asm/cpumask.h>
26 #ifdef CONFIG_X86_LOCAL_APIC
27 #include <asm/mpspec.h>
29 #include <mach_apic.h>
30 #include <asm/genapic.h>
31 #include <asm/uv/uv.h>
34 #include <asm/pgtable.h>
35 #include <asm/processor.h>
37 #include <asm/atomic.h>
38 #include <asm/proto.h>
39 #include <asm/sections.h>
40 #include <asm/setup.h>
41 #include <asm/hypervisor.h>
47 /* all of these masks are initialized in setup_cpu_local_masks() */
48 cpumask_var_t cpu_callin_mask
;
49 cpumask_var_t cpu_callout_mask
;
50 cpumask_var_t cpu_initialized_mask
;
52 /* representing cpus for which sibling maps can be computed */
53 cpumask_var_t cpu_sibling_setup_mask
;
55 /* correctly size the local cpu masks */
56 void setup_cpu_local_masks(void)
58 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
59 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
60 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
61 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
64 #else /* CONFIG_X86_32 */
66 cpumask_t cpu_callin_map
;
67 cpumask_t cpu_callout_map
;
68 cpumask_t cpu_initialized
;
69 cpumask_t cpu_sibling_setup_map
;
71 #endif /* CONFIG_X86_32 */
74 static struct cpu_dev
*this_cpu __cpuinitdata
;
76 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
79 * We need valid kernel segments for data and code in long mode too
80 * IRET will check the segment types kkeil 2000/10/28
81 * Also sysret mandates a special GDT layout
83 * The TLS descriptors are currently at a different place compared to i386.
84 * Hopefully nobody expects them at a fixed place (Wine?)
86 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
87 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
88 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
89 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
90 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
91 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
93 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
94 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
95 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
96 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
98 * Segments used for calling PnP BIOS have byte granularity.
99 * They code segments and data segments have fixed 64k limits,
100 * the transfer segment sizes are set at run time.
103 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
105 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
107 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
109 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
111 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
113 * The APM segments have byte granularity and their bases
114 * are set at run time. All have 64k limits.
117 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
119 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
121 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
123 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
124 [GDT_ENTRY_PERCPU
] = { { { 0x0000ffff, 0x00cf9200 } } },
127 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
130 static int cachesize_override __cpuinitdata
= -1;
131 static int disable_x86_serial_nr __cpuinitdata
= 1;
133 static int __init
cachesize_setup(char *str
)
135 get_option(&str
, &cachesize_override
);
138 __setup("cachesize=", cachesize_setup
);
140 static int __init
x86_fxsr_setup(char *s
)
142 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
143 setup_clear_cpu_cap(X86_FEATURE_XMM
);
146 __setup("nofxsr", x86_fxsr_setup
);
148 static int __init
x86_sep_setup(char *s
)
150 setup_clear_cpu_cap(X86_FEATURE_SEP
);
153 __setup("nosep", x86_sep_setup
);
155 /* Standard macro to see if a specific flag is changeable */
156 static inline int flag_is_changeable_p(u32 flag
)
161 * Cyrix and IDT cpus allow disabling of CPUID
162 * so the code below may return different results
163 * when it is executed before and after enabling
164 * the CPUID. Add "volatile" to not allow gcc to
165 * optimize the subsequent calls to this function.
167 asm volatile ("pushfl\n\t"
177 : "=&r" (f1
), "=&r" (f2
)
180 return ((f1
^f2
) & flag
) != 0;
183 /* Probe for the CPUID instruction */
184 static int __cpuinit
have_cpuid_p(void)
186 return flag_is_changeable_p(X86_EFLAGS_ID
);
189 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
191 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
192 /* Disable processor serial number */
193 unsigned long lo
, hi
;
194 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
196 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
197 printk(KERN_NOTICE
"CPU serial number disabled.\n");
198 clear_cpu_cap(c
, X86_FEATURE_PN
);
200 /* Disabling the serial number may affect the cpuid level */
201 c
->cpuid_level
= cpuid_eax(0);
205 static int __init
x86_serial_nr_setup(char *s
)
207 disable_x86_serial_nr
= 0;
210 __setup("serialnumber", x86_serial_nr_setup
);
212 static inline int flag_is_changeable_p(u32 flag
)
216 /* Probe for the CPUID instruction */
217 static inline int have_cpuid_p(void)
221 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
227 * Naming convention should be: <Name> [(<Codename>)]
228 * This table only is used unless init_<vendor>() below doesn't set it;
229 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
233 /* Look up CPU names by table lookup. */
234 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
236 struct cpu_model_info
*info
;
238 if (c
->x86_model
>= 16)
239 return NULL
; /* Range check */
244 info
= this_cpu
->c_models
;
246 while (info
&& info
->family
) {
247 if (info
->family
== c
->x86
)
248 return info
->model_names
[c
->x86_model
];
251 return NULL
; /* Not found */
254 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
256 /* Current gdt points %fs at the "master" per-cpu area: after this,
257 * it's on the real one. */
258 void switch_to_new_gdt(void)
260 struct desc_ptr gdt_descr
;
261 int cpu
= smp_processor_id();
263 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
264 gdt_descr
.size
= GDT_SIZE
- 1;
265 load_gdt(&gdt_descr
);
266 /* Reload the per-cpu base */
268 loadsegment(fs
, __KERNEL_PERCPU
);
271 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
275 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
277 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
280 display_cacheinfo(c
);
282 /* Not much we can do here... */
283 /* Check if at least it has cpuid */
284 if (c
->cpuid_level
== -1) {
285 /* No cpuid. It must be an ancient CPU */
287 strcpy(c
->x86_model_id
, "486");
288 else if (c
->x86
== 3)
289 strcpy(c
->x86_model_id
, "386");
294 static struct cpu_dev __cpuinitdata default_cpu
= {
295 .c_init
= default_init
,
296 .c_vendor
= "Unknown",
297 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
300 static void __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
305 if (c
->extended_cpuid_level
< 0x80000004)
308 v
= (unsigned int *) c
->x86_model_id
;
309 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
310 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
311 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
312 c
->x86_model_id
[48] = 0;
314 /* Intel chips right-justify this string for some dumb reason;
315 undo that brain damage */
316 p
= q
= &c
->x86_model_id
[0];
322 while (q
<= &c
->x86_model_id
[48])
323 *q
++ = '\0'; /* Zero-pad the rest */
327 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
329 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
331 n
= c
->extended_cpuid_level
;
333 if (n
>= 0x80000005) {
334 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
335 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
336 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
337 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
339 /* On K8 L1 TLB is inclusive, so don't count it */
344 if (n
< 0x80000006) /* Some chips just has a large L1. */
347 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
351 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
353 /* do processor-specific cache resizing */
354 if (this_cpu
->c_size_cache
)
355 l2size
= this_cpu
->c_size_cache(c
, l2size
);
357 /* Allow user to override all this if necessary. */
358 if (cachesize_override
!= -1)
359 l2size
= cachesize_override
;
362 return; /* Again, no L2 cache is possible */
365 c
->x86_cache_size
= l2size
;
367 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
371 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
374 u32 eax
, ebx
, ecx
, edx
;
375 int index_msb
, core_bits
;
377 if (!cpu_has(c
, X86_FEATURE_HT
))
380 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
383 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
386 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
388 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
390 if (smp_num_siblings
== 1) {
391 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
392 } else if (smp_num_siblings
> 1) {
394 if (smp_num_siblings
> nr_cpu_ids
) {
395 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
397 smp_num_siblings
= 1;
401 index_msb
= get_count_order(smp_num_siblings
);
403 c
->phys_proc_id
= phys_pkg_id(index_msb
);
405 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
408 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
410 index_msb
= get_count_order(smp_num_siblings
);
412 core_bits
= get_count_order(c
->x86_max_cores
);
415 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
416 ((1 << core_bits
) - 1);
418 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
419 ((1 << core_bits
) - 1);
424 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
425 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
427 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
433 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
435 char *v
= c
->x86_vendor_id
;
439 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
443 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
444 (cpu_devs
[i
]->c_ident
[1] &&
445 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
446 this_cpu
= cpu_devs
[i
];
447 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
454 printk(KERN_ERR
"CPU: vendor_id '%s' unknown, using generic init.\n", v
);
455 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
458 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
459 this_cpu
= &default_cpu
;
462 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
464 /* Get vendor name */
465 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
466 (unsigned int *)&c
->x86_vendor_id
[0],
467 (unsigned int *)&c
->x86_vendor_id
[8],
468 (unsigned int *)&c
->x86_vendor_id
[4]);
471 /* Intel-defined flags: level 0x00000001 */
472 if (c
->cpuid_level
>= 0x00000001) {
473 u32 junk
, tfms
, cap0
, misc
;
474 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
475 c
->x86
= (tfms
>> 8) & 0xf;
476 c
->x86_model
= (tfms
>> 4) & 0xf;
477 c
->x86_mask
= tfms
& 0xf;
479 c
->x86
+= (tfms
>> 20) & 0xff;
481 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
482 if (cap0
& (1<<19)) {
483 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
484 c
->x86_cache_alignment
= c
->x86_clflush_size
;
489 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
494 /* Intel-defined flags: level 0x00000001 */
495 if (c
->cpuid_level
>= 0x00000001) {
496 u32 capability
, excap
;
497 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
498 c
->x86_capability
[0] = capability
;
499 c
->x86_capability
[4] = excap
;
502 /* AMD-defined flags: level 0x80000001 */
503 xlvl
= cpuid_eax(0x80000000);
504 c
->extended_cpuid_level
= xlvl
;
505 if ((xlvl
& 0xffff0000) == 0x80000000) {
506 if (xlvl
>= 0x80000001) {
507 c
->x86_capability
[1] = cpuid_edx(0x80000001);
508 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
513 if (c
->extended_cpuid_level
>= 0x80000008) {
514 u32 eax
= cpuid_eax(0x80000008);
516 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
517 c
->x86_phys_bits
= eax
& 0xff;
521 if (c
->extended_cpuid_level
>= 0x80000007)
522 c
->x86_power
= cpuid_edx(0x80000007);
526 static void __cpuinit
identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
532 * First of all, decide if this is a 486 or higher
533 * It's a 486 if we can modify the AC flag
535 if (flag_is_changeable_p(X86_EFLAGS_AC
))
540 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
541 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
542 c
->x86_vendor_id
[0] = 0;
543 cpu_devs
[i
]->c_identify(c
);
544 if (c
->x86_vendor_id
[0]) {
553 * Do minimum CPU detection early.
554 * Fields really needed: vendor, cpuid_level, family, model, mask,
556 * The others are not touched to avoid unwanted side effects.
558 * WARNING: this function is only called on the BP. Don't add code here
559 * that is supposed to run on all CPUs.
561 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
564 c
->x86_clflush_size
= 64;
566 c
->x86_clflush_size
= 32;
568 c
->x86_cache_alignment
= c
->x86_clflush_size
;
570 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
571 c
->extended_cpuid_level
= 0;
574 identify_cpu_without_cpuid(c
);
576 /* cyrix could have cpuid enabled via c_identify()*/
586 if (this_cpu
->c_early_init
)
587 this_cpu
->c_early_init(c
);
589 validate_pat_support(c
);
592 c
->cpu_index
= boot_cpu_id
;
596 void __init
early_cpu_init(void)
598 struct cpu_dev
**cdev
;
601 printk("KERNEL supported cpus:\n");
602 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
603 struct cpu_dev
*cpudev
= *cdev
;
606 if (count
>= X86_VENDOR_NUM
)
608 cpu_devs
[count
] = cpudev
;
611 for (j
= 0; j
< 2; j
++) {
612 if (!cpudev
->c_ident
[j
])
614 printk(" %s %s\n", cpudev
->c_vendor
,
619 early_identify_cpu(&boot_cpu_data
);
623 * The NOPL instruction is supposed to exist on all CPUs with
624 * family >= 6; unfortunately, that's not true in practice because
625 * of early VIA chips and (more importantly) broken virtualizers that
626 * are not easy to detect. In the latter case it doesn't even *fail*
627 * reliably, so probing for it doesn't even work. Disable it completely
628 * unless we can find a reliable way to detect all the broken cases.
630 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
632 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
635 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
637 c
->extended_cpuid_level
= 0;
640 identify_cpu_without_cpuid(c
);
642 /* cyrix could have cpuid enabled via c_identify()*/
652 if (c
->cpuid_level
>= 0x00000001) {
653 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
655 # ifdef CONFIG_X86_HT
656 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
658 c
->apicid
= c
->initial_apicid
;
663 c
->phys_proc_id
= c
->initial_apicid
;
667 get_model_name(c
); /* Default name */
669 init_scattered_cpuid_features(c
);
674 * This does the hard work of actually picking apart the CPU stuff...
676 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
680 c
->loops_per_jiffy
= loops_per_jiffy
;
681 c
->x86_cache_size
= -1;
682 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
683 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
684 c
->x86_vendor_id
[0] = '\0'; /* Unset */
685 c
->x86_model_id
[0] = '\0'; /* Unset */
686 c
->x86_max_cores
= 1;
687 c
->x86_coreid_bits
= 0;
689 c
->x86_clflush_size
= 64;
691 c
->cpuid_level
= -1; /* CPUID not detected */
692 c
->x86_clflush_size
= 32;
694 c
->x86_cache_alignment
= c
->x86_clflush_size
;
695 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
699 if (this_cpu
->c_identify
)
700 this_cpu
->c_identify(c
);
703 c
->apicid
= phys_pkg_id(0);
707 * Vendor-specific initialization. In this section we
708 * canonicalize the feature flags, meaning if there are
709 * features a certain CPU supports which CPUID doesn't
710 * tell us, CPUID claiming incorrect flags, or other bugs,
711 * we handle them here.
713 * At the end of this section, c->x86_capability better
714 * indicate the features this CPU genuinely supports!
716 if (this_cpu
->c_init
)
719 /* Disable the PN if appropriate */
720 squash_the_stupid_serial_number(c
);
723 * The vendor-specific functions might have changed features. Now
724 * we do "generic changes."
727 /* If the model name is still unset, do table lookup. */
728 if (!c
->x86_model_id
[0]) {
730 p
= table_lookup_model(c
);
732 strcpy(c
->x86_model_id
, p
);
735 sprintf(c
->x86_model_id
, "%02x/%02x",
736 c
->x86
, c
->x86_model
);
745 * On SMP, boot_cpu_data holds the common feature set between
746 * all CPUs; so make sure that we indicate which features are
747 * common between the CPUs. The first time this routine gets
748 * executed, c == &boot_cpu_data.
750 if (c
!= &boot_cpu_data
) {
751 /* AND the already accumulated flags with these */
752 for (i
= 0; i
< NCAPINTS
; i
++)
753 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
756 /* Clear all flags overriden by options */
757 for (i
= 0; i
< NCAPINTS
; i
++)
758 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
760 #ifdef CONFIG_X86_MCE
761 /* Init Machine Check Exception if available. */
765 select_idle_routine(c
);
767 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
768 numa_add_cpu(smp_processor_id());
773 static void vgetcpu_set_mode(void)
775 if (cpu_has(&boot_cpu_data
, X86_FEATURE_RDTSCP
))
776 vgetcpu_mode
= VGETCPU_RDTSCP
;
778 vgetcpu_mode
= VGETCPU_LSL
;
782 void __init
identify_boot_cpu(void)
784 identify_cpu(&boot_cpu_data
);
793 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
795 BUG_ON(c
== &boot_cpu_data
);
808 static struct msr_range msr_range_array
[] __cpuinitdata
= {
809 { 0x00000000, 0x00000418},
810 { 0xc0000000, 0xc000040b},
811 { 0xc0010000, 0xc0010142},
812 { 0xc0011000, 0xc001103b},
815 static void __cpuinit
print_cpu_msr(void)
820 unsigned index_min
, index_max
;
822 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
823 index_min
= msr_range_array
[i
].min
;
824 index_max
= msr_range_array
[i
].max
;
825 for (index
= index_min
; index
< index_max
; index
++) {
826 if (rdmsrl_amd_safe(index
, &val
))
828 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
833 static int show_msr __cpuinitdata
;
834 static __init
int setup_show_msr(char *arg
)
838 get_option(&arg
, &num
);
844 __setup("show_msr=", setup_show_msr
);
846 static __init
int setup_noclflush(char *arg
)
848 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
851 __setup("noclflush", setup_noclflush
);
853 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
857 if (c
->x86_vendor
< X86_VENDOR_NUM
)
858 vendor
= this_cpu
->c_vendor
;
859 else if (c
->cpuid_level
>= 0)
860 vendor
= c
->x86_vendor_id
;
862 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
863 printk(KERN_CONT
"%s ", vendor
);
865 if (c
->x86_model_id
[0])
866 printk(KERN_CONT
"%s", c
->x86_model_id
);
868 printk(KERN_CONT
"%d86", c
->x86
);
870 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
871 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
873 printk(KERN_CONT
"\n");
876 if (c
->cpu_index
< show_msr
)
884 static __init
int setup_disablecpuid(char *arg
)
887 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
888 setup_clear_cpu_cap(bit
);
893 __setup("clearcpuid=", setup_disablecpuid
);
896 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
898 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
899 irq_stack_union
) __aligned(PAGE_SIZE
);
901 DEFINE_PER_CPU(char *, irq_stack_ptr
); /* will be set during per cpu init */
903 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
904 per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
- 64;
907 DEFINE_PER_CPU(unsigned long, kernel_stack
) =
908 (unsigned long)&init_thread_union
- KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
909 EXPORT_PER_CPU_SYMBOL(kernel_stack
);
911 DEFINE_PER_CPU(unsigned int, irq_count
) = -1;
913 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
914 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
])
915 __aligned(PAGE_SIZE
);
917 extern asmlinkage
void ignore_sysret(void);
919 /* May not be marked __init: used by software suspend */
920 void syscall_init(void)
923 * LSTAR and STAR live in a bit strange symbiosis.
924 * They both write to the same internal register. STAR allows to
925 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
927 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
928 wrmsrl(MSR_LSTAR
, system_call
);
929 wrmsrl(MSR_CSTAR
, ignore_sysret
);
931 #ifdef CONFIG_IA32_EMULATION
932 syscall32_cpu_init();
935 /* Flags to clear on syscall */
936 wrmsrl(MSR_SYSCALL_MASK
,
937 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
940 unsigned long kernel_eflags
;
943 * Copies of the original ist values from the tss are only accessed during
944 * debugging, no special alignment required.
946 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
950 /* Make sure %fs is initialized properly in idle threads */
951 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
953 memset(regs
, 0, sizeof(struct pt_regs
));
954 regs
->fs
= __KERNEL_PERCPU
;
960 * cpu_init() initializes state that is per-CPU. Some data is already
961 * initialized (naturally) in the bootstrap process, such as the GDT
962 * and IDT. We reload them nevertheless, this function acts as a
963 * 'CPU state barrier', nothing should get across.
964 * A lot of state is already set up in PDA init for 64 bit
967 void __cpuinit
cpu_init(void)
969 int cpu
= stack_smp_processor_id();
970 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
971 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
973 struct task_struct
*me
;
977 if (cpu
!= 0 && percpu_read(node_number
) == 0 &&
978 cpu_to_node(cpu
) != NUMA_NO_NODE
)
979 percpu_write(node_number
, cpu_to_node(cpu
));
984 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
))
985 panic("CPU#%d already initialized!\n", cpu
);
987 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
989 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
992 * Initialize the per-CPU GDT with the boot GDT,
993 * and set up the GDT descriptor:
999 load_idt((const struct desc_ptr
*)&idt_descr
);
1001 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1004 wrmsrl(MSR_FS_BASE
, 0);
1005 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1009 if (cpu
!= 0 && x2apic
)
1013 * set up and load the per-CPU TSS
1015 if (!orig_ist
->ist
[0]) {
1016 static const unsigned int sizes
[N_EXCEPTION_STACKS
] = {
1017 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1018 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1020 char *estacks
= per_cpu(exception_stacks
, cpu
);
1021 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1022 estacks
+= sizes
[v
];
1023 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1024 (unsigned long)estacks
;
1028 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1030 * <= is required because the CPU will access up to
1031 * 8 bits beyond the end of the IO permission bitmap.
1033 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1034 t
->io_bitmap
[i
] = ~0UL;
1036 atomic_inc(&init_mm
.mm_count
);
1037 me
->active_mm
= &init_mm
;
1040 enter_lazy_tlb(&init_mm
, me
);
1042 load_sp0(t
, ¤t
->thread
);
1043 set_tss_desc(cpu
, t
);
1045 load_LDT(&init_mm
.context
);
1049 * If the kgdb is connected no debug regs should be altered. This
1050 * is only applicable when KGDB and a KGDB I/O module are built
1051 * into the kernel and you are using early debugging with
1052 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1054 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
1055 arch_kgdb_ops
.correct_hw_break();
1059 * Clear all 6 debug registers:
1062 set_debugreg(0UL, 0);
1063 set_debugreg(0UL, 1);
1064 set_debugreg(0UL, 2);
1065 set_debugreg(0UL, 3);
1066 set_debugreg(0UL, 6);
1067 set_debugreg(0UL, 7);
1069 /* If the kgdb is connected no debug regs should be altered. */
1075 raw_local_save_flags(kernel_eflags
);
1083 void __cpuinit
cpu_init(void)
1085 int cpu
= smp_processor_id();
1086 struct task_struct
*curr
= current
;
1087 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1088 struct thread_struct
*thread
= &curr
->thread
;
1090 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
)) {
1091 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1092 for (;;) local_irq_enable();
1095 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1097 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1098 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1100 load_idt(&idt_descr
);
1101 switch_to_new_gdt();
1104 * Set up and load the per-CPU TSS and LDT
1106 atomic_inc(&init_mm
.mm_count
);
1107 curr
->active_mm
= &init_mm
;
1110 enter_lazy_tlb(&init_mm
, curr
);
1112 load_sp0(t
, thread
);
1113 set_tss_desc(cpu
, t
);
1115 load_LDT(&init_mm
.context
);
1117 #ifdef CONFIG_DOUBLEFAULT
1118 /* Set up doublefault TSS pointer in the GDT */
1119 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1123 asm volatile ("mov %0, %%gs" : : "r" (0));
1125 /* Clear all 6 debug registers: */
1134 * Force FPU initialization:
1137 current_thread_info()->status
= TS_XSAVE
;
1139 current_thread_info()->status
= 0;
1141 mxcsr_feature_mask_init();
1144 * Boot processor to setup the FP and extended state context info.
1146 if (smp_processor_id() == boot_cpu_id
)
1147 init_thread_xstate();