1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/pgtable.h>
26 #include <asm/cmdline.h>
27 #include <asm/stackprotector.h>
28 #include <asm/perf_event.h>
29 #include <asm/mmu_context.h>
30 #include <asm/doublefault.h>
31 #include <asm/archrandom.h>
32 #include <asm/hypervisor.h>
33 #include <asm/processor.h>
34 #include <asm/tlbflush.h>
35 #include <asm/debugreg.h>
36 #include <asm/sections.h>
37 #include <asm/vsyscall.h>
38 #include <linux/topology.h>
39 #include <linux/cpumask.h>
40 #include <linux/atomic.h>
41 #include <asm/proto.h>
42 #include <asm/setup.h>
45 #include <asm/fpu/internal.h>
47 #include <asm/hwcap2.h>
48 #include <linux/numa.h>
55 #include <asm/memtype.h>
56 #include <asm/microcode.h>
57 #include <asm/microcode_intel.h>
58 #include <asm/intel-family.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/uv/uv.h>
61 #include <asm/sigframe.h>
65 u32 elf_hwcap2 __read_mostly
;
67 /* all of these masks are initialized in setup_cpu_local_masks() */
68 cpumask_var_t cpu_initialized_mask
;
69 cpumask_var_t cpu_callout_mask
;
70 cpumask_var_t cpu_callin_mask
;
72 /* representing cpus for which sibling maps can be computed */
73 cpumask_var_t cpu_sibling_setup_mask
;
75 /* Number of siblings per CPU package */
76 int smp_num_siblings
= 1;
77 EXPORT_SYMBOL(smp_num_siblings
);
79 /* Last level cache ID of each logical CPU */
80 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
82 u16
get_llc_id(unsigned int cpu
)
84 return per_cpu(cpu_llc_id
, cpu
);
86 EXPORT_SYMBOL_GPL(get_llc_id
);
88 /* correctly size the local cpu masks */
89 void __init
setup_cpu_local_masks(void)
91 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
92 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
93 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
94 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
97 static void default_init(struct cpuinfo_x86
*c
)
100 cpu_detect_cache_sizes(c
);
102 /* Not much we can do here... */
103 /* Check if at least it has cpuid */
104 if (c
->cpuid_level
== -1) {
105 /* No cpuid. It must be an ancient CPU */
107 strcpy(c
->x86_model_id
, "486");
108 else if (c
->x86
== 3)
109 strcpy(c
->x86_model_id
, "386");
114 static const struct cpu_dev default_cpu
= {
115 .c_init
= default_init
,
116 .c_vendor
= "Unknown",
117 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
120 static const struct cpu_dev
*this_cpu
= &default_cpu
;
122 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
125 * We need valid kernel segments for data and code in long mode too
126 * IRET will check the segment types kkeil 2000/10/28
127 * Also sysret mandates a special GDT layout
129 * TLS descriptors are currently at a different place compared to i386.
130 * Hopefully nobody expects them at a fixed place (Wine?)
132 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
133 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
134 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
135 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
136 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
137 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
139 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
140 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
141 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
142 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
144 * Segments used for calling PnP BIOS have byte granularity.
145 * They code segments and data segments have fixed 64k limits,
146 * the transfer segment sizes are set at run time.
149 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
151 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
153 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
155 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
157 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
159 * The APM segments have byte granularity and their bases
160 * are set at run time. All have 64k limits.
163 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
165 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
167 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
169 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
170 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
173 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
176 static int __init
x86_nopcid_setup(char *s
)
178 /* nopcid doesn't accept parameters */
182 /* do not emit a message if the feature is not present */
183 if (!boot_cpu_has(X86_FEATURE_PCID
))
186 setup_clear_cpu_cap(X86_FEATURE_PCID
);
187 pr_info("nopcid: PCID feature disabled\n");
190 early_param("nopcid", x86_nopcid_setup
);
193 static int __init
x86_noinvpcid_setup(char *s
)
195 /* noinvpcid doesn't accept parameters */
199 /* do not emit a message if the feature is not present */
200 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
203 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
204 pr_info("noinvpcid: INVPCID feature disabled\n");
207 early_param("noinvpcid", x86_noinvpcid_setup
);
210 static int cachesize_override
= -1;
211 static int disable_x86_serial_nr
= 1;
213 static int __init
cachesize_setup(char *str
)
215 get_option(&str
, &cachesize_override
);
218 __setup("cachesize=", cachesize_setup
);
220 static int __init
x86_sep_setup(char *s
)
222 setup_clear_cpu_cap(X86_FEATURE_SEP
);
225 __setup("nosep", x86_sep_setup
);
227 /* Standard macro to see if a specific flag is changeable */
228 static inline int flag_is_changeable_p(u32 flag
)
233 * Cyrix and IDT cpus allow disabling of CPUID
234 * so the code below may return different results
235 * when it is executed before and after enabling
236 * the CPUID. Add "volatile" to not allow gcc to
237 * optimize the subsequent calls to this function.
239 asm volatile ("pushfl \n\t"
250 : "=&r" (f1
), "=&r" (f2
)
253 return ((f1
^f2
) & flag
) != 0;
256 /* Probe for the CPUID instruction */
257 int have_cpuid_p(void)
259 return flag_is_changeable_p(X86_EFLAGS_ID
);
262 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
264 unsigned long lo
, hi
;
266 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
269 /* Disable processor serial number: */
271 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
273 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
275 pr_notice("CPU serial number disabled.\n");
276 clear_cpu_cap(c
, X86_FEATURE_PN
);
278 /* Disabling the serial number may affect the cpuid level */
279 c
->cpuid_level
= cpuid_eax(0);
282 static int __init
x86_serial_nr_setup(char *s
)
284 disable_x86_serial_nr
= 0;
287 __setup("serialnumber", x86_serial_nr_setup
);
289 static inline int flag_is_changeable_p(u32 flag
)
293 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
298 static __init
int setup_disable_smep(char *arg
)
300 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
303 __setup("nosmep", setup_disable_smep
);
305 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
307 if (cpu_has(c
, X86_FEATURE_SMEP
))
308 cr4_set_bits(X86_CR4_SMEP
);
311 static __init
int setup_disable_smap(char *arg
)
313 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
316 __setup("nosmap", setup_disable_smap
);
318 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
320 unsigned long eflags
= native_save_fl();
322 /* This should have been cleared long ago */
323 BUG_ON(eflags
& X86_EFLAGS_AC
);
325 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
326 #ifdef CONFIG_X86_SMAP
327 cr4_set_bits(X86_CR4_SMAP
);
329 cr4_clear_bits(X86_CR4_SMAP
);
334 static __always_inline
void setup_umip(struct cpuinfo_x86
*c
)
336 /* Check the boot processor, plus build option for UMIP. */
337 if (!cpu_feature_enabled(X86_FEATURE_UMIP
))
340 /* Check the current processor's cpuid bits. */
341 if (!cpu_has(c
, X86_FEATURE_UMIP
))
344 cr4_set_bits(X86_CR4_UMIP
);
346 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
352 * Make sure UMIP is disabled in case it was enabled in a
353 * previous boot (e.g., via kexec).
355 cr4_clear_bits(X86_CR4_UMIP
);
358 /* These bits should not change their value after CPU init is finished. */
359 static const unsigned long cr4_pinned_mask
=
360 X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_UMIP
| X86_CR4_FSGSBASE
;
361 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning
);
362 static unsigned long cr4_pinned_bits __ro_after_init
;
364 void native_write_cr0(unsigned long val
)
366 unsigned long bits_missing
= 0;
369 asm volatile("mov %0,%%cr0": "+r" (val
) : : "memory");
371 if (static_branch_likely(&cr_pinning
)) {
372 if (unlikely((val
& X86_CR0_WP
) != X86_CR0_WP
)) {
373 bits_missing
= X86_CR0_WP
;
377 /* Warn after we've set the missing bits. */
378 WARN_ONCE(bits_missing
, "CR0 WP bit went missing!?\n");
381 EXPORT_SYMBOL(native_write_cr0
);
383 void native_write_cr4(unsigned long val
)
385 unsigned long bits_changed
= 0;
388 asm volatile("mov %0,%%cr4": "+r" (val
) : : "memory");
390 if (static_branch_likely(&cr_pinning
)) {
391 if (unlikely((val
& cr4_pinned_mask
) != cr4_pinned_bits
)) {
392 bits_changed
= (val
& cr4_pinned_mask
) ^ cr4_pinned_bits
;
393 val
= (val
& ~cr4_pinned_mask
) | cr4_pinned_bits
;
396 /* Warn after we've corrected the changed bits. */
397 WARN_ONCE(bits_changed
, "pinned CR4 bits changed: 0x%lx!?\n",
401 #if IS_MODULE(CONFIG_LKDTM)
402 EXPORT_SYMBOL_GPL(native_write_cr4
);
405 void cr4_update_irqsoff(unsigned long set
, unsigned long clear
)
407 unsigned long newval
, cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
409 lockdep_assert_irqs_disabled();
411 newval
= (cr4
& ~clear
) | set
;
413 this_cpu_write(cpu_tlbstate
.cr4
, newval
);
417 EXPORT_SYMBOL(cr4_update_irqsoff
);
419 /* Read the CR4 shadow. */
420 unsigned long cr4_read_shadow(void)
422 return this_cpu_read(cpu_tlbstate
.cr4
);
424 EXPORT_SYMBOL_GPL(cr4_read_shadow
);
428 unsigned long cr4
= __read_cr4();
430 if (boot_cpu_has(X86_FEATURE_PCID
))
431 cr4
|= X86_CR4_PCIDE
;
432 if (static_branch_likely(&cr_pinning
))
433 cr4
= (cr4
& ~cr4_pinned_mask
) | cr4_pinned_bits
;
437 /* Initialize cr4 shadow for this CPU. */
438 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
442 * Once CPU feature detection is finished (and boot params have been
443 * parsed), record any of the sensitive CR bits that are set, and
446 static void __init
setup_cr_pinning(void)
448 cr4_pinned_bits
= this_cpu_read(cpu_tlbstate
.cr4
) & cr4_pinned_mask
;
449 static_key_enable(&cr_pinning
.key
);
452 static __init
int x86_nofsgsbase_setup(char *arg
)
454 /* Require an exact match without trailing characters. */
458 /* Do not emit a message if the feature is not present. */
459 if (!boot_cpu_has(X86_FEATURE_FSGSBASE
))
462 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE
);
463 pr_info("FSGSBASE disabled via kernel command line\n");
466 __setup("nofsgsbase", x86_nofsgsbase_setup
);
469 * Protection Keys are not available in 32-bit mode.
471 static bool pku_disabled
;
473 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
475 if (c
== &boot_cpu_data
) {
476 if (pku_disabled
|| !cpu_feature_enabled(X86_FEATURE_PKU
))
479 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
480 * bit to be set. Enforce it.
482 setup_force_cpu_cap(X86_FEATURE_OSPKE
);
484 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE
)) {
488 cr4_set_bits(X86_CR4_PKE
);
489 /* Load the default PKRU value */
490 pkru_write_default();
493 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
494 static __init
int setup_disable_pku(char *arg
)
497 * Do not clear the X86_FEATURE_PKU bit. All of the
498 * runtime checks are against OSPKE so clearing the
501 * This way, we will see "pku" in cpuinfo, but not
502 * "ospke", which is exactly what we want. It shows
503 * that the CPU has PKU, but the OS has not enabled it.
504 * This happens to be exactly how a system would look
505 * if we disabled the config option.
507 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
511 __setup("nopku", setup_disable_pku
);
512 #endif /* CONFIG_X86_64 */
515 * Some CPU features depend on higher CPUID levels, which may not always
516 * be available due to CPUID level capping or broken virtualization
517 * software. Add those features to this table to auto-disable them.
519 struct cpuid_dependent_feature
{
524 static const struct cpuid_dependent_feature
525 cpuid_dependent_features
[] = {
526 { X86_FEATURE_MWAIT
, 0x00000005 },
527 { X86_FEATURE_DCA
, 0x00000009 },
528 { X86_FEATURE_XSAVE
, 0x0000000d },
532 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
534 const struct cpuid_dependent_feature
*df
;
536 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
538 if (!cpu_has(c
, df
->feature
))
541 * Note: cpuid_level is set to -1 if unavailable, but
542 * extended_extended_level is set to 0 if unavailable
543 * and the legitimate extended levels are all negative
544 * when signed; hence the weird messing around with
547 if (!((s32
)df
->level
< 0 ?
548 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
549 (s32
)df
->level
> (s32
)c
->cpuid_level
))
552 clear_cpu_cap(c
, df
->feature
);
556 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
557 x86_cap_flag(df
->feature
), df
->level
);
562 * Naming convention should be: <Name> [(<Codename>)]
563 * This table only is used unless init_<vendor>() below doesn't set it;
564 * in particular, if CPUID levels 0x80000002..4 are supported, this
568 /* Look up CPU names by table lookup. */
569 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
572 const struct legacy_cpu_model_info
*info
;
574 if (c
->x86_model
>= 16)
575 return NULL
; /* Range check */
580 info
= this_cpu
->legacy_models
;
582 while (info
->family
) {
583 if (info
->family
== c
->x86
)
584 return info
->model_names
[c
->x86_model
];
588 return NULL
; /* Not found */
591 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
592 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
593 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
595 void load_percpu_segment(int cpu
)
598 loadsegment(fs
, __KERNEL_PERCPU
);
600 __loadsegment_simple(gs
, 0);
601 wrmsrl(MSR_GS_BASE
, cpu_kernelmode_gs_base(cpu
));
606 /* The 32-bit entry code needs to find cpu_entry_area. */
607 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
610 /* Load the original GDT from the per-cpu structure */
611 void load_direct_gdt(int cpu
)
613 struct desc_ptr gdt_descr
;
615 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
616 gdt_descr
.size
= GDT_SIZE
- 1;
617 load_gdt(&gdt_descr
);
619 EXPORT_SYMBOL_GPL(load_direct_gdt
);
621 /* Load a fixmap remapping of the per-cpu GDT */
622 void load_fixmap_gdt(int cpu
)
624 struct desc_ptr gdt_descr
;
626 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
627 gdt_descr
.size
= GDT_SIZE
- 1;
628 load_gdt(&gdt_descr
);
630 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
633 * Current gdt points %fs at the "master" per-cpu area: after this,
634 * it's on the real one.
636 void switch_to_new_gdt(int cpu
)
638 /* Load the original GDT */
639 load_direct_gdt(cpu
);
640 /* Reload the per-cpu base */
641 load_percpu_segment(cpu
);
644 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
646 static void get_model_name(struct cpuinfo_x86
*c
)
651 if (c
->extended_cpuid_level
< 0x80000004)
654 v
= (unsigned int *)c
->x86_model_id
;
655 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
656 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
657 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
658 c
->x86_model_id
[48] = 0;
660 /* Trim whitespace */
661 p
= q
= s
= &c
->x86_model_id
[0];
667 /* Note the last non-whitespace index */
677 void detect_num_cpu_cores(struct cpuinfo_x86
*c
)
679 unsigned int eax
, ebx
, ecx
, edx
;
681 c
->x86_max_cores
= 1;
682 if (!IS_ENABLED(CONFIG_SMP
) || c
->cpuid_level
< 4)
685 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
687 c
->x86_max_cores
= (eax
>> 26) + 1;
690 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
692 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
694 n
= c
->extended_cpuid_level
;
696 if (n
>= 0x80000005) {
697 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
698 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
700 /* On K8 L1 TLB is inclusive, so don't count it */
705 if (n
< 0x80000006) /* Some chips just has a large L1. */
708 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
712 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
714 /* do processor-specific cache resizing */
715 if (this_cpu
->legacy_cache_size
)
716 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
718 /* Allow user to override all this if necessary. */
719 if (cachesize_override
!= -1)
720 l2size
= cachesize_override
;
723 return; /* Again, no L2 cache is possible */
726 c
->x86_cache_size
= l2size
;
729 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
730 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
731 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
732 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
733 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
734 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
735 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
737 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
739 if (this_cpu
->c_detect_tlb
)
740 this_cpu
->c_detect_tlb(c
);
742 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
743 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
744 tlb_lli_4m
[ENTRIES
]);
746 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
747 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
748 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
751 int detect_ht_early(struct cpuinfo_x86
*c
)
754 u32 eax
, ebx
, ecx
, edx
;
756 if (!cpu_has(c
, X86_FEATURE_HT
))
759 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
762 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
765 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
767 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
768 if (smp_num_siblings
== 1)
769 pr_info_once("CPU0: Hyper-Threading is disabled\n");
774 void detect_ht(struct cpuinfo_x86
*c
)
777 int index_msb
, core_bits
;
779 if (detect_ht_early(c
) < 0)
782 index_msb
= get_count_order(smp_num_siblings
);
783 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
785 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
787 index_msb
= get_count_order(smp_num_siblings
);
789 core_bits
= get_count_order(c
->x86_max_cores
);
791 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
792 ((1 << core_bits
) - 1);
796 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
798 char *v
= c
->x86_vendor_id
;
801 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
805 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
806 (cpu_devs
[i
]->c_ident
[1] &&
807 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
809 this_cpu
= cpu_devs
[i
];
810 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
815 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
816 "CPU: Your system may be unstable.\n", v
);
818 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
819 this_cpu
= &default_cpu
;
822 void cpu_detect(struct cpuinfo_x86
*c
)
824 /* Get vendor name */
825 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
826 (unsigned int *)&c
->x86_vendor_id
[0],
827 (unsigned int *)&c
->x86_vendor_id
[8],
828 (unsigned int *)&c
->x86_vendor_id
[4]);
831 /* Intel-defined flags: level 0x00000001 */
832 if (c
->cpuid_level
>= 0x00000001) {
833 u32 junk
, tfms
, cap0
, misc
;
835 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
836 c
->x86
= x86_family(tfms
);
837 c
->x86_model
= x86_model(tfms
);
838 c
->x86_stepping
= x86_stepping(tfms
);
840 if (cap0
& (1<<19)) {
841 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
842 c
->x86_cache_alignment
= c
->x86_clflush_size
;
847 static void apply_forced_caps(struct cpuinfo_x86
*c
)
851 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
852 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
853 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
857 static void init_speculation_control(struct cpuinfo_x86
*c
)
860 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
861 * and they also have a different bit for STIBP support. Also,
862 * a hypervisor might have set the individual AMD bits even on
863 * Intel CPUs, for finer-grained selection of what's available.
865 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
866 set_cpu_cap(c
, X86_FEATURE_IBRS
);
867 set_cpu_cap(c
, X86_FEATURE_IBPB
);
868 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
871 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
872 set_cpu_cap(c
, X86_FEATURE_STIBP
);
874 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
875 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
876 set_cpu_cap(c
, X86_FEATURE_SSBD
);
878 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
879 set_cpu_cap(c
, X86_FEATURE_IBRS
);
880 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
883 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
884 set_cpu_cap(c
, X86_FEATURE_IBPB
);
886 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
887 set_cpu_cap(c
, X86_FEATURE_STIBP
);
888 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
891 if (cpu_has(c
, X86_FEATURE_AMD_SSBD
)) {
892 set_cpu_cap(c
, X86_FEATURE_SSBD
);
893 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
894 clear_cpu_cap(c
, X86_FEATURE_VIRT_SSBD
);
898 void get_cpu_cap(struct cpuinfo_x86
*c
)
900 u32 eax
, ebx
, ecx
, edx
;
902 /* Intel-defined flags: level 0x00000001 */
903 if (c
->cpuid_level
>= 0x00000001) {
904 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
906 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
907 c
->x86_capability
[CPUID_1_EDX
] = edx
;
910 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
911 if (c
->cpuid_level
>= 0x00000006)
912 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
914 /* Additional Intel-defined flags: level 0x00000007 */
915 if (c
->cpuid_level
>= 0x00000007) {
916 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
917 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
918 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
919 c
->x86_capability
[CPUID_7_EDX
] = edx
;
921 /* Check valid sub-leaf index before accessing it */
923 cpuid_count(0x00000007, 1, &eax
, &ebx
, &ecx
, &edx
);
924 c
->x86_capability
[CPUID_7_1_EAX
] = eax
;
928 /* Extended state features: level 0x0000000d */
929 if (c
->cpuid_level
>= 0x0000000d) {
930 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
932 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
935 /* AMD-defined flags: level 0x80000001 */
936 eax
= cpuid_eax(0x80000000);
937 c
->extended_cpuid_level
= eax
;
939 if ((eax
& 0xffff0000) == 0x80000000) {
940 if (eax
>= 0x80000001) {
941 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
943 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
944 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
948 if (c
->extended_cpuid_level
>= 0x80000007) {
949 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
951 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
955 if (c
->extended_cpuid_level
>= 0x80000008) {
956 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
957 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
960 if (c
->extended_cpuid_level
>= 0x8000000a)
961 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
963 if (c
->extended_cpuid_level
>= 0x8000001f)
964 c
->x86_capability
[CPUID_8000_001F_EAX
] = cpuid_eax(0x8000001f);
966 init_scattered_cpuid_features(c
);
967 init_speculation_control(c
);
970 * Clear/Set all flags overridden by options, after probe.
971 * This needs to happen each time we re-probe, which may happen
972 * several times during CPU initialization.
974 apply_forced_caps(c
);
977 void get_cpu_address_sizes(struct cpuinfo_x86
*c
)
979 u32 eax
, ebx
, ecx
, edx
;
981 if (c
->extended_cpuid_level
>= 0x80000008) {
982 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
984 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
985 c
->x86_phys_bits
= eax
& 0xff;
988 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
989 c
->x86_phys_bits
= 36;
991 c
->x86_cache_bits
= c
->x86_phys_bits
;
994 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
1000 * First of all, decide if this is a 486 or higher
1001 * It's a 486 if we can modify the AC flag
1003 if (flag_is_changeable_p(X86_EFLAGS_AC
))
1008 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
1009 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
1010 c
->x86_vendor_id
[0] = 0;
1011 cpu_devs
[i
]->c_identify(c
);
1012 if (c
->x86_vendor_id
[0]) {
1020 #define NO_SPECULATION BIT(0)
1021 #define NO_MELTDOWN BIT(1)
1022 #define NO_SSB BIT(2)
1023 #define NO_L1TF BIT(3)
1024 #define NO_MDS BIT(4)
1025 #define MSBDS_ONLY BIT(5)
1026 #define NO_SWAPGS BIT(6)
1027 #define NO_ITLB_MULTIHIT BIT(7)
1028 #define NO_SPECTRE_V2 BIT(8)
1030 #define VULNWL(vendor, family, model, whitelist) \
1031 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1033 #define VULNWL_INTEL(model, whitelist) \
1034 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1036 #define VULNWL_AMD(family, whitelist) \
1037 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1039 #define VULNWL_HYGON(family, whitelist) \
1040 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1042 static const __initconst
struct x86_cpu_id cpu_vuln_whitelist
[] = {
1043 VULNWL(ANY
, 4, X86_MODEL_ANY
, NO_SPECULATION
),
1044 VULNWL(CENTAUR
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1045 VULNWL(INTEL
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1046 VULNWL(NSC
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1048 /* Intel Family 6 */
1049 VULNWL_INTEL(ATOM_SALTWELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1050 VULNWL_INTEL(ATOM_SALTWELL_TABLET
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1051 VULNWL_INTEL(ATOM_SALTWELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1052 VULNWL_INTEL(ATOM_BONNELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1053 VULNWL_INTEL(ATOM_BONNELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1055 VULNWL_INTEL(ATOM_SILVERMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1056 VULNWL_INTEL(ATOM_SILVERMONT_D
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1057 VULNWL_INTEL(ATOM_SILVERMONT_MID
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1058 VULNWL_INTEL(ATOM_AIRMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1059 VULNWL_INTEL(XEON_PHI_KNL
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1060 VULNWL_INTEL(XEON_PHI_KNM
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1062 VULNWL_INTEL(CORE_YONAH
, NO_SSB
),
1064 VULNWL_INTEL(ATOM_AIRMONT_MID
, NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1065 VULNWL_INTEL(ATOM_AIRMONT_NP
, NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1067 VULNWL_INTEL(ATOM_GOLDMONT
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1068 VULNWL_INTEL(ATOM_GOLDMONT_D
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1069 VULNWL_INTEL(ATOM_GOLDMONT_PLUS
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1072 * Technically, swapgs isn't serializing on AMD (despite it previously
1073 * being documented as such in the APM). But according to AMD, %gs is
1074 * updated non-speculatively, and the issuing of %gs-relative memory
1075 * operands will be blocked until the %gs update completes, which is
1076 * good enough for our purposes.
1079 VULNWL_INTEL(ATOM_TREMONT_D
, NO_ITLB_MULTIHIT
),
1081 /* AMD Family 0xf - 0x12 */
1082 VULNWL_AMD(0x0f, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1083 VULNWL_AMD(0x10, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1084 VULNWL_AMD(0x11, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1085 VULNWL_AMD(0x12, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1087 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1088 VULNWL_AMD(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1089 VULNWL_HYGON(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1091 /* Zhaoxin Family 7 */
1092 VULNWL(CENTAUR
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
),
1093 VULNWL(ZHAOXIN
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
),
1097 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1098 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1099 INTEL_FAM6_##model, steppings, \
1100 X86_FEATURE_ANY, issues)
1102 #define SRBDS BIT(0)
1104 static const struct x86_cpu_id cpu_vuln_blacklist
[] __initconst
= {
1105 VULNBL_INTEL_STEPPINGS(IVYBRIDGE
, X86_STEPPING_ANY
, SRBDS
),
1106 VULNBL_INTEL_STEPPINGS(HASWELL
, X86_STEPPING_ANY
, SRBDS
),
1107 VULNBL_INTEL_STEPPINGS(HASWELL_L
, X86_STEPPING_ANY
, SRBDS
),
1108 VULNBL_INTEL_STEPPINGS(HASWELL_G
, X86_STEPPING_ANY
, SRBDS
),
1109 VULNBL_INTEL_STEPPINGS(BROADWELL_G
, X86_STEPPING_ANY
, SRBDS
),
1110 VULNBL_INTEL_STEPPINGS(BROADWELL
, X86_STEPPING_ANY
, SRBDS
),
1111 VULNBL_INTEL_STEPPINGS(SKYLAKE_L
, X86_STEPPING_ANY
, SRBDS
),
1112 VULNBL_INTEL_STEPPINGS(SKYLAKE
, X86_STEPPING_ANY
, SRBDS
),
1113 VULNBL_INTEL_STEPPINGS(KABYLAKE_L
, X86_STEPPINGS(0x0, 0xC), SRBDS
),
1114 VULNBL_INTEL_STEPPINGS(KABYLAKE
, X86_STEPPINGS(0x0, 0xD), SRBDS
),
1118 static bool __init
cpu_matches(const struct x86_cpu_id
*table
, unsigned long which
)
1120 const struct x86_cpu_id
*m
= x86_match_cpu(table
);
1122 return m
&& !!(m
->driver_data
& which
);
1125 u64
x86_read_arch_cap_msr(void)
1129 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
1130 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
1135 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
1137 u64 ia32_cap
= x86_read_arch_cap_msr();
1139 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1140 if (!cpu_matches(cpu_vuln_whitelist
, NO_ITLB_MULTIHIT
) &&
1141 !(ia32_cap
& ARCH_CAP_PSCHANGE_MC_NO
))
1142 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT
);
1144 if (cpu_matches(cpu_vuln_whitelist
, NO_SPECULATION
))
1147 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
1149 if (!cpu_matches(cpu_vuln_whitelist
, NO_SPECTRE_V2
))
1150 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
1152 if (!cpu_matches(cpu_vuln_whitelist
, NO_SSB
) &&
1153 !(ia32_cap
& ARCH_CAP_SSB_NO
) &&
1154 !cpu_has(c
, X86_FEATURE_AMD_SSB_NO
))
1155 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
1157 if (ia32_cap
& ARCH_CAP_IBRS_ALL
)
1158 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED
);
1160 if (!cpu_matches(cpu_vuln_whitelist
, NO_MDS
) &&
1161 !(ia32_cap
& ARCH_CAP_MDS_NO
)) {
1162 setup_force_cpu_bug(X86_BUG_MDS
);
1163 if (cpu_matches(cpu_vuln_whitelist
, MSBDS_ONLY
))
1164 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY
);
1167 if (!cpu_matches(cpu_vuln_whitelist
, NO_SWAPGS
))
1168 setup_force_cpu_bug(X86_BUG_SWAPGS
);
1171 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1172 * - TSX is supported or
1173 * - TSX_CTRL is present
1175 * TSX_CTRL check is needed for cases when TSX could be disabled before
1176 * the kernel boot e.g. kexec.
1177 * TSX_CTRL check alone is not sufficient for cases when the microcode
1178 * update is not present or running as guest that don't get TSX_CTRL.
1180 if (!(ia32_cap
& ARCH_CAP_TAA_NO
) &&
1181 (cpu_has(c
, X86_FEATURE_RTM
) ||
1182 (ia32_cap
& ARCH_CAP_TSX_CTRL_MSR
)))
1183 setup_force_cpu_bug(X86_BUG_TAA
);
1186 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1187 * in the vulnerability blacklist.
1189 if ((cpu_has(c
, X86_FEATURE_RDRAND
) ||
1190 cpu_has(c
, X86_FEATURE_RDSEED
)) &&
1191 cpu_matches(cpu_vuln_blacklist
, SRBDS
))
1192 setup_force_cpu_bug(X86_BUG_SRBDS
);
1194 if (cpu_matches(cpu_vuln_whitelist
, NO_MELTDOWN
))
1197 /* Rogue Data Cache Load? No! */
1198 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
1201 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
1203 if (cpu_matches(cpu_vuln_whitelist
, NO_L1TF
))
1206 setup_force_cpu_bug(X86_BUG_L1TF
);
1210 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1211 * unfortunately, that's not true in practice because of early VIA
1212 * chips and (more importantly) broken virtualizers that are not easy
1213 * to detect. In the latter case it doesn't even *fail* reliably, so
1214 * probing for it doesn't even work. Disable it completely on 32-bit
1215 * unless we can find a reliable way to detect all the broken cases.
1216 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1218 static void detect_nopl(void)
1220 #ifdef CONFIG_X86_32
1221 setup_clear_cpu_cap(X86_FEATURE_NOPL
);
1223 setup_force_cpu_cap(X86_FEATURE_NOPL
);
1228 * We parse cpu parameters early because fpu__init_system() is executed
1229 * before parse_early_param().
1231 static void __init
cpu_parse_early_param(void)
1235 int arglen
, res
, bit
;
1237 #ifdef CONFIG_X86_32
1238 if (cmdline_find_option_bool(boot_command_line
, "no387"))
1239 #ifdef CONFIG_MATH_EMULATION
1240 setup_clear_cpu_cap(X86_FEATURE_FPU
);
1242 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1245 if (cmdline_find_option_bool(boot_command_line
, "nofxsr"))
1246 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
1249 if (cmdline_find_option_bool(boot_command_line
, "noxsave"))
1250 setup_clear_cpu_cap(X86_FEATURE_XSAVE
);
1252 if (cmdline_find_option_bool(boot_command_line
, "noxsaveopt"))
1253 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT
);
1255 if (cmdline_find_option_bool(boot_command_line
, "noxsaves"))
1256 setup_clear_cpu_cap(X86_FEATURE_XSAVES
);
1258 arglen
= cmdline_find_option(boot_command_line
, "clearcpuid", arg
, sizeof(arg
));
1262 pr_info("Clearing CPUID bits:");
1264 res
= get_option(&argptr
, &bit
);
1265 if (res
== 0 || res
== 3)
1268 /* If the argument was too long, the last bit may be cut off */
1269 if (res
== 1 && arglen
>= sizeof(arg
))
1272 if (bit
>= 0 && bit
< NCAPINTS
* 32) {
1273 pr_cont(" " X86_CAP_FMT
, x86_cap_flag(bit
));
1274 setup_clear_cpu_cap(bit
);
1281 * Do minimum CPU detection early.
1282 * Fields really needed: vendor, cpuid_level, family, model, mask,
1284 * The others are not touched to avoid unwanted side effects.
1286 * WARNING: this function is only called on the boot CPU. Don't add code
1287 * here that is supposed to run on all CPUs.
1289 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
1291 #ifdef CONFIG_X86_64
1292 c
->x86_clflush_size
= 64;
1293 c
->x86_phys_bits
= 36;
1294 c
->x86_virt_bits
= 48;
1296 c
->x86_clflush_size
= 32;
1297 c
->x86_phys_bits
= 32;
1298 c
->x86_virt_bits
= 32;
1300 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1302 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1303 c
->extended_cpuid_level
= 0;
1305 if (!have_cpuid_p())
1306 identify_cpu_without_cpuid(c
);
1308 /* cyrix could have cpuid enabled via c_identify()*/
1309 if (have_cpuid_p()) {
1313 get_cpu_address_sizes(c
);
1314 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1315 cpu_parse_early_param();
1317 if (this_cpu
->c_early_init
)
1318 this_cpu
->c_early_init(c
);
1321 filter_cpuid_features(c
, false);
1323 if (this_cpu
->c_bsp_init
)
1324 this_cpu
->c_bsp_init(c
);
1326 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1329 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1331 cpu_set_bug_bits(c
);
1335 fpu__init_system(c
);
1337 init_sigframe_size();
1339 #ifdef CONFIG_X86_32
1341 * Regardless of whether PCID is enumerated, the SDM says
1342 * that it can't be enabled in 32-bit mode.
1344 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1348 * Later in the boot process pgtable_l5_enabled() relies on
1349 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1350 * enabled by this point we need to clear the feature bit to avoid
1351 * false-positives at the later stage.
1353 * pgtable_l5_enabled() can be false here for several reasons:
1354 * - 5-level paging is disabled compile-time;
1355 * - it's 32-bit kernel;
1356 * - machine doesn't support 5-level paging;
1357 * - user specified 'no5lvl' in kernel command line.
1359 if (!pgtable_l5_enabled())
1360 setup_clear_cpu_cap(X86_FEATURE_LA57
);
1365 void __init
early_cpu_init(void)
1367 const struct cpu_dev
*const *cdev
;
1370 #ifdef CONFIG_PROCESSOR_SELECT
1371 pr_info("KERNEL supported cpus:\n");
1374 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1375 const struct cpu_dev
*cpudev
= *cdev
;
1377 if (count
>= X86_VENDOR_NUM
)
1379 cpu_devs
[count
] = cpudev
;
1382 #ifdef CONFIG_PROCESSOR_SELECT
1386 for (j
= 0; j
< 2; j
++) {
1387 if (!cpudev
->c_ident
[j
])
1389 pr_info(" %s %s\n", cpudev
->c_vendor
,
1390 cpudev
->c_ident
[j
]);
1395 early_identify_cpu(&boot_cpu_data
);
1398 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
1400 #ifdef CONFIG_X86_64
1402 * Empirically, writing zero to a segment selector on AMD does
1403 * not clear the base, whereas writing zero to a segment
1404 * selector on Intel does clear the base. Intel's behavior
1405 * allows slightly faster context switches in the common case
1406 * where GS is unused by the prev and next threads.
1408 * Since neither vendor documents this anywhere that I can see,
1409 * detect it directly instead of hard-coding the choice by
1412 * I've designated AMD's behavior as the "bug" because it's
1413 * counterintuitive and less friendly.
1416 unsigned long old_base
, tmp
;
1417 rdmsrl(MSR_FS_BASE
, old_base
);
1418 wrmsrl(MSR_FS_BASE
, 1);
1420 rdmsrl(MSR_FS_BASE
, tmp
);
1422 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1423 wrmsrl(MSR_FS_BASE
, old_base
);
1427 static void generic_identify(struct cpuinfo_x86
*c
)
1429 c
->extended_cpuid_level
= 0;
1431 if (!have_cpuid_p())
1432 identify_cpu_without_cpuid(c
);
1434 /* cyrix could have cpuid enabled via c_identify()*/
1435 if (!have_cpuid_p())
1444 get_cpu_address_sizes(c
);
1446 if (c
->cpuid_level
>= 0x00000001) {
1447 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1448 #ifdef CONFIG_X86_32
1450 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1452 c
->apicid
= c
->initial_apicid
;
1455 c
->phys_proc_id
= c
->initial_apicid
;
1458 get_model_name(c
); /* Default name */
1460 detect_null_seg_behavior(c
);
1463 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1464 * systems that run Linux at CPL > 0 may or may not have the
1465 * issue, but, even if they have the issue, there's absolutely
1466 * nothing we can do about it because we can't use the real IRET
1469 * NB: For the time being, only 32-bit kernels support
1470 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1471 * whether to apply espfix using paravirt hooks. If any
1472 * non-paravirt system ever shows up that does *not* have the
1473 * ESPFIX issue, we can change this.
1475 #ifdef CONFIG_X86_32
1476 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1481 * Validate that ACPI/mptables have the same information about the
1482 * effective APIC id and update the package map.
1484 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1487 unsigned int apicid
, cpu
= smp_processor_id();
1489 apicid
= apic
->cpu_present_to_apicid(cpu
);
1491 if (apicid
!= c
->apicid
) {
1492 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1493 cpu
, apicid
, c
->initial_apicid
);
1495 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1496 BUG_ON(topology_update_die_map(c
->cpu_die_id
, cpu
));
1498 c
->logical_proc_id
= 0;
1503 * This does the hard work of actually picking apart the CPU stuff...
1505 static void identify_cpu(struct cpuinfo_x86
*c
)
1509 c
->loops_per_jiffy
= loops_per_jiffy
;
1510 c
->x86_cache_size
= 0;
1511 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1512 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1513 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1514 c
->x86_model_id
[0] = '\0'; /* Unset */
1515 c
->x86_max_cores
= 1;
1516 c
->x86_coreid_bits
= 0;
1518 #ifdef CONFIG_X86_64
1519 c
->x86_clflush_size
= 64;
1520 c
->x86_phys_bits
= 36;
1521 c
->x86_virt_bits
= 48;
1523 c
->cpuid_level
= -1; /* CPUID not detected */
1524 c
->x86_clflush_size
= 32;
1525 c
->x86_phys_bits
= 32;
1526 c
->x86_virt_bits
= 32;
1528 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1529 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1530 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1531 memset(&c
->vmx_capability
, 0, sizeof(c
->vmx_capability
));
1534 generic_identify(c
);
1536 if (this_cpu
->c_identify
)
1537 this_cpu
->c_identify(c
);
1539 /* Clear/Set all flags overridden by options, after probe */
1540 apply_forced_caps(c
);
1542 #ifdef CONFIG_X86_64
1543 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1547 * Vendor-specific initialization. In this section we
1548 * canonicalize the feature flags, meaning if there are
1549 * features a certain CPU supports which CPUID doesn't
1550 * tell us, CPUID claiming incorrect flags, or other bugs,
1551 * we handle them here.
1553 * At the end of this section, c->x86_capability better
1554 * indicate the features this CPU genuinely supports!
1556 if (this_cpu
->c_init
)
1557 this_cpu
->c_init(c
);
1559 /* Disable the PN if appropriate */
1560 squash_the_stupid_serial_number(c
);
1562 /* Set up SMEP/SMAP/UMIP */
1567 /* Enable FSGSBASE instructions if available. */
1568 if (cpu_has(c
, X86_FEATURE_FSGSBASE
)) {
1569 cr4_set_bits(X86_CR4_FSGSBASE
);
1570 elf_hwcap2
|= HWCAP2_FSGSBASE
;
1574 * The vendor-specific functions might have changed features.
1575 * Now we do "generic changes."
1578 /* Filter out anything that depends on CPUID levels we don't have */
1579 filter_cpuid_features(c
, true);
1581 /* If the model name is still unset, do table lookup. */
1582 if (!c
->x86_model_id
[0]) {
1584 p
= table_lookup_model(c
);
1586 strcpy(c
->x86_model_id
, p
);
1588 /* Last resort... */
1589 sprintf(c
->x86_model_id
, "%02x/%02x",
1590 c
->x86
, c
->x86_model
);
1593 #ifdef CONFIG_X86_64
1601 * Clear/Set all flags overridden by options, need do it
1602 * before following smp all cpus cap AND.
1604 apply_forced_caps(c
);
1607 * On SMP, boot_cpu_data holds the common feature set between
1608 * all CPUs; so make sure that we indicate which features are
1609 * common between the CPUs. The first time this routine gets
1610 * executed, c == &boot_cpu_data.
1612 if (c
!= &boot_cpu_data
) {
1613 /* AND the already accumulated flags with these */
1614 for (i
= 0; i
< NCAPINTS
; i
++)
1615 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1617 /* OR, i.e. replicate the bug flags */
1618 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1619 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1622 /* Init Machine Check Exception if available. */
1625 select_idle_routine(c
);
1628 numa_add_cpu(smp_processor_id());
1633 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1634 * on 32-bit kernels:
1636 #ifdef CONFIG_X86_32
1637 void enable_sep_cpu(void)
1639 struct tss_struct
*tss
;
1642 if (!boot_cpu_has(X86_FEATURE_SEP
))
1646 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1649 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1650 * see the big comment in struct x86_hw_tss's definition.
1653 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1654 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1655 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1656 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1662 void __init
identify_boot_cpu(void)
1664 identify_cpu(&boot_cpu_data
);
1665 #ifdef CONFIG_X86_32
1669 cpu_detect_tlb(&boot_cpu_data
);
1675 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1677 BUG_ON(c
== &boot_cpu_data
);
1679 #ifdef CONFIG_X86_32
1683 validate_apic_and_package_id(c
);
1684 x86_spec_ctrl_setup_ap();
1688 static __init
int setup_noclflush(char *arg
)
1690 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1691 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1694 __setup("noclflush", setup_noclflush
);
1696 void print_cpu_info(struct cpuinfo_x86
*c
)
1698 const char *vendor
= NULL
;
1700 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1701 vendor
= this_cpu
->c_vendor
;
1703 if (c
->cpuid_level
>= 0)
1704 vendor
= c
->x86_vendor_id
;
1707 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1708 pr_cont("%s ", vendor
);
1710 if (c
->x86_model_id
[0])
1711 pr_cont("%s", c
->x86_model_id
);
1713 pr_cont("%d86", c
->x86
);
1715 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1717 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
1718 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
1724 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
1725 * function prevents it from becoming an environment variable for init.
1727 static __init
int setup_clearcpuid(char *arg
)
1731 __setup("clearcpuid=", setup_clearcpuid
);
1733 #ifdef CONFIG_X86_64
1734 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data
,
1735 fixed_percpu_data
) __aligned(PAGE_SIZE
) __visible
;
1736 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data
);
1739 * The following percpu variables are hot. Align current_task to
1740 * cacheline size such that they fall in the same cacheline.
1742 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1744 EXPORT_PER_CPU_SYMBOL(current_task
);
1746 DEFINE_PER_CPU(void *, hardirq_stack_ptr
);
1747 DEFINE_PER_CPU(bool, hardirq_stack_inuse
);
1749 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1750 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1752 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) = TOP_OF_INIT_STACK
;
1754 /* May not be marked __init: used by software suspend */
1755 void syscall_init(void)
1757 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1758 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1760 #ifdef CONFIG_IA32_EMULATION
1761 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1763 * This only works on Intel CPUs.
1764 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1765 * This does not cause SYSENTER to jump to the wrong location, because
1766 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1768 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1769 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
,
1770 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1771 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1773 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1774 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1775 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1776 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1780 * Flags to clear on syscall; clear as much as possible
1781 * to minimize user space-kernel interference.
1783 wrmsrl(MSR_SYSCALL_MASK
,
1784 X86_EFLAGS_CF
|X86_EFLAGS_PF
|X86_EFLAGS_AF
|
1785 X86_EFLAGS_ZF
|X86_EFLAGS_SF
|X86_EFLAGS_TF
|
1786 X86_EFLAGS_IF
|X86_EFLAGS_DF
|X86_EFLAGS_OF
|
1787 X86_EFLAGS_IOPL
|X86_EFLAGS_NT
|X86_EFLAGS_RF
|
1788 X86_EFLAGS_AC
|X86_EFLAGS_ID
);
1791 #else /* CONFIG_X86_64 */
1793 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1794 EXPORT_PER_CPU_SYMBOL(current_task
);
1795 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1796 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1799 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1800 * the top of the kernel stack. Use an extra percpu variable to track the
1801 * top of the kernel stack directly.
1803 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1804 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1805 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1807 #ifdef CONFIG_STACKPROTECTOR
1808 DEFINE_PER_CPU(unsigned long, __stack_chk_guard
);
1809 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard
);
1812 #endif /* CONFIG_X86_64 */
1815 * Clear all 6 debug registers:
1817 static void clear_all_debug_regs(void)
1821 for (i
= 0; i
< 8; i
++) {
1822 /* Ignore db4, db5 */
1823 if ((i
== 4) || (i
== 5))
1832 * Restore debug regs if using kgdbwait and you have a kernel debugger
1833 * connection established.
1835 static void dbg_restore_debug_regs(void)
1837 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1838 arch_kgdb_ops
.correct_hw_break();
1840 #else /* ! CONFIG_KGDB */
1841 #define dbg_restore_debug_regs()
1842 #endif /* ! CONFIG_KGDB */
1844 static void wait_for_master_cpu(int cpu
)
1848 * wait for ACK from master CPU before continuing
1849 * with AP initialization
1851 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1852 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1857 #ifdef CONFIG_X86_64
1858 static inline void setup_getcpu(int cpu
)
1860 unsigned long cpudata
= vdso_encode_cpunode(cpu
, early_cpu_to_node(cpu
));
1861 struct desc_struct d
= { };
1863 if (boot_cpu_has(X86_FEATURE_RDTSCP
) || boot_cpu_has(X86_FEATURE_RDPID
))
1864 wrmsr(MSR_TSC_AUX
, cpudata
, 0);
1866 /* Store CPU and node number in limit. */
1868 d
.limit1
= cpudata
>> 16;
1870 d
.type
= 5; /* RO data, expand down, accessed */
1871 d
.dpl
= 3; /* Visible to user code */
1872 d
.s
= 1; /* Not a system segment */
1873 d
.p
= 1; /* Present */
1874 d
.d
= 1; /* 32-bit */
1876 write_gdt_entry(get_cpu_gdt_rw(cpu
), GDT_ENTRY_CPUNODE
, &d
, DESCTYPE_S
);
1879 static inline void ucode_cpu_init(int cpu
)
1885 static inline void tss_setup_ist(struct tss_struct
*tss
)
1887 /* Set up the per-CPU TSS IST stacks */
1888 tss
->x86_tss
.ist
[IST_INDEX_DF
] = __this_cpu_ist_top_va(DF
);
1889 tss
->x86_tss
.ist
[IST_INDEX_NMI
] = __this_cpu_ist_top_va(NMI
);
1890 tss
->x86_tss
.ist
[IST_INDEX_DB
] = __this_cpu_ist_top_va(DB
);
1891 tss
->x86_tss
.ist
[IST_INDEX_MCE
] = __this_cpu_ist_top_va(MCE
);
1892 /* Only mapped when SEV-ES is active */
1893 tss
->x86_tss
.ist
[IST_INDEX_VC
] = __this_cpu_ist_top_va(VC
);
1896 #else /* CONFIG_X86_64 */
1898 static inline void setup_getcpu(int cpu
) { }
1900 static inline void ucode_cpu_init(int cpu
)
1902 show_ucode_info_early();
1905 static inline void tss_setup_ist(struct tss_struct
*tss
) { }
1907 #endif /* !CONFIG_X86_64 */
1909 static inline void tss_setup_io_bitmap(struct tss_struct
*tss
)
1911 tss
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET_INVALID
;
1913 #ifdef CONFIG_X86_IOPL_IOPERM
1914 tss
->io_bitmap
.prev_max
= 0;
1915 tss
->io_bitmap
.prev_sequence
= 0;
1916 memset(tss
->io_bitmap
.bitmap
, 0xff, sizeof(tss
->io_bitmap
.bitmap
));
1918 * Invalidate the extra array entry past the end of the all
1919 * permission bitmap as required by the hardware.
1921 tss
->io_bitmap
.mapall
[IO_BITMAP_LONGS
] = ~0UL;
1926 * Setup everything needed to handle exceptions from the IDT, including the IST
1927 * exceptions which use paranoid_entry().
1929 void cpu_init_exception_handling(void)
1931 struct tss_struct
*tss
= this_cpu_ptr(&cpu_tss_rw
);
1932 int cpu
= raw_smp_processor_id();
1934 /* paranoid_entry() gets the CPU number from the GDT */
1937 /* IST vectors need TSS to be set up. */
1939 tss_setup_io_bitmap(tss
);
1940 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1944 /* Finally load the IDT */
1949 * cpu_init() initializes state that is per-CPU. Some data is already
1950 * initialized (naturally) in the bootstrap process, such as the GDT. We
1951 * reload it nevertheless, this function acts as a 'CPU state barrier',
1952 * nothing should get across.
1956 struct task_struct
*cur
= current
;
1957 int cpu
= raw_smp_processor_id();
1959 wait_for_master_cpu(cpu
);
1961 ucode_cpu_init(cpu
);
1964 if (this_cpu_read(numa_node
) == 0 &&
1965 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1966 set_numa_node(early_cpu_to_node(cpu
));
1968 pr_debug("Initializing CPU#%d\n", cpu
);
1970 if (IS_ENABLED(CONFIG_X86_64
) || cpu_feature_enabled(X86_FEATURE_VME
) ||
1971 boot_cpu_has(X86_FEATURE_TSC
) || boot_cpu_has(X86_FEATURE_DE
))
1972 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1975 * Initialize the per-CPU GDT with the boot GDT,
1976 * and set up the GDT descriptor:
1978 switch_to_new_gdt(cpu
);
1980 if (IS_ENABLED(CONFIG_X86_64
)) {
1982 memset(cur
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1985 wrmsrl(MSR_FS_BASE
, 0);
1986 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1993 cur
->active_mm
= &init_mm
;
1995 initialize_tlbstate_and_flush();
1996 enter_lazy_tlb(&init_mm
, cur
);
1999 * sp0 points to the entry trampoline stack regardless of what task
2002 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
2004 load_mm_ldt(&init_mm
);
2006 clear_all_debug_regs();
2007 dbg_restore_debug_regs();
2009 doublefault_init_cpu_tss();
2016 load_fixmap_gdt(cpu
);
2020 void cpu_init_secondary(void)
2023 * Relies on the BP having set-up the IDT tables, which are loaded
2024 * on this CPU in cpu_init_exception_handling().
2026 cpu_init_exception_handling();
2032 * The microcode loader calls this upon late microcode load to recheck features,
2033 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2036 void microcode_check(void)
2038 struct cpuinfo_x86 info
;
2040 perf_check_microcode();
2042 /* Reload CPUID max function as it might've changed. */
2043 info
.cpuid_level
= cpuid_eax(0);
2046 * Copy all capability leafs to pick up the synthetic ones so that
2047 * memcmp() below doesn't fail on that. The ones coming from CPUID will
2048 * get overwritten in get_cpu_cap().
2050 memcpy(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
));
2054 if (!memcmp(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
)))
2057 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2058 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2062 * Invoked from core CPU hotplug code after hotplug operations
2064 void arch_smt_update(void)
2066 /* Handle the speculative execution misfeatures */
2067 cpu_bugs_smt_update();
2068 /* Check whether IPI broadcasting can be enabled */