1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched/mm.h>
11 #include <linux/sched/clock.h>
12 #include <linux/sched/task.h>
13 #include <linux/init.h>
14 #include <linux/kprobes.h>
15 #include <linux/kgdb.h>
16 #include <linux/smp.h>
18 #include <linux/syscore_ops.h>
20 #include <asm/stackprotector.h>
21 #include <asm/perf_event.h>
22 #include <asm/mmu_context.h>
23 #include <asm/archrandom.h>
24 #include <asm/hypervisor.h>
25 #include <asm/processor.h>
26 #include <asm/tlbflush.h>
27 #include <asm/debugreg.h>
28 #include <asm/sections.h>
29 #include <asm/vsyscall.h>
30 #include <linux/topology.h>
31 #include <linux/cpumask.h>
32 #include <asm/pgtable.h>
33 #include <linux/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/setup.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/hwcap2.h>
41 #include <linux/numa.h>
48 #include <asm/microcode.h>
49 #include <asm/microcode_intel.h>
50 #include <asm/intel-family.h>
51 #include <asm/cpu_device_id.h>
53 #ifdef CONFIG_X86_LOCAL_APIC
54 #include <asm/uv/uv.h>
59 u32 elf_hwcap2 __read_mostly
;
61 /* all of these masks are initialized in setup_cpu_local_masks() */
62 cpumask_var_t cpu_initialized_mask
;
63 cpumask_var_t cpu_callout_mask
;
64 cpumask_var_t cpu_callin_mask
;
66 /* representing cpus for which sibling maps can be computed */
67 cpumask_var_t cpu_sibling_setup_mask
;
69 /* correctly size the local cpu masks */
70 void __init
setup_cpu_local_masks(void)
72 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
73 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
74 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
75 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
78 static void default_init(struct cpuinfo_x86
*c
)
81 cpu_detect_cache_sizes(c
);
83 /* Not much we can do here... */
84 /* Check if at least it has cpuid */
85 if (c
->cpuid_level
== -1) {
86 /* No cpuid. It must be an ancient CPU */
88 strcpy(c
->x86_model_id
, "486");
90 strcpy(c
->x86_model_id
, "386");
95 static const struct cpu_dev default_cpu
= {
96 .c_init
= default_init
,
97 .c_vendor
= "Unknown",
98 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
101 static const struct cpu_dev
*this_cpu
= &default_cpu
;
103 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
106 * We need valid kernel segments for data and code in long mode too
107 * IRET will check the segment types kkeil 2000/10/28
108 * Also sysret mandates a special GDT layout
110 * TLS descriptors are currently at a different place compared to i386.
111 * Hopefully nobody expects them at a fixed place (Wine?)
113 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
115 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
118 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
120 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
121 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
122 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
123 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
125 * Segments used for calling PnP BIOS have byte granularity.
126 * They code segments and data segments have fixed 64k limits,
127 * the transfer segment sizes are set at run time.
130 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
132 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
134 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
136 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
138 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
140 * The APM segments have byte granularity and their bases
141 * are set at run time. All have 64k limits.
144 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
146 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
148 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
150 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
151 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
152 GDT_STACK_CANARY_INIT
155 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
157 static int __init
x86_mpx_setup(char *s
)
159 /* require an exact match without trailing characters */
163 /* do not emit a message if the feature is not present */
164 if (!boot_cpu_has(X86_FEATURE_MPX
))
167 setup_clear_cpu_cap(X86_FEATURE_MPX
);
168 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
171 __setup("nompx", x86_mpx_setup
);
174 static int __init
x86_nopcid_setup(char *s
)
176 /* nopcid doesn't accept parameters */
180 /* do not emit a message if the feature is not present */
181 if (!boot_cpu_has(X86_FEATURE_PCID
))
184 setup_clear_cpu_cap(X86_FEATURE_PCID
);
185 pr_info("nopcid: PCID feature disabled\n");
188 early_param("nopcid", x86_nopcid_setup
);
191 static int __init
x86_noinvpcid_setup(char *s
)
193 /* noinvpcid doesn't accept parameters */
197 /* do not emit a message if the feature is not present */
198 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
201 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
202 pr_info("noinvpcid: INVPCID feature disabled\n");
205 early_param("noinvpcid", x86_noinvpcid_setup
);
208 static int cachesize_override
= -1;
209 static int disable_x86_serial_nr
= 1;
211 static int __init
cachesize_setup(char *str
)
213 get_option(&str
, &cachesize_override
);
216 __setup("cachesize=", cachesize_setup
);
218 static int __init
x86_sep_setup(char *s
)
220 setup_clear_cpu_cap(X86_FEATURE_SEP
);
223 __setup("nosep", x86_sep_setup
);
225 /* Standard macro to see if a specific flag is changeable */
226 static inline int flag_is_changeable_p(u32 flag
)
231 * Cyrix and IDT cpus allow disabling of CPUID
232 * so the code below may return different results
233 * when it is executed before and after enabling
234 * the CPUID. Add "volatile" to not allow gcc to
235 * optimize the subsequent calls to this function.
237 asm volatile ("pushfl \n\t"
248 : "=&r" (f1
), "=&r" (f2
)
251 return ((f1
^f2
) & flag
) != 0;
254 /* Probe for the CPUID instruction */
255 int have_cpuid_p(void)
257 return flag_is_changeable_p(X86_EFLAGS_ID
);
260 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
262 unsigned long lo
, hi
;
264 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
267 /* Disable processor serial number: */
269 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
271 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
273 pr_notice("CPU serial number disabled.\n");
274 clear_cpu_cap(c
, X86_FEATURE_PN
);
276 /* Disabling the serial number may affect the cpuid level */
277 c
->cpuid_level
= cpuid_eax(0);
280 static int __init
x86_serial_nr_setup(char *s
)
282 disable_x86_serial_nr
= 0;
285 __setup("serialnumber", x86_serial_nr_setup
);
287 static inline int flag_is_changeable_p(u32 flag
)
291 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
296 static __init
int setup_disable_smep(char *arg
)
298 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
299 /* Check for things that depend on SMEP being enabled: */
300 check_mpx_erratum(&boot_cpu_data
);
303 __setup("nosmep", setup_disable_smep
);
305 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
307 if (cpu_has(c
, X86_FEATURE_SMEP
))
308 cr4_set_bits(X86_CR4_SMEP
);
311 static __init
int setup_disable_smap(char *arg
)
313 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
316 __setup("nosmap", setup_disable_smap
);
318 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
320 unsigned long eflags
= native_save_fl();
322 /* This should have been cleared long ago */
323 BUG_ON(eflags
& X86_EFLAGS_AC
);
325 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
326 #ifdef CONFIG_X86_SMAP
327 cr4_set_bits(X86_CR4_SMAP
);
329 cr4_clear_bits(X86_CR4_SMAP
);
334 static __always_inline
void setup_umip(struct cpuinfo_x86
*c
)
336 /* Check the boot processor, plus build option for UMIP. */
337 if (!cpu_feature_enabled(X86_FEATURE_UMIP
))
340 /* Check the current processor's cpuid bits. */
341 if (!cpu_has(c
, X86_FEATURE_UMIP
))
344 cr4_set_bits(X86_CR4_UMIP
);
346 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n");
352 * Make sure UMIP is disabled in case it was enabled in a
353 * previous boot (e.g., via kexec).
355 cr4_clear_bits(X86_CR4_UMIP
);
359 * Protection Keys are not available in 32-bit mode.
361 static bool pku_disabled
;
363 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
365 /* check the boot processor, plus compile options for PKU: */
366 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
368 /* checks the actual processor's cpuid bits: */
369 if (!cpu_has(c
, X86_FEATURE_PKU
))
374 cr4_set_bits(X86_CR4_PKE
);
376 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
377 * cpuid bit to be set. We need to ensure that we
378 * update that bit in this CPU's "cpu_info".
383 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
384 static __init
int setup_disable_pku(char *arg
)
387 * Do not clear the X86_FEATURE_PKU bit. All of the
388 * runtime checks are against OSPKE so clearing the
391 * This way, we will see "pku" in cpuinfo, but not
392 * "ospke", which is exactly what we want. It shows
393 * that the CPU has PKU, but the OS has not enabled it.
394 * This happens to be exactly how a system would look
395 * if we disabled the config option.
397 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
401 __setup("nopku", setup_disable_pku
);
402 #endif /* CONFIG_X86_64 */
405 * Some CPU features depend on higher CPUID levels, which may not always
406 * be available due to CPUID level capping or broken virtualization
407 * software. Add those features to this table to auto-disable them.
409 struct cpuid_dependent_feature
{
414 static const struct cpuid_dependent_feature
415 cpuid_dependent_features
[] = {
416 { X86_FEATURE_MWAIT
, 0x00000005 },
417 { X86_FEATURE_DCA
, 0x00000009 },
418 { X86_FEATURE_XSAVE
, 0x0000000d },
422 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
424 const struct cpuid_dependent_feature
*df
;
426 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
428 if (!cpu_has(c
, df
->feature
))
431 * Note: cpuid_level is set to -1 if unavailable, but
432 * extended_extended_level is set to 0 if unavailable
433 * and the legitimate extended levels are all negative
434 * when signed; hence the weird messing around with
437 if (!((s32
)df
->level
< 0 ?
438 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
439 (s32
)df
->level
> (s32
)c
->cpuid_level
))
442 clear_cpu_cap(c
, df
->feature
);
446 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
447 x86_cap_flag(df
->feature
), df
->level
);
452 * Naming convention should be: <Name> [(<Codename>)]
453 * This table only is used unless init_<vendor>() below doesn't set it;
454 * in particular, if CPUID levels 0x80000002..4 are supported, this
458 /* Look up CPU names by table lookup. */
459 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
462 const struct legacy_cpu_model_info
*info
;
464 if (c
->x86_model
>= 16)
465 return NULL
; /* Range check */
470 info
= this_cpu
->legacy_models
;
472 while (info
->family
) {
473 if (info
->family
== c
->x86
)
474 return info
->model_names
[c
->x86_model
];
478 return NULL
; /* Not found */
481 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
];
482 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
];
484 void load_percpu_segment(int cpu
)
487 loadsegment(fs
, __KERNEL_PERCPU
);
489 __loadsegment_simple(gs
, 0);
490 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
492 load_stack_canary_segment();
496 /* The 32-bit entry code needs to find cpu_entry_area. */
497 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
502 * Special IST stacks which the CPU switches to when it calls
503 * an IST-marked descriptor entry. Up to 7 stacks (hardware
504 * limit), all of them are 4K, except the debug stack which
507 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
508 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
509 [DEBUG_STACK
- 1] = DEBUG_STKSZ
513 /* Load the original GDT from the per-cpu structure */
514 void load_direct_gdt(int cpu
)
516 struct desc_ptr gdt_descr
;
518 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
519 gdt_descr
.size
= GDT_SIZE
- 1;
520 load_gdt(&gdt_descr
);
522 EXPORT_SYMBOL_GPL(load_direct_gdt
);
524 /* Load a fixmap remapping of the per-cpu GDT */
525 void load_fixmap_gdt(int cpu
)
527 struct desc_ptr gdt_descr
;
529 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
530 gdt_descr
.size
= GDT_SIZE
- 1;
531 load_gdt(&gdt_descr
);
533 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
536 * Current gdt points %fs at the "master" per-cpu area: after this,
537 * it's on the real one.
539 void switch_to_new_gdt(int cpu
)
541 /* Load the original GDT */
542 load_direct_gdt(cpu
);
543 /* Reload the per-cpu base */
544 load_percpu_segment(cpu
);
547 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
549 static void get_model_name(struct cpuinfo_x86
*c
)
554 if (c
->extended_cpuid_level
< 0x80000004)
557 v
= (unsigned int *)c
->x86_model_id
;
558 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
559 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
560 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
561 c
->x86_model_id
[48] = 0;
563 /* Trim whitespace */
564 p
= q
= s
= &c
->x86_model_id
[0];
570 /* Note the last non-whitespace index */
580 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
582 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
584 n
= c
->extended_cpuid_level
;
586 if (n
>= 0x80000005) {
587 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
588 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
590 /* On K8 L1 TLB is inclusive, so don't count it */
595 if (n
< 0x80000006) /* Some chips just has a large L1. */
598 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
602 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
604 /* do processor-specific cache resizing */
605 if (this_cpu
->legacy_cache_size
)
606 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
608 /* Allow user to override all this if necessary. */
609 if (cachesize_override
!= -1)
610 l2size
= cachesize_override
;
613 return; /* Again, no L2 cache is possible */
616 c
->x86_cache_size
= l2size
;
619 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
620 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
621 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
622 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
623 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
624 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
625 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
627 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
629 if (this_cpu
->c_detect_tlb
)
630 this_cpu
->c_detect_tlb(c
);
632 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
633 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
634 tlb_lli_4m
[ENTRIES
]);
636 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
637 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
638 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
641 void detect_ht(struct cpuinfo_x86
*c
)
644 u32 eax
, ebx
, ecx
, edx
;
645 int index_msb
, core_bits
;
648 if (!cpu_has(c
, X86_FEATURE_HT
))
651 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
654 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
657 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
659 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
661 if (smp_num_siblings
== 1) {
662 pr_info_once("CPU0: Hyper-Threading is disabled\n");
666 if (smp_num_siblings
<= 1)
669 index_msb
= get_count_order(smp_num_siblings
);
670 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
672 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
674 index_msb
= get_count_order(smp_num_siblings
);
676 core_bits
= get_count_order(c
->x86_max_cores
);
678 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
679 ((1 << core_bits
) - 1);
682 if (!printed
&& (c
->x86_max_cores
* smp_num_siblings
) > 1) {
683 pr_info("CPU: Physical Processor ID: %d\n",
685 pr_info("CPU: Processor Core ID: %d\n",
692 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
694 char *v
= c
->x86_vendor_id
;
697 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
701 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
702 (cpu_devs
[i
]->c_ident
[1] &&
703 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
705 this_cpu
= cpu_devs
[i
];
706 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
711 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
712 "CPU: Your system may be unstable.\n", v
);
714 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
715 this_cpu
= &default_cpu
;
718 void cpu_detect(struct cpuinfo_x86
*c
)
720 /* Get vendor name */
721 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
722 (unsigned int *)&c
->x86_vendor_id
[0],
723 (unsigned int *)&c
->x86_vendor_id
[8],
724 (unsigned int *)&c
->x86_vendor_id
[4]);
727 /* Intel-defined flags: level 0x00000001 */
728 if (c
->cpuid_level
>= 0x00000001) {
729 u32 junk
, tfms
, cap0
, misc
;
731 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
732 c
->x86
= x86_family(tfms
);
733 c
->x86_model
= x86_model(tfms
);
734 c
->x86_stepping
= x86_stepping(tfms
);
736 if (cap0
& (1<<19)) {
737 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
738 c
->x86_cache_alignment
= c
->x86_clflush_size
;
743 static void apply_forced_caps(struct cpuinfo_x86
*c
)
747 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
748 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
749 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
753 static void init_speculation_control(struct cpuinfo_x86
*c
)
756 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
757 * and they also have a different bit for STIBP support. Also,
758 * a hypervisor might have set the individual AMD bits even on
759 * Intel CPUs, for finer-grained selection of what's available.
761 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
762 set_cpu_cap(c
, X86_FEATURE_IBRS
);
763 set_cpu_cap(c
, X86_FEATURE_IBPB
);
764 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
767 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
768 set_cpu_cap(c
, X86_FEATURE_STIBP
);
770 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
771 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
772 set_cpu_cap(c
, X86_FEATURE_SSBD
);
774 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
775 set_cpu_cap(c
, X86_FEATURE_IBRS
);
776 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
779 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
780 set_cpu_cap(c
, X86_FEATURE_IBPB
);
782 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
783 set_cpu_cap(c
, X86_FEATURE_STIBP
);
784 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
788 void get_cpu_cap(struct cpuinfo_x86
*c
)
790 u32 eax
, ebx
, ecx
, edx
;
792 /* Intel-defined flags: level 0x00000001 */
793 if (c
->cpuid_level
>= 0x00000001) {
794 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
796 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
797 c
->x86_capability
[CPUID_1_EDX
] = edx
;
800 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
801 if (c
->cpuid_level
>= 0x00000006)
802 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
804 /* Additional Intel-defined flags: level 0x00000007 */
805 if (c
->cpuid_level
>= 0x00000007) {
806 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
807 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
808 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
809 c
->x86_capability
[CPUID_7_EDX
] = edx
;
812 /* Extended state features: level 0x0000000d */
813 if (c
->cpuid_level
>= 0x0000000d) {
814 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
816 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
819 /* Additional Intel-defined flags: level 0x0000000F */
820 if (c
->cpuid_level
>= 0x0000000F) {
822 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
823 cpuid_count(0x0000000F, 0, &eax
, &ebx
, &ecx
, &edx
);
824 c
->x86_capability
[CPUID_F_0_EDX
] = edx
;
826 if (cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
827 /* will be overridden if occupancy monitoring exists */
828 c
->x86_cache_max_rmid
= ebx
;
830 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
831 cpuid_count(0x0000000F, 1, &eax
, &ebx
, &ecx
, &edx
);
832 c
->x86_capability
[CPUID_F_1_EDX
] = edx
;
834 if ((cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
)) ||
835 ((cpu_has(c
, X86_FEATURE_CQM_MBM_TOTAL
)) ||
836 (cpu_has(c
, X86_FEATURE_CQM_MBM_LOCAL
)))) {
837 c
->x86_cache_max_rmid
= ecx
;
838 c
->x86_cache_occ_scale
= ebx
;
841 c
->x86_cache_max_rmid
= -1;
842 c
->x86_cache_occ_scale
= -1;
846 /* AMD-defined flags: level 0x80000001 */
847 eax
= cpuid_eax(0x80000000);
848 c
->extended_cpuid_level
= eax
;
850 if ((eax
& 0xffff0000) == 0x80000000) {
851 if (eax
>= 0x80000001) {
852 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
854 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
855 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
859 if (c
->extended_cpuid_level
>= 0x80000007) {
860 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
862 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
866 if (c
->extended_cpuid_level
>= 0x80000008) {
867 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
869 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
870 c
->x86_phys_bits
= eax
& 0xff;
871 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
874 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
875 c
->x86_phys_bits
= 36;
878 if (c
->extended_cpuid_level
>= 0x8000000a)
879 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
881 init_scattered_cpuid_features(c
);
882 init_speculation_control(c
);
885 * Clear/Set all flags overridden by options, after probe.
886 * This needs to happen each time we re-probe, which may happen
887 * several times during CPU initialization.
889 apply_forced_caps(c
);
892 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
898 * First of all, decide if this is a 486 or higher
899 * It's a 486 if we can modify the AC flag
901 if (flag_is_changeable_p(X86_EFLAGS_AC
))
906 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
907 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
908 c
->x86_vendor_id
[0] = 0;
909 cpu_devs
[i
]->c_identify(c
);
910 if (c
->x86_vendor_id
[0]) {
918 static const __initconst
struct x86_cpu_id cpu_no_speculation
[] = {
919 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_CEDARVIEW
, X86_FEATURE_ANY
},
920 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_CLOVERVIEW
, X86_FEATURE_ANY
},
921 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_LINCROFT
, X86_FEATURE_ANY
},
922 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_PENWELL
, X86_FEATURE_ANY
},
923 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_PINEVIEW
, X86_FEATURE_ANY
},
924 { X86_VENDOR_CENTAUR
, 5 },
925 { X86_VENDOR_INTEL
, 5 },
926 { X86_VENDOR_NSC
, 5 },
927 { X86_VENDOR_ANY
, 4 },
931 static const __initconst
struct x86_cpu_id cpu_no_meltdown
[] = {
936 static const __initconst
struct x86_cpu_id cpu_no_spec_store_bypass
[] = {
937 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_PINEVIEW
},
938 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_LINCROFT
},
939 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_PENWELL
},
940 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_CLOVERVIEW
},
941 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_CEDARVIEW
},
942 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_SILVERMONT1
},
943 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_AIRMONT
},
944 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_SILVERMONT2
},
945 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_ATOM_MERRIFIELD
},
946 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_CORE_YONAH
},
947 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_XEON_PHI_KNL
},
948 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_XEON_PHI_KNM
},
949 { X86_VENDOR_CENTAUR
, 5, },
950 { X86_VENDOR_INTEL
, 5, },
951 { X86_VENDOR_NSC
, 5, },
952 { X86_VENDOR_AMD
, 0x12, },
953 { X86_VENDOR_AMD
, 0x11, },
954 { X86_VENDOR_AMD
, 0x10, },
955 { X86_VENDOR_AMD
, 0xf, },
956 { X86_VENDOR_ANY
, 4, },
960 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
964 if (cpu_has(c
, X86_FEATURE_ARCH_CAPABILITIES
))
965 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
967 if (!x86_match_cpu(cpu_no_spec_store_bypass
) &&
968 !(ia32_cap
& ARCH_CAP_SSBD_NO
))
969 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
971 if (x86_match_cpu(cpu_no_speculation
))
974 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
975 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
977 if (x86_match_cpu(cpu_no_meltdown
))
980 /* Rogue Data Cache Load? No! */
981 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
984 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
988 * Do minimum CPU detection early.
989 * Fields really needed: vendor, cpuid_level, family, model, mask,
991 * The others are not touched to avoid unwanted side effects.
993 * WARNING: this function is only called on the boot CPU. Don't add code
994 * here that is supposed to run on all CPUs.
996 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
999 c
->x86_clflush_size
= 64;
1000 c
->x86_phys_bits
= 36;
1001 c
->x86_virt_bits
= 48;
1003 c
->x86_clflush_size
= 32;
1004 c
->x86_phys_bits
= 32;
1005 c
->x86_virt_bits
= 32;
1007 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1009 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
1010 c
->extended_cpuid_level
= 0;
1012 /* cyrix could have cpuid enabled via c_identify()*/
1013 if (have_cpuid_p()) {
1017 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1019 if (this_cpu
->c_early_init
)
1020 this_cpu
->c_early_init(c
);
1023 filter_cpuid_features(c
, false);
1025 if (this_cpu
->c_bsp_init
)
1026 this_cpu
->c_bsp_init(c
);
1028 identify_cpu_without_cpuid(c
);
1029 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1032 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1034 cpu_set_bug_bits(c
);
1036 fpu__init_system(c
);
1038 #ifdef CONFIG_X86_32
1040 * Regardless of whether PCID is enumerated, the SDM says
1041 * that it can't be enabled in 32-bit mode.
1043 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1047 void __init
early_cpu_init(void)
1049 const struct cpu_dev
*const *cdev
;
1052 #ifdef CONFIG_PROCESSOR_SELECT
1053 pr_info("KERNEL supported cpus:\n");
1056 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1057 const struct cpu_dev
*cpudev
= *cdev
;
1059 if (count
>= X86_VENDOR_NUM
)
1061 cpu_devs
[count
] = cpudev
;
1064 #ifdef CONFIG_PROCESSOR_SELECT
1068 for (j
= 0; j
< 2; j
++) {
1069 if (!cpudev
->c_ident
[j
])
1071 pr_info(" %s %s\n", cpudev
->c_vendor
,
1072 cpudev
->c_ident
[j
]);
1077 early_identify_cpu(&boot_cpu_data
);
1081 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1082 * unfortunately, that's not true in practice because of early VIA
1083 * chips and (more importantly) broken virtualizers that are not easy
1084 * to detect. In the latter case it doesn't even *fail* reliably, so
1085 * probing for it doesn't even work. Disable it completely on 32-bit
1086 * unless we can find a reliable way to detect all the broken cases.
1087 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1089 static void detect_nopl(struct cpuinfo_x86
*c
)
1091 #ifdef CONFIG_X86_32
1092 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
1094 set_cpu_cap(c
, X86_FEATURE_NOPL
);
1098 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
1100 #ifdef CONFIG_X86_64
1102 * Empirically, writing zero to a segment selector on AMD does
1103 * not clear the base, whereas writing zero to a segment
1104 * selector on Intel does clear the base. Intel's behavior
1105 * allows slightly faster context switches in the common case
1106 * where GS is unused by the prev and next threads.
1108 * Since neither vendor documents this anywhere that I can see,
1109 * detect it directly instead of hardcoding the choice by
1112 * I've designated AMD's behavior as the "bug" because it's
1113 * counterintuitive and less friendly.
1116 unsigned long old_base
, tmp
;
1117 rdmsrl(MSR_FS_BASE
, old_base
);
1118 wrmsrl(MSR_FS_BASE
, 1);
1120 rdmsrl(MSR_FS_BASE
, tmp
);
1122 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1123 wrmsrl(MSR_FS_BASE
, old_base
);
1127 static void generic_identify(struct cpuinfo_x86
*c
)
1129 c
->extended_cpuid_level
= 0;
1131 if (!have_cpuid_p())
1132 identify_cpu_without_cpuid(c
);
1134 /* cyrix could have cpuid enabled via c_identify()*/
1135 if (!have_cpuid_p())
1144 if (c
->cpuid_level
>= 0x00000001) {
1145 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1146 #ifdef CONFIG_X86_32
1148 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1150 c
->apicid
= c
->initial_apicid
;
1153 c
->phys_proc_id
= c
->initial_apicid
;
1156 get_model_name(c
); /* Default name */
1160 detect_null_seg_behavior(c
);
1163 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1164 * systems that run Linux at CPL > 0 may or may not have the
1165 * issue, but, even if they have the issue, there's absolutely
1166 * nothing we can do about it because we can't use the real IRET
1169 * NB: For the time being, only 32-bit kernels support
1170 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1171 * whether to apply espfix using paravirt hooks. If any
1172 * non-paravirt system ever shows up that does *not* have the
1173 * ESPFIX issue, we can change this.
1175 #ifdef CONFIG_X86_32
1176 # ifdef CONFIG_PARAVIRT
1178 extern void native_iret(void);
1179 if (pv_cpu_ops
.iret
== native_iret
)
1180 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1183 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1188 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
1191 * The heavy lifting of max_rmid and cache_occ_scale are handled
1192 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1193 * in case CQM bits really aren't there in this CPU.
1195 if (c
!= &boot_cpu_data
) {
1196 boot_cpu_data
.x86_cache_max_rmid
=
1197 min(boot_cpu_data
.x86_cache_max_rmid
,
1198 c
->x86_cache_max_rmid
);
1203 * Validate that ACPI/mptables have the same information about the
1204 * effective APIC id and update the package map.
1206 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1209 unsigned int apicid
, cpu
= smp_processor_id();
1211 apicid
= apic
->cpu_present_to_apicid(cpu
);
1213 if (apicid
!= c
->apicid
) {
1214 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1215 cpu
, apicid
, c
->initial_apicid
);
1217 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1219 c
->logical_proc_id
= 0;
1224 * This does the hard work of actually picking apart the CPU stuff...
1226 static void identify_cpu(struct cpuinfo_x86
*c
)
1230 c
->loops_per_jiffy
= loops_per_jiffy
;
1231 c
->x86_cache_size
= 0;
1232 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1233 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1234 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1235 c
->x86_model_id
[0] = '\0'; /* Unset */
1236 c
->x86_max_cores
= 1;
1237 c
->x86_coreid_bits
= 0;
1239 #ifdef CONFIG_X86_64
1240 c
->x86_clflush_size
= 64;
1241 c
->x86_phys_bits
= 36;
1242 c
->x86_virt_bits
= 48;
1244 c
->cpuid_level
= -1; /* CPUID not detected */
1245 c
->x86_clflush_size
= 32;
1246 c
->x86_phys_bits
= 32;
1247 c
->x86_virt_bits
= 32;
1249 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1250 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
1252 generic_identify(c
);
1254 if (this_cpu
->c_identify
)
1255 this_cpu
->c_identify(c
);
1257 /* Clear/Set all flags overridden by options, after probe */
1258 apply_forced_caps(c
);
1260 #ifdef CONFIG_X86_64
1261 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1265 * Vendor-specific initialization. In this section we
1266 * canonicalize the feature flags, meaning if there are
1267 * features a certain CPU supports which CPUID doesn't
1268 * tell us, CPUID claiming incorrect flags, or other bugs,
1269 * we handle them here.
1271 * At the end of this section, c->x86_capability better
1272 * indicate the features this CPU genuinely supports!
1274 if (this_cpu
->c_init
)
1275 this_cpu
->c_init(c
);
1277 /* Disable the PN if appropriate */
1278 squash_the_stupid_serial_number(c
);
1280 /* Set up SMEP/SMAP/UMIP */
1286 * The vendor-specific functions might have changed features.
1287 * Now we do "generic changes."
1290 /* Filter out anything that depends on CPUID levels we don't have */
1291 filter_cpuid_features(c
, true);
1293 /* If the model name is still unset, do table lookup. */
1294 if (!c
->x86_model_id
[0]) {
1296 p
= table_lookup_model(c
);
1298 strcpy(c
->x86_model_id
, p
);
1300 /* Last resort... */
1301 sprintf(c
->x86_model_id
, "%02x/%02x",
1302 c
->x86
, c
->x86_model
);
1305 #ifdef CONFIG_X86_64
1310 x86_init_cache_qos(c
);
1314 * Clear/Set all flags overridden by options, need do it
1315 * before following smp all cpus cap AND.
1317 apply_forced_caps(c
);
1320 * On SMP, boot_cpu_data holds the common feature set between
1321 * all CPUs; so make sure that we indicate which features are
1322 * common between the CPUs. The first time this routine gets
1323 * executed, c == &boot_cpu_data.
1325 if (c
!= &boot_cpu_data
) {
1326 /* AND the already accumulated flags with these */
1327 for (i
= 0; i
< NCAPINTS
; i
++)
1328 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1330 /* OR, i.e. replicate the bug flags */
1331 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1332 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1335 /* Init Machine Check Exception if available. */
1338 select_idle_routine(c
);
1341 numa_add_cpu(smp_processor_id());
1346 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1347 * on 32-bit kernels:
1349 #ifdef CONFIG_X86_32
1350 void enable_sep_cpu(void)
1352 struct tss_struct
*tss
;
1355 if (!boot_cpu_has(X86_FEATURE_SEP
))
1359 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1362 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1363 * see the big comment in struct x86_hw_tss's definition.
1366 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1367 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1368 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1369 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1375 void __init
identify_boot_cpu(void)
1377 identify_cpu(&boot_cpu_data
);
1378 #ifdef CONFIG_X86_32
1382 cpu_detect_tlb(&boot_cpu_data
);
1385 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1387 BUG_ON(c
== &boot_cpu_data
);
1389 #ifdef CONFIG_X86_32
1393 validate_apic_and_package_id(c
);
1394 x86_spec_ctrl_setup_ap();
1397 static __init
int setup_noclflush(char *arg
)
1399 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1400 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1403 __setup("noclflush", setup_noclflush
);
1405 void print_cpu_info(struct cpuinfo_x86
*c
)
1407 const char *vendor
= NULL
;
1409 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1410 vendor
= this_cpu
->c_vendor
;
1412 if (c
->cpuid_level
>= 0)
1413 vendor
= c
->x86_vendor_id
;
1416 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1417 pr_cont("%s ", vendor
);
1419 if (c
->x86_model_id
[0])
1420 pr_cont("%s", c
->x86_model_id
);
1422 pr_cont("%d86", c
->x86
);
1424 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1426 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
1427 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
1433 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1434 * But we need to keep a dummy __setup around otherwise it would
1435 * show up as an environment variable for init.
1437 static __init
int setup_clearcpuid(char *arg
)
1441 __setup("clearcpuid=", setup_clearcpuid
);
1443 #ifdef CONFIG_X86_64
1444 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
1445 irq_stack_union
) __aligned(PAGE_SIZE
) __visible
;
1448 * The following percpu variables are hot. Align current_task to
1449 * cacheline size such that they fall in the same cacheline.
1451 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1453 EXPORT_PER_CPU_SYMBOL(current_task
);
1455 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
1456 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
;
1458 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1460 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1461 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1463 /* May not be marked __init: used by software suspend */
1464 void syscall_init(void)
1466 extern char _entry_trampoline
[];
1467 extern char entry_SYSCALL_64_trampoline
[];
1469 int cpu
= smp_processor_id();
1470 unsigned long SYSCALL64_entry_trampoline
=
1471 (unsigned long)get_cpu_entry_area(cpu
)->entry_trampoline
+
1472 (entry_SYSCALL_64_trampoline
- _entry_trampoline
);
1474 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1475 if (static_cpu_has(X86_FEATURE_PTI
))
1476 wrmsrl(MSR_LSTAR
, SYSCALL64_entry_trampoline
);
1478 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1480 #ifdef CONFIG_IA32_EMULATION
1481 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1483 * This only works on Intel CPUs.
1484 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1485 * This does not cause SYSENTER to jump to the wrong location, because
1486 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1488 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1489 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1));
1490 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1492 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1493 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1494 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1495 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1498 /* Flags to clear on syscall */
1499 wrmsrl(MSR_SYSCALL_MASK
,
1500 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1501 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1505 * Copies of the original ist values from the tss are only accessed during
1506 * debugging, no special alignment required.
1508 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1510 static DEFINE_PER_CPU(unsigned long, debug_stack_addr
);
1511 DEFINE_PER_CPU(int, debug_stack_usage
);
1513 int is_debug_stack(unsigned long addr
)
1515 return __this_cpu_read(debug_stack_usage
) ||
1516 (addr
<= __this_cpu_read(debug_stack_addr
) &&
1517 addr
> (__this_cpu_read(debug_stack_addr
) - DEBUG_STKSZ
));
1519 NOKPROBE_SYMBOL(is_debug_stack
);
1521 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1523 void debug_stack_set_zero(void)
1525 this_cpu_inc(debug_idt_ctr
);
1528 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1530 void debug_stack_reset(void)
1532 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1534 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1537 NOKPROBE_SYMBOL(debug_stack_reset
);
1539 #else /* CONFIG_X86_64 */
1541 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1542 EXPORT_PER_CPU_SYMBOL(current_task
);
1543 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1544 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1547 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1548 * the top of the kernel stack. Use an extra percpu variable to track the
1549 * top of the kernel stack directly.
1551 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1552 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1553 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1555 #ifdef CONFIG_CC_STACKPROTECTOR
1556 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1559 #endif /* CONFIG_X86_64 */
1562 * Clear all 6 debug registers:
1564 static void clear_all_debug_regs(void)
1568 for (i
= 0; i
< 8; i
++) {
1569 /* Ignore db4, db5 */
1570 if ((i
== 4) || (i
== 5))
1579 * Restore debug regs if using kgdbwait and you have a kernel debugger
1580 * connection established.
1582 static void dbg_restore_debug_regs(void)
1584 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1585 arch_kgdb_ops
.correct_hw_break();
1587 #else /* ! CONFIG_KGDB */
1588 #define dbg_restore_debug_regs()
1589 #endif /* ! CONFIG_KGDB */
1591 static void wait_for_master_cpu(int cpu
)
1595 * wait for ACK from master CPU before continuing
1596 * with AP initialization
1598 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1599 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1605 * cpu_init() initializes state that is per-CPU. Some data is already
1606 * initialized (naturally) in the bootstrap process, such as the GDT
1607 * and IDT. We reload them nevertheless, this function acts as a
1608 * 'CPU state barrier', nothing should get across.
1609 * A lot of state is already set up in PDA init for 64 bit
1611 #ifdef CONFIG_X86_64
1615 struct orig_ist
*oist
;
1616 struct task_struct
*me
;
1617 struct tss_struct
*t
;
1619 int cpu
= raw_smp_processor_id();
1622 wait_for_master_cpu(cpu
);
1625 * Initialize the CR4 shadow before doing anything that could
1633 t
= &per_cpu(cpu_tss_rw
, cpu
);
1634 oist
= &per_cpu(orig_ist
, cpu
);
1637 if (this_cpu_read(numa_node
) == 0 &&
1638 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1639 set_numa_node(early_cpu_to_node(cpu
));
1644 pr_debug("Initializing CPU#%d\n", cpu
);
1646 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1649 * Initialize the per-CPU GDT with the boot GDT,
1650 * and set up the GDT descriptor:
1653 switch_to_new_gdt(cpu
);
1658 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1661 wrmsrl(MSR_FS_BASE
, 0);
1662 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1669 * set up and load the per-CPU TSS
1671 if (!oist
->ist
[0]) {
1672 char *estacks
= get_cpu_entry_area(cpu
)->exception_stacks
;
1674 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1675 estacks
+= exception_stack_sizes
[v
];
1676 oist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1677 (unsigned long)estacks
;
1678 if (v
== DEBUG_STACK
-1)
1679 per_cpu(debug_stack_addr
, cpu
) = (unsigned long)estacks
;
1683 t
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET
;
1686 * <= is required because the CPU will access up to
1687 * 8 bits beyond the end of the IO permission bitmap.
1689 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1690 t
->io_bitmap
[i
] = ~0UL;
1693 me
->active_mm
= &init_mm
;
1695 initialize_tlbstate_and_flush();
1696 enter_lazy_tlb(&init_mm
, me
);
1699 * Initialize the TSS. sp0 points to the entry trampoline stack
1700 * regardless of what task is running.
1702 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1704 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
1706 load_mm_ldt(&init_mm
);
1708 clear_all_debug_regs();
1709 dbg_restore_debug_regs();
1716 load_fixmap_gdt(cpu
);
1723 int cpu
= smp_processor_id();
1724 struct task_struct
*curr
= current
;
1725 struct tss_struct
*t
= &per_cpu(cpu_tss_rw
, cpu
);
1727 wait_for_master_cpu(cpu
);
1730 * Initialize the CR4 shadow before doing anything that could
1735 show_ucode_info_early();
1737 pr_info("Initializing CPU#%d\n", cpu
);
1739 if (cpu_feature_enabled(X86_FEATURE_VME
) ||
1740 boot_cpu_has(X86_FEATURE_TSC
) ||
1741 boot_cpu_has(X86_FEATURE_DE
))
1742 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1745 switch_to_new_gdt(cpu
);
1748 * Set up and load the per-CPU TSS and LDT
1751 curr
->active_mm
= &init_mm
;
1753 initialize_tlbstate_and_flush();
1754 enter_lazy_tlb(&init_mm
, curr
);
1757 * Initialize the TSS. Don't bother initializing sp0, as the initial
1758 * task never enters user mode.
1760 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1763 load_mm_ldt(&init_mm
);
1765 t
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET
;
1767 #ifdef CONFIG_DOUBLEFAULT
1768 /* Set up doublefault TSS pointer in the GDT */
1769 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1772 clear_all_debug_regs();
1773 dbg_restore_debug_regs();
1777 load_fixmap_gdt(cpu
);
1781 static void bsp_resume(void)
1783 if (this_cpu
->c_bsp_resume
)
1784 this_cpu
->c_bsp_resume(&boot_cpu_data
);
1787 static struct syscore_ops cpu_syscore_ops
= {
1788 .resume
= bsp_resume
,
1791 static int __init
init_cpu_syscore(void)
1793 register_syscore_ops(&cpu_syscore_ops
);
1796 core_initcall(init_cpu_syscore
);
1799 * The microcode loader calls this upon late microcode load to recheck features,
1800 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1803 void microcode_check(void)
1805 struct cpuinfo_x86 info
;
1807 perf_check_microcode();
1809 /* Reload CPUID max function as it might've changed. */
1810 info
.cpuid_level
= cpuid_eax(0);
1813 * Copy all capability leafs to pick up the synthetic ones so that
1814 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1815 * get overwritten in get_cpu_cap().
1817 memcpy(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
));
1821 if (!memcmp(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
)))
1824 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1825 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");