1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/pgtable.h>
26 #include <asm/stackprotector.h>
27 #include <asm/perf_event.h>
28 #include <asm/mmu_context.h>
29 #include <asm/doublefault.h>
30 #include <asm/archrandom.h>
31 #include <asm/hypervisor.h>
32 #include <asm/processor.h>
33 #include <asm/tlbflush.h>
34 #include <asm/debugreg.h>
35 #include <asm/sections.h>
36 #include <asm/vsyscall.h>
37 #include <linux/topology.h>
38 #include <linux/cpumask.h>
39 #include <linux/atomic.h>
40 #include <asm/proto.h>
41 #include <asm/setup.h>
44 #include <asm/fpu/internal.h>
46 #include <asm/hwcap2.h>
47 #include <linux/numa.h>
54 #include <asm/memtype.h>
55 #include <asm/microcode.h>
56 #include <asm/microcode_intel.h>
57 #include <asm/intel-family.h>
58 #include <asm/cpu_device_id.h>
59 #include <asm/uv/uv.h>
63 u32 elf_hwcap2 __read_mostly
;
65 /* all of these masks are initialized in setup_cpu_local_masks() */
66 cpumask_var_t cpu_initialized_mask
;
67 cpumask_var_t cpu_callout_mask
;
68 cpumask_var_t cpu_callin_mask
;
70 /* representing cpus for which sibling maps can be computed */
71 cpumask_var_t cpu_sibling_setup_mask
;
73 /* Number of siblings per CPU package */
74 int smp_num_siblings
= 1;
75 EXPORT_SYMBOL(smp_num_siblings
);
77 /* Last level cache ID of each logical CPU */
78 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
80 /* correctly size the local cpu masks */
81 void __init
setup_cpu_local_masks(void)
83 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
84 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
85 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
89 static void default_init(struct cpuinfo_x86
*c
)
92 cpu_detect_cache_sizes(c
);
94 /* Not much we can do here... */
95 /* Check if at least it has cpuid */
96 if (c
->cpuid_level
== -1) {
97 /* No cpuid. It must be an ancient CPU */
99 strcpy(c
->x86_model_id
, "486");
100 else if (c
->x86
== 3)
101 strcpy(c
->x86_model_id
, "386");
106 static const struct cpu_dev default_cpu
= {
107 .c_init
= default_init
,
108 .c_vendor
= "Unknown",
109 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
112 static const struct cpu_dev
*this_cpu
= &default_cpu
;
114 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
117 * We need valid kernel segments for data and code in long mode too
118 * IRET will check the segment types kkeil 2000/10/28
119 * Also sysret mandates a special GDT layout
121 * TLS descriptors are currently at a different place compared to i386.
122 * Hopefully nobody expects them at a fixed place (Wine?)
124 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
136 * Segments used for calling PnP BIOS have byte granularity.
137 * They code segments and data segments have fixed 64k limits,
138 * the transfer segment sizes are set at run time.
141 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
147 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
149 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
151 * The APM segments have byte granularity and their bases
152 * are set at run time. All have 64k limits.
155 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
157 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
159 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
161 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 GDT_STACK_CANARY_INIT
166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
169 static int __init
x86_nopcid_setup(char *s
)
171 /* nopcid doesn't accept parameters */
175 /* do not emit a message if the feature is not present */
176 if (!boot_cpu_has(X86_FEATURE_PCID
))
179 setup_clear_cpu_cap(X86_FEATURE_PCID
);
180 pr_info("nopcid: PCID feature disabled\n");
183 early_param("nopcid", x86_nopcid_setup
);
186 static int __init
x86_noinvpcid_setup(char *s
)
188 /* noinvpcid doesn't accept parameters */
192 /* do not emit a message if the feature is not present */
193 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
196 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
197 pr_info("noinvpcid: INVPCID feature disabled\n");
200 early_param("noinvpcid", x86_noinvpcid_setup
);
203 static int cachesize_override
= -1;
204 static int disable_x86_serial_nr
= 1;
206 static int __init
cachesize_setup(char *str
)
208 get_option(&str
, &cachesize_override
);
211 __setup("cachesize=", cachesize_setup
);
213 static int __init
x86_sep_setup(char *s
)
215 setup_clear_cpu_cap(X86_FEATURE_SEP
);
218 __setup("nosep", x86_sep_setup
);
220 /* Standard macro to see if a specific flag is changeable */
221 static inline int flag_is_changeable_p(u32 flag
)
226 * Cyrix and IDT cpus allow disabling of CPUID
227 * so the code below may return different results
228 * when it is executed before and after enabling
229 * the CPUID. Add "volatile" to not allow gcc to
230 * optimize the subsequent calls to this function.
232 asm volatile ("pushfl \n\t"
243 : "=&r" (f1
), "=&r" (f2
)
246 return ((f1
^f2
) & flag
) != 0;
249 /* Probe for the CPUID instruction */
250 int have_cpuid_p(void)
252 return flag_is_changeable_p(X86_EFLAGS_ID
);
255 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
257 unsigned long lo
, hi
;
259 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
262 /* Disable processor serial number: */
264 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
266 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
268 pr_notice("CPU serial number disabled.\n");
269 clear_cpu_cap(c
, X86_FEATURE_PN
);
271 /* Disabling the serial number may affect the cpuid level */
272 c
->cpuid_level
= cpuid_eax(0);
275 static int __init
x86_serial_nr_setup(char *s
)
277 disable_x86_serial_nr
= 0;
280 __setup("serialnumber", x86_serial_nr_setup
);
282 static inline int flag_is_changeable_p(u32 flag
)
286 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
291 static __init
int setup_disable_smep(char *arg
)
293 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
296 __setup("nosmep", setup_disable_smep
);
298 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
300 if (cpu_has(c
, X86_FEATURE_SMEP
))
301 cr4_set_bits(X86_CR4_SMEP
);
304 static __init
int setup_disable_smap(char *arg
)
306 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
309 __setup("nosmap", setup_disable_smap
);
311 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
313 unsigned long eflags
= native_save_fl();
315 /* This should have been cleared long ago */
316 BUG_ON(eflags
& X86_EFLAGS_AC
);
318 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
319 #ifdef CONFIG_X86_SMAP
320 cr4_set_bits(X86_CR4_SMAP
);
322 cr4_clear_bits(X86_CR4_SMAP
);
327 static __always_inline
void setup_umip(struct cpuinfo_x86
*c
)
329 /* Check the boot processor, plus build option for UMIP. */
330 if (!cpu_feature_enabled(X86_FEATURE_UMIP
))
333 /* Check the current processor's cpuid bits. */
334 if (!cpu_has(c
, X86_FEATURE_UMIP
))
337 cr4_set_bits(X86_CR4_UMIP
);
339 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
345 * Make sure UMIP is disabled in case it was enabled in a
346 * previous boot (e.g., via kexec).
348 cr4_clear_bits(X86_CR4_UMIP
);
351 /* These bits should not change their value after CPU init is finished. */
352 static const unsigned long cr4_pinned_mask
=
353 X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_UMIP
| X86_CR4_FSGSBASE
;
354 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning
);
355 static unsigned long cr4_pinned_bits __ro_after_init
;
357 void native_write_cr0(unsigned long val
)
359 unsigned long bits_missing
= 0;
362 asm volatile("mov %0,%%cr0": "+r" (val
), "+m" (__force_order
));
364 if (static_branch_likely(&cr_pinning
)) {
365 if (unlikely((val
& X86_CR0_WP
) != X86_CR0_WP
)) {
366 bits_missing
= X86_CR0_WP
;
370 /* Warn after we've set the missing bits. */
371 WARN_ONCE(bits_missing
, "CR0 WP bit went missing!?\n");
374 EXPORT_SYMBOL(native_write_cr0
);
376 void native_write_cr4(unsigned long val
)
378 unsigned long bits_changed
= 0;
381 asm volatile("mov %0,%%cr4": "+r" (val
), "+m" (cr4_pinned_bits
));
383 if (static_branch_likely(&cr_pinning
)) {
384 if (unlikely((val
& cr4_pinned_mask
) != cr4_pinned_bits
)) {
385 bits_changed
= (val
& cr4_pinned_mask
) ^ cr4_pinned_bits
;
386 val
= (val
& ~cr4_pinned_mask
) | cr4_pinned_bits
;
389 /* Warn after we've corrected the changed bits. */
390 WARN_ONCE(bits_changed
, "pinned CR4 bits changed: 0x%lx!?\n",
394 #if IS_MODULE(CONFIG_LKDTM)
395 EXPORT_SYMBOL_GPL(native_write_cr4
);
398 void cr4_update_irqsoff(unsigned long set
, unsigned long clear
)
400 unsigned long newval
, cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
402 lockdep_assert_irqs_disabled();
404 newval
= (cr4
& ~clear
) | set
;
406 this_cpu_write(cpu_tlbstate
.cr4
, newval
);
410 EXPORT_SYMBOL(cr4_update_irqsoff
);
412 /* Read the CR4 shadow. */
413 unsigned long cr4_read_shadow(void)
415 return this_cpu_read(cpu_tlbstate
.cr4
);
417 EXPORT_SYMBOL_GPL(cr4_read_shadow
);
421 unsigned long cr4
= __read_cr4();
423 if (boot_cpu_has(X86_FEATURE_PCID
))
424 cr4
|= X86_CR4_PCIDE
;
425 if (static_branch_likely(&cr_pinning
))
426 cr4
= (cr4
& ~cr4_pinned_mask
) | cr4_pinned_bits
;
430 /* Initialize cr4 shadow for this CPU. */
431 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
435 * Once CPU feature detection is finished (and boot params have been
436 * parsed), record any of the sensitive CR bits that are set, and
439 static void __init
setup_cr_pinning(void)
441 cr4_pinned_bits
= this_cpu_read(cpu_tlbstate
.cr4
) & cr4_pinned_mask
;
442 static_key_enable(&cr_pinning
.key
);
445 static __init
int x86_nofsgsbase_setup(char *arg
)
447 /* Require an exact match without trailing characters. */
451 /* Do not emit a message if the feature is not present. */
452 if (!boot_cpu_has(X86_FEATURE_FSGSBASE
))
455 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE
);
456 pr_info("FSGSBASE disabled via kernel command line\n");
459 __setup("nofsgsbase", x86_nofsgsbase_setup
);
462 * Protection Keys are not available in 32-bit mode.
464 static bool pku_disabled
;
466 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
468 struct pkru_state
*pk
;
470 /* check the boot processor, plus compile options for PKU: */
471 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
473 /* checks the actual processor's cpuid bits: */
474 if (!cpu_has(c
, X86_FEATURE_PKU
))
479 cr4_set_bits(X86_CR4_PKE
);
480 pk
= get_xsave_addr(&init_fpstate
.xsave
, XFEATURE_PKRU
);
482 pk
->pkru
= init_pkru_value
;
484 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
485 * cpuid bit to be set. We need to ensure that we
486 * update that bit in this CPU's "cpu_info".
488 set_cpu_cap(c
, X86_FEATURE_OSPKE
);
491 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
492 static __init
int setup_disable_pku(char *arg
)
495 * Do not clear the X86_FEATURE_PKU bit. All of the
496 * runtime checks are against OSPKE so clearing the
499 * This way, we will see "pku" in cpuinfo, but not
500 * "ospke", which is exactly what we want. It shows
501 * that the CPU has PKU, but the OS has not enabled it.
502 * This happens to be exactly how a system would look
503 * if we disabled the config option.
505 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
509 __setup("nopku", setup_disable_pku
);
510 #endif /* CONFIG_X86_64 */
513 * Some CPU features depend on higher CPUID levels, which may not always
514 * be available due to CPUID level capping or broken virtualization
515 * software. Add those features to this table to auto-disable them.
517 struct cpuid_dependent_feature
{
522 static const struct cpuid_dependent_feature
523 cpuid_dependent_features
[] = {
524 { X86_FEATURE_MWAIT
, 0x00000005 },
525 { X86_FEATURE_DCA
, 0x00000009 },
526 { X86_FEATURE_XSAVE
, 0x0000000d },
530 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
532 const struct cpuid_dependent_feature
*df
;
534 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
536 if (!cpu_has(c
, df
->feature
))
539 * Note: cpuid_level is set to -1 if unavailable, but
540 * extended_extended_level is set to 0 if unavailable
541 * and the legitimate extended levels are all negative
542 * when signed; hence the weird messing around with
545 if (!((s32
)df
->level
< 0 ?
546 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
547 (s32
)df
->level
> (s32
)c
->cpuid_level
))
550 clear_cpu_cap(c
, df
->feature
);
554 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
555 x86_cap_flag(df
->feature
), df
->level
);
560 * Naming convention should be: <Name> [(<Codename>)]
561 * This table only is used unless init_<vendor>() below doesn't set it;
562 * in particular, if CPUID levels 0x80000002..4 are supported, this
566 /* Look up CPU names by table lookup. */
567 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
570 const struct legacy_cpu_model_info
*info
;
572 if (c
->x86_model
>= 16)
573 return NULL
; /* Range check */
578 info
= this_cpu
->legacy_models
;
580 while (info
->family
) {
581 if (info
->family
== c
->x86
)
582 return info
->model_names
[c
->x86_model
];
586 return NULL
; /* Not found */
589 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
590 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
591 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
593 void load_percpu_segment(int cpu
)
596 loadsegment(fs
, __KERNEL_PERCPU
);
598 __loadsegment_simple(gs
, 0);
599 wrmsrl(MSR_GS_BASE
, cpu_kernelmode_gs_base(cpu
));
601 load_stack_canary_segment();
605 /* The 32-bit entry code needs to find cpu_entry_area. */
606 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
609 /* Load the original GDT from the per-cpu structure */
610 void load_direct_gdt(int cpu
)
612 struct desc_ptr gdt_descr
;
614 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
615 gdt_descr
.size
= GDT_SIZE
- 1;
616 load_gdt(&gdt_descr
);
618 EXPORT_SYMBOL_GPL(load_direct_gdt
);
620 /* Load a fixmap remapping of the per-cpu GDT */
621 void load_fixmap_gdt(int cpu
)
623 struct desc_ptr gdt_descr
;
625 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
626 gdt_descr
.size
= GDT_SIZE
- 1;
627 load_gdt(&gdt_descr
);
629 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
632 * Current gdt points %fs at the "master" per-cpu area: after this,
633 * it's on the real one.
635 void switch_to_new_gdt(int cpu
)
637 /* Load the original GDT */
638 load_direct_gdt(cpu
);
639 /* Reload the per-cpu base */
640 load_percpu_segment(cpu
);
643 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
645 static void get_model_name(struct cpuinfo_x86
*c
)
650 if (c
->extended_cpuid_level
< 0x80000004)
653 v
= (unsigned int *)c
->x86_model_id
;
654 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
655 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
656 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
657 c
->x86_model_id
[48] = 0;
659 /* Trim whitespace */
660 p
= q
= s
= &c
->x86_model_id
[0];
666 /* Note the last non-whitespace index */
676 void detect_num_cpu_cores(struct cpuinfo_x86
*c
)
678 unsigned int eax
, ebx
, ecx
, edx
;
680 c
->x86_max_cores
= 1;
681 if (!IS_ENABLED(CONFIG_SMP
) || c
->cpuid_level
< 4)
684 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
686 c
->x86_max_cores
= (eax
>> 26) + 1;
689 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
691 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
693 n
= c
->extended_cpuid_level
;
695 if (n
>= 0x80000005) {
696 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
697 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
699 /* On K8 L1 TLB is inclusive, so don't count it */
704 if (n
< 0x80000006) /* Some chips just has a large L1. */
707 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
711 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
713 /* do processor-specific cache resizing */
714 if (this_cpu
->legacy_cache_size
)
715 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
717 /* Allow user to override all this if necessary. */
718 if (cachesize_override
!= -1)
719 l2size
= cachesize_override
;
722 return; /* Again, no L2 cache is possible */
725 c
->x86_cache_size
= l2size
;
728 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
729 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
730 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
731 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
732 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
733 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
734 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
736 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
738 if (this_cpu
->c_detect_tlb
)
739 this_cpu
->c_detect_tlb(c
);
741 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
742 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
743 tlb_lli_4m
[ENTRIES
]);
745 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
746 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
747 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
750 int detect_ht_early(struct cpuinfo_x86
*c
)
753 u32 eax
, ebx
, ecx
, edx
;
755 if (!cpu_has(c
, X86_FEATURE_HT
))
758 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
761 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
764 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
766 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
767 if (smp_num_siblings
== 1)
768 pr_info_once("CPU0: Hyper-Threading is disabled\n");
773 void detect_ht(struct cpuinfo_x86
*c
)
776 int index_msb
, core_bits
;
778 if (detect_ht_early(c
) < 0)
781 index_msb
= get_count_order(smp_num_siblings
);
782 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
784 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
786 index_msb
= get_count_order(smp_num_siblings
);
788 core_bits
= get_count_order(c
->x86_max_cores
);
790 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
791 ((1 << core_bits
) - 1);
795 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
797 char *v
= c
->x86_vendor_id
;
800 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
804 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
805 (cpu_devs
[i
]->c_ident
[1] &&
806 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
808 this_cpu
= cpu_devs
[i
];
809 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
814 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
815 "CPU: Your system may be unstable.\n", v
);
817 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
818 this_cpu
= &default_cpu
;
821 void cpu_detect(struct cpuinfo_x86
*c
)
823 /* Get vendor name */
824 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
825 (unsigned int *)&c
->x86_vendor_id
[0],
826 (unsigned int *)&c
->x86_vendor_id
[8],
827 (unsigned int *)&c
->x86_vendor_id
[4]);
830 /* Intel-defined flags: level 0x00000001 */
831 if (c
->cpuid_level
>= 0x00000001) {
832 u32 junk
, tfms
, cap0
, misc
;
834 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
835 c
->x86
= x86_family(tfms
);
836 c
->x86_model
= x86_model(tfms
);
837 c
->x86_stepping
= x86_stepping(tfms
);
839 if (cap0
& (1<<19)) {
840 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
841 c
->x86_cache_alignment
= c
->x86_clflush_size
;
846 static void apply_forced_caps(struct cpuinfo_x86
*c
)
850 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
851 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
852 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
856 static void init_speculation_control(struct cpuinfo_x86
*c
)
859 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
860 * and they also have a different bit for STIBP support. Also,
861 * a hypervisor might have set the individual AMD bits even on
862 * Intel CPUs, for finer-grained selection of what's available.
864 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
865 set_cpu_cap(c
, X86_FEATURE_IBRS
);
866 set_cpu_cap(c
, X86_FEATURE_IBPB
);
867 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
870 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
871 set_cpu_cap(c
, X86_FEATURE_STIBP
);
873 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
874 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
875 set_cpu_cap(c
, X86_FEATURE_SSBD
);
877 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
878 set_cpu_cap(c
, X86_FEATURE_IBRS
);
879 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
882 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
883 set_cpu_cap(c
, X86_FEATURE_IBPB
);
885 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
886 set_cpu_cap(c
, X86_FEATURE_STIBP
);
887 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
890 if (cpu_has(c
, X86_FEATURE_AMD_SSBD
)) {
891 set_cpu_cap(c
, X86_FEATURE_SSBD
);
892 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
893 clear_cpu_cap(c
, X86_FEATURE_VIRT_SSBD
);
897 void get_cpu_cap(struct cpuinfo_x86
*c
)
899 u32 eax
, ebx
, ecx
, edx
;
901 /* Intel-defined flags: level 0x00000001 */
902 if (c
->cpuid_level
>= 0x00000001) {
903 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
905 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
906 c
->x86_capability
[CPUID_1_EDX
] = edx
;
909 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
910 if (c
->cpuid_level
>= 0x00000006)
911 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
913 /* Additional Intel-defined flags: level 0x00000007 */
914 if (c
->cpuid_level
>= 0x00000007) {
915 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
916 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
917 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
918 c
->x86_capability
[CPUID_7_EDX
] = edx
;
920 /* Check valid sub-leaf index before accessing it */
922 cpuid_count(0x00000007, 1, &eax
, &ebx
, &ecx
, &edx
);
923 c
->x86_capability
[CPUID_7_1_EAX
] = eax
;
927 /* Extended state features: level 0x0000000d */
928 if (c
->cpuid_level
>= 0x0000000d) {
929 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
931 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
934 /* AMD-defined flags: level 0x80000001 */
935 eax
= cpuid_eax(0x80000000);
936 c
->extended_cpuid_level
= eax
;
938 if ((eax
& 0xffff0000) == 0x80000000) {
939 if (eax
>= 0x80000001) {
940 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
942 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
943 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
947 if (c
->extended_cpuid_level
>= 0x80000007) {
948 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
950 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
954 if (c
->extended_cpuid_level
>= 0x80000008) {
955 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
956 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
959 if (c
->extended_cpuid_level
>= 0x8000000a)
960 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
962 init_scattered_cpuid_features(c
);
963 init_speculation_control(c
);
966 * Clear/Set all flags overridden by options, after probe.
967 * This needs to happen each time we re-probe, which may happen
968 * several times during CPU initialization.
970 apply_forced_caps(c
);
973 void get_cpu_address_sizes(struct cpuinfo_x86
*c
)
975 u32 eax
, ebx
, ecx
, edx
;
977 if (c
->extended_cpuid_level
>= 0x80000008) {
978 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
980 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
981 c
->x86_phys_bits
= eax
& 0xff;
984 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
985 c
->x86_phys_bits
= 36;
987 c
->x86_cache_bits
= c
->x86_phys_bits
;
990 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
996 * First of all, decide if this is a 486 or higher
997 * It's a 486 if we can modify the AC flag
999 if (flag_is_changeable_p(X86_EFLAGS_AC
))
1004 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
1005 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
1006 c
->x86_vendor_id
[0] = 0;
1007 cpu_devs
[i
]->c_identify(c
);
1008 if (c
->x86_vendor_id
[0]) {
1016 #define NO_SPECULATION BIT(0)
1017 #define NO_MELTDOWN BIT(1)
1018 #define NO_SSB BIT(2)
1019 #define NO_L1TF BIT(3)
1020 #define NO_MDS BIT(4)
1021 #define MSBDS_ONLY BIT(5)
1022 #define NO_SWAPGS BIT(6)
1023 #define NO_ITLB_MULTIHIT BIT(7)
1024 #define NO_SPECTRE_V2 BIT(8)
1026 #define VULNWL(vendor, family, model, whitelist) \
1027 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1029 #define VULNWL_INTEL(model, whitelist) \
1030 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1032 #define VULNWL_AMD(family, whitelist) \
1033 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1035 #define VULNWL_HYGON(family, whitelist) \
1036 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1038 static const __initconst
struct x86_cpu_id cpu_vuln_whitelist
[] = {
1039 VULNWL(ANY
, 4, X86_MODEL_ANY
, NO_SPECULATION
),
1040 VULNWL(CENTAUR
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1041 VULNWL(INTEL
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1042 VULNWL(NSC
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1044 /* Intel Family 6 */
1045 VULNWL_INTEL(ATOM_SALTWELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1046 VULNWL_INTEL(ATOM_SALTWELL_TABLET
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1047 VULNWL_INTEL(ATOM_SALTWELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1048 VULNWL_INTEL(ATOM_BONNELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1049 VULNWL_INTEL(ATOM_BONNELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1051 VULNWL_INTEL(ATOM_SILVERMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1052 VULNWL_INTEL(ATOM_SILVERMONT_D
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1053 VULNWL_INTEL(ATOM_SILVERMONT_MID
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1054 VULNWL_INTEL(ATOM_AIRMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1055 VULNWL_INTEL(XEON_PHI_KNL
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1056 VULNWL_INTEL(XEON_PHI_KNM
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1058 VULNWL_INTEL(CORE_YONAH
, NO_SSB
),
1060 VULNWL_INTEL(ATOM_AIRMONT_MID
, NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1061 VULNWL_INTEL(ATOM_AIRMONT_NP
, NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1063 VULNWL_INTEL(ATOM_GOLDMONT
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1064 VULNWL_INTEL(ATOM_GOLDMONT_D
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1065 VULNWL_INTEL(ATOM_GOLDMONT_PLUS
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1068 * Technically, swapgs isn't serializing on AMD (despite it previously
1069 * being documented as such in the APM). But according to AMD, %gs is
1070 * updated non-speculatively, and the issuing of %gs-relative memory
1071 * operands will be blocked until the %gs update completes, which is
1072 * good enough for our purposes.
1075 VULNWL_INTEL(ATOM_TREMONT_D
, NO_ITLB_MULTIHIT
),
1077 /* AMD Family 0xf - 0x12 */
1078 VULNWL_AMD(0x0f, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1079 VULNWL_AMD(0x10, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1080 VULNWL_AMD(0x11, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1081 VULNWL_AMD(0x12, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1083 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1084 VULNWL_AMD(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1085 VULNWL_HYGON(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1087 /* Zhaoxin Family 7 */
1088 VULNWL(CENTAUR
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
),
1089 VULNWL(ZHAOXIN
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
),
1093 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1094 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1095 INTEL_FAM6_##model, steppings, \
1096 X86_FEATURE_ANY, issues)
1098 #define SRBDS BIT(0)
1100 static const struct x86_cpu_id cpu_vuln_blacklist
[] __initconst
= {
1101 VULNBL_INTEL_STEPPINGS(IVYBRIDGE
, X86_STEPPING_ANY
, SRBDS
),
1102 VULNBL_INTEL_STEPPINGS(HASWELL
, X86_STEPPING_ANY
, SRBDS
),
1103 VULNBL_INTEL_STEPPINGS(HASWELL_L
, X86_STEPPING_ANY
, SRBDS
),
1104 VULNBL_INTEL_STEPPINGS(HASWELL_G
, X86_STEPPING_ANY
, SRBDS
),
1105 VULNBL_INTEL_STEPPINGS(BROADWELL_G
, X86_STEPPING_ANY
, SRBDS
),
1106 VULNBL_INTEL_STEPPINGS(BROADWELL
, X86_STEPPING_ANY
, SRBDS
),
1107 VULNBL_INTEL_STEPPINGS(SKYLAKE_L
, X86_STEPPING_ANY
, SRBDS
),
1108 VULNBL_INTEL_STEPPINGS(SKYLAKE
, X86_STEPPING_ANY
, SRBDS
),
1109 VULNBL_INTEL_STEPPINGS(KABYLAKE_L
, X86_STEPPINGS(0x0, 0xC), SRBDS
),
1110 VULNBL_INTEL_STEPPINGS(KABYLAKE
, X86_STEPPINGS(0x0, 0xD), SRBDS
),
1114 static bool __init
cpu_matches(const struct x86_cpu_id
*table
, unsigned long which
)
1116 const struct x86_cpu_id
*m
= x86_match_cpu(table
);
1118 return m
&& !!(m
->driver_data
& which
);
1121 u64
x86_read_arch_cap_msr(void)
1125 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
1126 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
1131 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
1133 u64 ia32_cap
= x86_read_arch_cap_msr();
1135 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1136 if (!cpu_matches(cpu_vuln_whitelist
, NO_ITLB_MULTIHIT
) &&
1137 !(ia32_cap
& ARCH_CAP_PSCHANGE_MC_NO
))
1138 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT
);
1140 if (cpu_matches(cpu_vuln_whitelist
, NO_SPECULATION
))
1143 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
1145 if (!cpu_matches(cpu_vuln_whitelist
, NO_SPECTRE_V2
))
1146 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
1148 if (!cpu_matches(cpu_vuln_whitelist
, NO_SSB
) &&
1149 !(ia32_cap
& ARCH_CAP_SSB_NO
) &&
1150 !cpu_has(c
, X86_FEATURE_AMD_SSB_NO
))
1151 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
1153 if (ia32_cap
& ARCH_CAP_IBRS_ALL
)
1154 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED
);
1156 if (!cpu_matches(cpu_vuln_whitelist
, NO_MDS
) &&
1157 !(ia32_cap
& ARCH_CAP_MDS_NO
)) {
1158 setup_force_cpu_bug(X86_BUG_MDS
);
1159 if (cpu_matches(cpu_vuln_whitelist
, MSBDS_ONLY
))
1160 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY
);
1163 if (!cpu_matches(cpu_vuln_whitelist
, NO_SWAPGS
))
1164 setup_force_cpu_bug(X86_BUG_SWAPGS
);
1167 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1168 * - TSX is supported or
1169 * - TSX_CTRL is present
1171 * TSX_CTRL check is needed for cases when TSX could be disabled before
1172 * the kernel boot e.g. kexec.
1173 * TSX_CTRL check alone is not sufficient for cases when the microcode
1174 * update is not present or running as guest that don't get TSX_CTRL.
1176 if (!(ia32_cap
& ARCH_CAP_TAA_NO
) &&
1177 (cpu_has(c
, X86_FEATURE_RTM
) ||
1178 (ia32_cap
& ARCH_CAP_TSX_CTRL_MSR
)))
1179 setup_force_cpu_bug(X86_BUG_TAA
);
1182 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1183 * in the vulnerability blacklist.
1185 if ((cpu_has(c
, X86_FEATURE_RDRAND
) ||
1186 cpu_has(c
, X86_FEATURE_RDSEED
)) &&
1187 cpu_matches(cpu_vuln_blacklist
, SRBDS
))
1188 setup_force_cpu_bug(X86_BUG_SRBDS
);
1190 if (cpu_matches(cpu_vuln_whitelist
, NO_MELTDOWN
))
1193 /* Rogue Data Cache Load? No! */
1194 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
1197 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
1199 if (cpu_matches(cpu_vuln_whitelist
, NO_L1TF
))
1202 setup_force_cpu_bug(X86_BUG_L1TF
);
1206 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1207 * unfortunately, that's not true in practice because of early VIA
1208 * chips and (more importantly) broken virtualizers that are not easy
1209 * to detect. In the latter case it doesn't even *fail* reliably, so
1210 * probing for it doesn't even work. Disable it completely on 32-bit
1211 * unless we can find a reliable way to detect all the broken cases.
1212 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1214 static void detect_nopl(void)
1216 #ifdef CONFIG_X86_32
1217 setup_clear_cpu_cap(X86_FEATURE_NOPL
);
1219 setup_force_cpu_cap(X86_FEATURE_NOPL
);
1224 * Do minimum CPU detection early.
1225 * Fields really needed: vendor, cpuid_level, family, model, mask,
1227 * The others are not touched to avoid unwanted side effects.
1229 * WARNING: this function is only called on the boot CPU. Don't add code
1230 * here that is supposed to run on all CPUs.
1232 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
1234 #ifdef CONFIG_X86_64
1235 c
->x86_clflush_size
= 64;
1236 c
->x86_phys_bits
= 36;
1237 c
->x86_virt_bits
= 48;
1239 c
->x86_clflush_size
= 32;
1240 c
->x86_phys_bits
= 32;
1241 c
->x86_virt_bits
= 32;
1243 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1245 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1246 c
->extended_cpuid_level
= 0;
1248 if (!have_cpuid_p())
1249 identify_cpu_without_cpuid(c
);
1251 /* cyrix could have cpuid enabled via c_identify()*/
1252 if (have_cpuid_p()) {
1256 get_cpu_address_sizes(c
);
1257 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1259 if (this_cpu
->c_early_init
)
1260 this_cpu
->c_early_init(c
);
1263 filter_cpuid_features(c
, false);
1265 if (this_cpu
->c_bsp_init
)
1266 this_cpu
->c_bsp_init(c
);
1268 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1271 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1273 cpu_set_bug_bits(c
);
1275 cpu_set_core_cap_bits(c
);
1277 fpu__init_system(c
);
1279 #ifdef CONFIG_X86_32
1281 * Regardless of whether PCID is enumerated, the SDM says
1282 * that it can't be enabled in 32-bit mode.
1284 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1288 * Later in the boot process pgtable_l5_enabled() relies on
1289 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1290 * enabled by this point we need to clear the feature bit to avoid
1291 * false-positives at the later stage.
1293 * pgtable_l5_enabled() can be false here for several reasons:
1294 * - 5-level paging is disabled compile-time;
1295 * - it's 32-bit kernel;
1296 * - machine doesn't support 5-level paging;
1297 * - user specified 'no5lvl' in kernel command line.
1299 if (!pgtable_l5_enabled())
1300 setup_clear_cpu_cap(X86_FEATURE_LA57
);
1305 void __init
early_cpu_init(void)
1307 const struct cpu_dev
*const *cdev
;
1310 #ifdef CONFIG_PROCESSOR_SELECT
1311 pr_info("KERNEL supported cpus:\n");
1314 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1315 const struct cpu_dev
*cpudev
= *cdev
;
1317 if (count
>= X86_VENDOR_NUM
)
1319 cpu_devs
[count
] = cpudev
;
1322 #ifdef CONFIG_PROCESSOR_SELECT
1326 for (j
= 0; j
< 2; j
++) {
1327 if (!cpudev
->c_ident
[j
])
1329 pr_info(" %s %s\n", cpudev
->c_vendor
,
1330 cpudev
->c_ident
[j
]);
1335 early_identify_cpu(&boot_cpu_data
);
1338 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
1340 #ifdef CONFIG_X86_64
1342 * Empirically, writing zero to a segment selector on AMD does
1343 * not clear the base, whereas writing zero to a segment
1344 * selector on Intel does clear the base. Intel's behavior
1345 * allows slightly faster context switches in the common case
1346 * where GS is unused by the prev and next threads.
1348 * Since neither vendor documents this anywhere that I can see,
1349 * detect it directly instead of hardcoding the choice by
1352 * I've designated AMD's behavior as the "bug" because it's
1353 * counterintuitive and less friendly.
1356 unsigned long old_base
, tmp
;
1357 rdmsrl(MSR_FS_BASE
, old_base
);
1358 wrmsrl(MSR_FS_BASE
, 1);
1360 rdmsrl(MSR_FS_BASE
, tmp
);
1362 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1363 wrmsrl(MSR_FS_BASE
, old_base
);
1367 static void generic_identify(struct cpuinfo_x86
*c
)
1369 c
->extended_cpuid_level
= 0;
1371 if (!have_cpuid_p())
1372 identify_cpu_without_cpuid(c
);
1374 /* cyrix could have cpuid enabled via c_identify()*/
1375 if (!have_cpuid_p())
1384 get_cpu_address_sizes(c
);
1386 if (c
->cpuid_level
>= 0x00000001) {
1387 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1388 #ifdef CONFIG_X86_32
1390 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1392 c
->apicid
= c
->initial_apicid
;
1395 c
->phys_proc_id
= c
->initial_apicid
;
1398 get_model_name(c
); /* Default name */
1400 detect_null_seg_behavior(c
);
1403 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1404 * systems that run Linux at CPL > 0 may or may not have the
1405 * issue, but, even if they have the issue, there's absolutely
1406 * nothing we can do about it because we can't use the real IRET
1409 * NB: For the time being, only 32-bit kernels support
1410 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1411 * whether to apply espfix using paravirt hooks. If any
1412 * non-paravirt system ever shows up that does *not* have the
1413 * ESPFIX issue, we can change this.
1415 #ifdef CONFIG_X86_32
1416 # ifdef CONFIG_PARAVIRT_XXL
1418 extern void native_iret(void);
1419 if (pv_ops
.cpu
.iret
== native_iret
)
1420 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1423 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1429 * Validate that ACPI/mptables have the same information about the
1430 * effective APIC id and update the package map.
1432 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1435 unsigned int apicid
, cpu
= smp_processor_id();
1437 apicid
= apic
->cpu_present_to_apicid(cpu
);
1439 if (apicid
!= c
->apicid
) {
1440 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1441 cpu
, apicid
, c
->initial_apicid
);
1443 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1444 BUG_ON(topology_update_die_map(c
->cpu_die_id
, cpu
));
1446 c
->logical_proc_id
= 0;
1451 * This does the hard work of actually picking apart the CPU stuff...
1453 static void identify_cpu(struct cpuinfo_x86
*c
)
1457 c
->loops_per_jiffy
= loops_per_jiffy
;
1458 c
->x86_cache_size
= 0;
1459 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1460 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1461 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1462 c
->x86_model_id
[0] = '\0'; /* Unset */
1463 c
->x86_max_cores
= 1;
1464 c
->x86_coreid_bits
= 0;
1466 #ifdef CONFIG_X86_64
1467 c
->x86_clflush_size
= 64;
1468 c
->x86_phys_bits
= 36;
1469 c
->x86_virt_bits
= 48;
1471 c
->cpuid_level
= -1; /* CPUID not detected */
1472 c
->x86_clflush_size
= 32;
1473 c
->x86_phys_bits
= 32;
1474 c
->x86_virt_bits
= 32;
1476 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1477 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1478 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1479 memset(&c
->vmx_capability
, 0, sizeof(c
->vmx_capability
));
1482 generic_identify(c
);
1484 if (this_cpu
->c_identify
)
1485 this_cpu
->c_identify(c
);
1487 /* Clear/Set all flags overridden by options, after probe */
1488 apply_forced_caps(c
);
1490 #ifdef CONFIG_X86_64
1491 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1495 * Vendor-specific initialization. In this section we
1496 * canonicalize the feature flags, meaning if there are
1497 * features a certain CPU supports which CPUID doesn't
1498 * tell us, CPUID claiming incorrect flags, or other bugs,
1499 * we handle them here.
1501 * At the end of this section, c->x86_capability better
1502 * indicate the features this CPU genuinely supports!
1504 if (this_cpu
->c_init
)
1505 this_cpu
->c_init(c
);
1507 /* Disable the PN if appropriate */
1508 squash_the_stupid_serial_number(c
);
1510 /* Set up SMEP/SMAP/UMIP */
1515 /* Enable FSGSBASE instructions if available. */
1516 if (cpu_has(c
, X86_FEATURE_FSGSBASE
)) {
1517 cr4_set_bits(X86_CR4_FSGSBASE
);
1518 elf_hwcap2
|= HWCAP2_FSGSBASE
;
1522 * The vendor-specific functions might have changed features.
1523 * Now we do "generic changes."
1526 /* Filter out anything that depends on CPUID levels we don't have */
1527 filter_cpuid_features(c
, true);
1529 /* If the model name is still unset, do table lookup. */
1530 if (!c
->x86_model_id
[0]) {
1532 p
= table_lookup_model(c
);
1534 strcpy(c
->x86_model_id
, p
);
1536 /* Last resort... */
1537 sprintf(c
->x86_model_id
, "%02x/%02x",
1538 c
->x86
, c
->x86_model
);
1541 #ifdef CONFIG_X86_64
1549 * Clear/Set all flags overridden by options, need do it
1550 * before following smp all cpus cap AND.
1552 apply_forced_caps(c
);
1555 * On SMP, boot_cpu_data holds the common feature set between
1556 * all CPUs; so make sure that we indicate which features are
1557 * common between the CPUs. The first time this routine gets
1558 * executed, c == &boot_cpu_data.
1560 if (c
!= &boot_cpu_data
) {
1561 /* AND the already accumulated flags with these */
1562 for (i
= 0; i
< NCAPINTS
; i
++)
1563 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1565 /* OR, i.e. replicate the bug flags */
1566 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1567 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1570 /* Init Machine Check Exception if available. */
1573 select_idle_routine(c
);
1576 numa_add_cpu(smp_processor_id());
1581 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1582 * on 32-bit kernels:
1584 #ifdef CONFIG_X86_32
1585 void enable_sep_cpu(void)
1587 struct tss_struct
*tss
;
1590 if (!boot_cpu_has(X86_FEATURE_SEP
))
1594 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1597 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1598 * see the big comment in struct x86_hw_tss's definition.
1601 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1602 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1603 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1604 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1610 void __init
identify_boot_cpu(void)
1612 identify_cpu(&boot_cpu_data
);
1613 #ifdef CONFIG_X86_32
1617 cpu_detect_tlb(&boot_cpu_data
);
1623 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1625 BUG_ON(c
== &boot_cpu_data
);
1627 #ifdef CONFIG_X86_32
1631 validate_apic_and_package_id(c
);
1632 x86_spec_ctrl_setup_ap();
1636 static __init
int setup_noclflush(char *arg
)
1638 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1639 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1642 __setup("noclflush", setup_noclflush
);
1644 void print_cpu_info(struct cpuinfo_x86
*c
)
1646 const char *vendor
= NULL
;
1648 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1649 vendor
= this_cpu
->c_vendor
;
1651 if (c
->cpuid_level
>= 0)
1652 vendor
= c
->x86_vendor_id
;
1655 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1656 pr_cont("%s ", vendor
);
1658 if (c
->x86_model_id
[0])
1659 pr_cont("%s", c
->x86_model_id
);
1661 pr_cont("%d86", c
->x86
);
1663 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1665 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
1666 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
1672 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1673 * But we need to keep a dummy __setup around otherwise it would
1674 * show up as an environment variable for init.
1676 static __init
int setup_clearcpuid(char *arg
)
1680 __setup("clearcpuid=", setup_clearcpuid
);
1682 #ifdef CONFIG_X86_64
1683 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data
,
1684 fixed_percpu_data
) __aligned(PAGE_SIZE
) __visible
;
1685 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data
);
1688 * The following percpu variables are hot. Align current_task to
1689 * cacheline size such that they fall in the same cacheline.
1691 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1693 EXPORT_PER_CPU_SYMBOL(current_task
);
1695 DEFINE_PER_CPU(struct irq_stack
*, hardirq_stack_ptr
);
1696 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1698 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1699 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1701 /* May not be marked __init: used by software suspend */
1702 void syscall_init(void)
1704 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1705 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1707 #ifdef CONFIG_IA32_EMULATION
1708 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1710 * This only works on Intel CPUs.
1711 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1712 * This does not cause SYSENTER to jump to the wrong location, because
1713 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1715 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1716 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
,
1717 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1718 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1720 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1721 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1722 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1723 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1726 /* Flags to clear on syscall */
1727 wrmsrl(MSR_SYSCALL_MASK
,
1728 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1729 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1732 #else /* CONFIG_X86_64 */
1734 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1735 EXPORT_PER_CPU_SYMBOL(current_task
);
1736 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1737 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1740 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1741 * the top of the kernel stack. Use an extra percpu variable to track the
1742 * top of the kernel stack directly.
1744 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1745 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1746 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1748 #ifdef CONFIG_STACKPROTECTOR
1749 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1752 #endif /* CONFIG_X86_64 */
1755 * Clear all 6 debug registers:
1757 static void clear_all_debug_regs(void)
1761 for (i
= 0; i
< 8; i
++) {
1762 /* Ignore db4, db5 */
1763 if ((i
== 4) || (i
== 5))
1772 * Restore debug regs if using kgdbwait and you have a kernel debugger
1773 * connection established.
1775 static void dbg_restore_debug_regs(void)
1777 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1778 arch_kgdb_ops
.correct_hw_break();
1780 #else /* ! CONFIG_KGDB */
1781 #define dbg_restore_debug_regs()
1782 #endif /* ! CONFIG_KGDB */
1784 static void wait_for_master_cpu(int cpu
)
1788 * wait for ACK from master CPU before continuing
1789 * with AP initialization
1791 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1792 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1797 #ifdef CONFIG_X86_64
1798 static inline void setup_getcpu(int cpu
)
1800 unsigned long cpudata
= vdso_encode_cpunode(cpu
, early_cpu_to_node(cpu
));
1801 struct desc_struct d
= { };
1803 if (boot_cpu_has(X86_FEATURE_RDTSCP
))
1804 write_rdtscp_aux(cpudata
);
1806 /* Store CPU and node number in limit. */
1808 d
.limit1
= cpudata
>> 16;
1810 d
.type
= 5; /* RO data, expand down, accessed */
1811 d
.dpl
= 3; /* Visible to user code */
1812 d
.s
= 1; /* Not a system segment */
1813 d
.p
= 1; /* Present */
1814 d
.d
= 1; /* 32-bit */
1816 write_gdt_entry(get_cpu_gdt_rw(cpu
), GDT_ENTRY_CPUNODE
, &d
, DESCTYPE_S
);
1819 static inline void ucode_cpu_init(int cpu
)
1825 static inline void tss_setup_ist(struct tss_struct
*tss
)
1827 /* Set up the per-CPU TSS IST stacks */
1828 tss
->x86_tss
.ist
[IST_INDEX_DF
] = __this_cpu_ist_top_va(DF
);
1829 tss
->x86_tss
.ist
[IST_INDEX_NMI
] = __this_cpu_ist_top_va(NMI
);
1830 tss
->x86_tss
.ist
[IST_INDEX_DB
] = __this_cpu_ist_top_va(DB
);
1831 tss
->x86_tss
.ist
[IST_INDEX_MCE
] = __this_cpu_ist_top_va(MCE
);
1832 /* Only mapped when SEV-ES is active */
1833 tss
->x86_tss
.ist
[IST_INDEX_VC
] = __this_cpu_ist_top_va(VC
);
1836 #else /* CONFIG_X86_64 */
1838 static inline void setup_getcpu(int cpu
) { }
1840 static inline void ucode_cpu_init(int cpu
)
1842 show_ucode_info_early();
1845 static inline void tss_setup_ist(struct tss_struct
*tss
) { }
1847 #endif /* !CONFIG_X86_64 */
1849 static inline void tss_setup_io_bitmap(struct tss_struct
*tss
)
1851 tss
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET_INVALID
;
1853 #ifdef CONFIG_X86_IOPL_IOPERM
1854 tss
->io_bitmap
.prev_max
= 0;
1855 tss
->io_bitmap
.prev_sequence
= 0;
1856 memset(tss
->io_bitmap
.bitmap
, 0xff, sizeof(tss
->io_bitmap
.bitmap
));
1858 * Invalidate the extra array entry past the end of the all
1859 * permission bitmap as required by the hardware.
1861 tss
->io_bitmap
.mapall
[IO_BITMAP_LONGS
] = ~0UL;
1866 * cpu_init() initializes state that is per-CPU. Some data is already
1867 * initialized (naturally) in the bootstrap process, such as the GDT
1868 * and IDT. We reload them nevertheless, this function acts as a
1869 * 'CPU state barrier', nothing should get across.
1873 struct tss_struct
*tss
= this_cpu_ptr(&cpu_tss_rw
);
1874 struct task_struct
*cur
= current
;
1875 int cpu
= raw_smp_processor_id();
1877 wait_for_master_cpu(cpu
);
1879 ucode_cpu_init(cpu
);
1882 if (this_cpu_read(numa_node
) == 0 &&
1883 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1884 set_numa_node(early_cpu_to_node(cpu
));
1888 pr_debug("Initializing CPU#%d\n", cpu
);
1890 if (IS_ENABLED(CONFIG_X86_64
) || cpu_feature_enabled(X86_FEATURE_VME
) ||
1891 boot_cpu_has(X86_FEATURE_TSC
) || boot_cpu_has(X86_FEATURE_DE
))
1892 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1895 * Initialize the per-CPU GDT with the boot GDT,
1896 * and set up the GDT descriptor:
1898 switch_to_new_gdt(cpu
);
1901 if (IS_ENABLED(CONFIG_X86_64
)) {
1903 memset(cur
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1906 wrmsrl(MSR_FS_BASE
, 0);
1907 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1914 cur
->active_mm
= &init_mm
;
1916 initialize_tlbstate_and_flush();
1917 enter_lazy_tlb(&init_mm
, cur
);
1919 /* Initialize the TSS. */
1921 tss_setup_io_bitmap(tss
);
1922 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1926 * sp0 points to the entry trampoline stack regardless of what task
1929 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
1931 load_mm_ldt(&init_mm
);
1933 clear_all_debug_regs();
1934 dbg_restore_debug_regs();
1936 doublefault_init_cpu_tss();
1943 load_fixmap_gdt(cpu
);
1947 * The microcode loader calls this upon late microcode load to recheck features,
1948 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1951 void microcode_check(void)
1953 struct cpuinfo_x86 info
;
1955 perf_check_microcode();
1957 /* Reload CPUID max function as it might've changed. */
1958 info
.cpuid_level
= cpuid_eax(0);
1961 * Copy all capability leafs to pick up the synthetic ones so that
1962 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1963 * get overwritten in get_cpu_cap().
1965 memcpy(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
));
1969 if (!memcmp(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
)))
1972 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1973 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1977 * Invoked from core CPU hotplug code after hotplug operations
1979 void arch_smt_update(void)
1981 /* Handle the speculative execution misfeatures */
1982 cpu_bugs_smt_update();
1983 /* Check whether IPI broadcasting can be enabled */