1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/processor.h>
12 #include <asm/mmu_context.h>
17 #ifdef CONFIG_X86_LOCAL_APIC
18 #include <asm/mpspec.h>
20 #include <mach_apic.h>
25 static struct cpu_dev
*this_cpu __cpuinitdata
;
27 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
28 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
29 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
30 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
31 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
33 * Segments used for calling PnP BIOS have byte granularity.
34 * They code segments and data segments have fixed 64k limits,
35 * the transfer segment sizes are set at run time.
38 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
40 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
42 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
44 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
46 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
48 * The APM segments have byte granularity and their bases
49 * are set at run time. All have 64k limits.
52 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
54 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
56 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
58 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
59 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
61 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
63 static int cachesize_override __cpuinitdata
= -1;
64 static int disable_x86_serial_nr __cpuinitdata
= 1;
66 static int __init
cachesize_setup(char *str
)
68 get_option(&str
, &cachesize_override
);
71 __setup("cachesize=", cachesize_setup
);
74 * Naming convention should be: <Name> [(<Codename>)]
75 * This table only is used unless init_<vendor>() below doesn't set it;
76 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
80 /* Look up CPU names by table lookup. */
81 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
83 struct cpu_model_info
*info
;
85 if (c
->x86_model
>= 16)
86 return NULL
; /* Range check */
91 info
= this_cpu
->c_models
;
93 while (info
&& info
->family
) {
94 if (info
->family
== c
->x86
)
95 return info
->model_names
[c
->x86_model
];
98 return NULL
; /* Not found */
101 static int __init
x86_fxsr_setup(char *s
)
103 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
104 setup_clear_cpu_cap(X86_FEATURE_XMM
);
107 __setup("nofxsr", x86_fxsr_setup
);
109 static int __init
x86_sep_setup(char *s
)
111 setup_clear_cpu_cap(X86_FEATURE_SEP
);
114 __setup("nosep", x86_sep_setup
);
116 /* Standard macro to see if a specific flag is changeable */
117 static inline int flag_is_changeable_p(u32 flag
)
131 : "=&r" (f1
), "=&r" (f2
)
134 return ((f1
^f2
) & flag
) != 0;
137 /* Probe for the CPUID instruction */
138 static int __cpuinit
have_cpuid_p(void)
140 return flag_is_changeable_p(X86_EFLAGS_ID
);
143 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
145 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
146 /* Disable processor serial number */
147 unsigned long lo
, hi
;
148 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
150 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
151 printk(KERN_NOTICE
"CPU serial number disabled.\n");
152 clear_cpu_cap(c
, X86_FEATURE_PN
);
154 /* Disabling the serial number may affect the cpuid level */
155 c
->cpuid_level
= cpuid_eax(0);
159 static int __init
x86_serial_nr_setup(char *s
)
161 disable_x86_serial_nr
= 0;
164 __setup("serialnumber", x86_serial_nr_setup
);
166 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
168 /* Current gdt points %fs at the "master" per-cpu area: after this,
169 * it's on the real one. */
170 void switch_to_new_gdt(void)
172 struct desc_ptr gdt_descr
;
174 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
175 gdt_descr
.size
= GDT_SIZE
- 1;
176 load_gdt(&gdt_descr
);
177 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU
) : "memory");
180 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
182 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
184 /* Not much we can do here... */
185 /* Check if at least it has cpuid */
186 if (c
->cpuid_level
== -1) {
187 /* No cpuid. It must be an ancient CPU */
189 strcpy(c
->x86_model_id
, "486");
190 else if (c
->x86
== 3)
191 strcpy(c
->x86_model_id
, "386");
195 static struct cpu_dev __cpuinitdata default_cpu
= {
196 .c_init
= default_init
,
197 .c_vendor
= "Unknown",
198 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
201 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
206 if (c
->extended_cpuid_level
< 0x80000004)
209 v
= (unsigned int *) c
->x86_model_id
;
210 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
211 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
212 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
213 c
->x86_model_id
[48] = 0;
215 /* Intel chips right-justify this string for some dumb reason;
216 undo that brain damage */
217 p
= q
= &c
->x86_model_id
[0];
223 while (q
<= &c
->x86_model_id
[48])
224 *q
++ = '\0'; /* Zero-pad the rest */
230 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
232 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
234 n
= c
->extended_cpuid_level
;
236 if (n
>= 0x80000005) {
237 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
238 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
239 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
240 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
243 if (n
< 0x80000006) /* Some chips just has a large L1. */
246 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
249 /* do processor-specific cache resizing */
250 if (this_cpu
->c_size_cache
)
251 l2size
= this_cpu
->c_size_cache(c
, l2size
);
253 /* Allow user to override all this if necessary. */
254 if (cachesize_override
!= -1)
255 l2size
= cachesize_override
;
258 return; /* Again, no L2 cache is possible */
260 c
->x86_cache_size
= l2size
;
262 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
267 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
269 u32 eax
, ebx
, ecx
, edx
;
270 int index_msb
, core_bits
;
272 if (!cpu_has(c
, X86_FEATURE_HT
))
275 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
278 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
280 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
282 if (smp_num_siblings
== 1) {
283 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
284 } else if (smp_num_siblings
> 1) {
286 if (smp_num_siblings
> NR_CPUS
) {
287 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
289 smp_num_siblings
= 1;
293 index_msb
= get_count_order(smp_num_siblings
);
294 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
297 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
299 index_msb
= get_count_order(smp_num_siblings
);
301 core_bits
= get_count_order(c
->x86_max_cores
);
303 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
304 ((1 << core_bits
) - 1);
308 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
309 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
311 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
317 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
319 char *v
= c
->x86_vendor_id
;
323 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
327 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
328 (cpu_devs
[i
]->c_ident
[1] &&
329 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
330 this_cpu
= cpu_devs
[i
];
331 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
338 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
339 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
342 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
343 this_cpu
= &default_cpu
;
346 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
348 /* Get vendor name */
349 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
350 (unsigned int *)&c
->x86_vendor_id
[0],
351 (unsigned int *)&c
->x86_vendor_id
[8],
352 (unsigned int *)&c
->x86_vendor_id
[4]);
355 /* Intel-defined flags: level 0x00000001 */
356 if (c
->cpuid_level
>= 0x00000001) {
357 u32 junk
, tfms
, cap0
, misc
;
358 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
359 c
->x86
= (tfms
>> 8) & 0xf;
360 c
->x86_model
= (tfms
>> 4) & 0xf;
361 c
->x86_mask
= tfms
& 0xf;
363 c
->x86
+= (tfms
>> 20) & 0xff;
365 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
366 if (cap0
& (1<<19)) {
367 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
368 c
->x86_cache_alignment
= c
->x86_clflush_size
;
373 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
378 /* Intel-defined flags: level 0x00000001 */
379 if (c
->cpuid_level
>= 0x00000001) {
380 u32 capability
, excap
;
381 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
382 c
->x86_capability
[0] = capability
;
383 c
->x86_capability
[4] = excap
;
386 /* AMD-defined flags: level 0x80000001 */
387 xlvl
= cpuid_eax(0x80000000);
388 c
->extended_cpuid_level
= xlvl
;
389 if ((xlvl
& 0xffff0000) == 0x80000000) {
390 if (xlvl
>= 0x80000001) {
391 c
->x86_capability
[1] = cpuid_edx(0x80000001);
392 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
397 * Do minimum CPU detection early.
398 * Fields really needed: vendor, cpuid_level, family, model, mask,
400 * The others are not touched to avoid unwanted side effects.
402 * WARNING: this function is only called on the BP. Don't add code here
403 * that is supposed to run on all CPUs.
405 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
407 c
->x86_clflush_size
= 32;
408 c
->x86_cache_alignment
= c
->x86_clflush_size
;
413 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
415 c
->extended_cpuid_level
= 0;
423 if (this_cpu
->c_early_init
)
424 this_cpu
->c_early_init(c
);
426 validate_pat_support(c
);
429 void __init
early_cpu_init(void)
431 struct cpu_dev
**cdev
;
434 printk("KERNEL supported cpus:\n");
435 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
436 struct cpu_dev
*cpudev
= *cdev
;
439 if (count
>= X86_VENDOR_NUM
)
441 cpu_devs
[count
] = cpudev
;
444 for (j
= 0; j
< 2; j
++) {
445 if (!cpudev
->c_ident
[j
])
447 printk(" %s %s\n", cpudev
->c_vendor
,
452 early_identify_cpu(&boot_cpu_data
);
456 * The NOPL instruction is supposed to exist on all CPUs with
457 * family >= 6, unfortunately, that's not true in practice because
458 * of early VIA chips and (more importantly) broken virtualizers that
459 * are not easy to detect. Hence, probe for it based on first
462 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
464 const u32 nopl_signature
= 0x888c53b1; /* Random number */
465 u32 has_nopl
= nopl_signature
;
467 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
470 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
472 " .section .fixup,\"ax\"\n"
479 if (has_nopl
== nopl_signature
)
480 set_cpu_cap(c
, X86_FEATURE_NOPL
);
484 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
489 c
->extended_cpuid_level
= 0;
497 if (c
->cpuid_level
>= 0x00000001) {
498 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
500 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
501 c
->phys_proc_id
= c
->initial_apicid
;
503 c
->apicid
= c
->initial_apicid
;
507 if (c
->extended_cpuid_level
>= 0x80000004)
508 get_model_name(c
); /* Default name */
510 init_scattered_cpuid_features(c
);
515 * This does the hard work of actually picking apart the CPU stuff...
517 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
521 c
->loops_per_jiffy
= loops_per_jiffy
;
522 c
->x86_cache_size
= -1;
523 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
524 c
->cpuid_level
= -1; /* CPUID not detected */
525 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
526 c
->x86_vendor_id
[0] = '\0'; /* Unset */
527 c
->x86_model_id
[0] = '\0'; /* Unset */
528 c
->x86_max_cores
= 1;
529 c
->x86_clflush_size
= 32;
530 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
532 if (!have_cpuid_p()) {
534 * First of all, decide if this is a 486 or higher
535 * It's a 486 if we can modify the AC flag
537 if (flag_is_changeable_p(X86_EFLAGS_AC
))
545 if (this_cpu
->c_identify
)
546 this_cpu
->c_identify(c
);
549 * Vendor-specific initialization. In this section we
550 * canonicalize the feature flags, meaning if there are
551 * features a certain CPU supports which CPUID doesn't
552 * tell us, CPUID claiming incorrect flags, or other bugs,
553 * we handle them here.
555 * At the end of this section, c->x86_capability better
556 * indicate the features this CPU genuinely supports!
558 if (this_cpu
->c_init
)
561 /* Disable the PN if appropriate */
562 squash_the_stupid_serial_number(c
);
565 * The vendor-specific functions might have changed features. Now
566 * we do "generic changes."
569 /* If the model name is still unset, do table lookup. */
570 if (!c
->x86_model_id
[0]) {
572 p
= table_lookup_model(c
);
574 strcpy(c
->x86_model_id
, p
);
577 sprintf(c
->x86_model_id
, "%02x/%02x",
578 c
->x86
, c
->x86_model
);
582 * On SMP, boot_cpu_data holds the common feature set between
583 * all CPUs; so make sure that we indicate which features are
584 * common between the CPUs. The first time this routine gets
585 * executed, c == &boot_cpu_data.
587 if (c
!= &boot_cpu_data
) {
588 /* AND the already accumulated flags with these */
589 for (i
= 0; i
< NCAPINTS
; i
++)
590 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
593 /* Clear all flags overriden by options */
594 for (i
= 0; i
< NCAPINTS
; i
++)
595 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
597 /* Init Machine Check Exception if available. */
600 select_idle_routine(c
);
603 void __init
identify_boot_cpu(void)
605 identify_cpu(&boot_cpu_data
);
610 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
612 BUG_ON(c
== &boot_cpu_data
);
623 static struct msr_range msr_range_array
[] __cpuinitdata
= {
624 { 0x00000000, 0x00000418},
625 { 0xc0000000, 0xc000040b},
626 { 0xc0010000, 0xc0010142},
627 { 0xc0011000, 0xc001103b},
630 static void __cpuinit
print_cpu_msr(void)
635 unsigned index_min
, index_max
;
637 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
638 index_min
= msr_range_array
[i
].min
;
639 index_max
= msr_range_array
[i
].max
;
640 for (index
= index_min
; index
< index_max
; index
++) {
641 if (rdmsrl_amd_safe(index
, &val
))
643 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
648 static int show_msr __cpuinitdata
;
649 static __init
int setup_show_msr(char *arg
)
653 get_option(&arg
, &num
);
659 __setup("show_msr=", setup_show_msr
);
661 static __init
int setup_noclflush(char *arg
)
663 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
666 __setup("noclflush", setup_noclflush
);
668 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
672 if (c
->x86_vendor
< X86_VENDOR_NUM
)
673 vendor
= this_cpu
->c_vendor
;
674 else if (c
->cpuid_level
>= 0)
675 vendor
= c
->x86_vendor_id
;
677 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
678 printk(KERN_CONT
"%s ", vendor
);
680 if (c
->x86_model_id
[0])
681 printk(KERN_CONT
"%s", c
->x86_model_id
);
683 printk(KERN_CONT
"%d86", c
->x86
);
685 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
686 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
688 printk(KERN_CONT
"\n");
691 if (c
->cpu_index
< show_msr
)
699 static __init
int setup_disablecpuid(char *arg
)
702 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
703 setup_clear_cpu_cap(bit
);
708 __setup("clearcpuid=", setup_disablecpuid
);
710 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
712 /* Make sure %fs is initialized properly in idle threads */
713 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
715 memset(regs
, 0, sizeof(struct pt_regs
));
716 regs
->fs
= __KERNEL_PERCPU
;
721 * cpu_init() initializes state that is per-CPU. Some data is already
722 * initialized (naturally) in the bootstrap process, such as the GDT
723 * and IDT. We reload them nevertheless, this function acts as a
724 * 'CPU state barrier', nothing should get across.
726 void __cpuinit
cpu_init(void)
728 int cpu
= smp_processor_id();
729 struct task_struct
*curr
= current
;
730 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
731 struct thread_struct
*thread
= &curr
->thread
;
733 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
734 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
735 for (;;) local_irq_enable();
738 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
740 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
741 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
743 load_idt(&idt_descr
);
747 * Set up and load the per-CPU TSS and LDT
749 atomic_inc(&init_mm
.mm_count
);
750 curr
->active_mm
= &init_mm
;
753 enter_lazy_tlb(&init_mm
, curr
);
756 set_tss_desc(cpu
, t
);
758 load_LDT(&init_mm
.context
);
760 #ifdef CONFIG_DOUBLEFAULT
761 /* Set up doublefault TSS pointer in the GDT */
762 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
766 asm volatile ("mov %0, %%gs" : : "r" (0));
768 /* Clear all 6 debug registers: */
777 * Force FPU initialization:
780 current_thread_info()->status
= TS_XSAVE
;
782 current_thread_info()->status
= 0;
784 mxcsr_feature_mask_init();
787 * Boot processor to setup the FP and extended state context info.
789 if (!smp_processor_id())
790 init_thread_xstate();
795 #ifdef CONFIG_HOTPLUG_CPU
796 void __cpuinit
cpu_uninit(void)
798 int cpu
= raw_smp_processor_id();
799 cpu_clear(cpu
, cpu_initialized
);
802 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
803 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;