1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
31 #include <asm/pgtable.h>
32 #include <asm/processor.h>
34 #include <asm/atomic.h>
35 #include <asm/proto.h>
36 #include <asm/sections.h>
37 #include <asm/setup.h>
41 static struct cpu_dev
*this_cpu __cpuinitdata
;
44 /* We need valid kernel segments for data and code in long mode too
45 * IRET will check the segment types kkeil 2000/10/28
46 * Also sysret mandates a special GDT layout
48 /* The TLS descriptors are currently at a different place compared to i386.
49 Hopefully nobody expects them at a fixed place (Wine?) */
50 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
51 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
52 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
53 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
54 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
55 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
56 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
59 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
60 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
61 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
62 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
63 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
65 * Segments used for calling PnP BIOS have byte granularity.
66 * They code segments and data segments have fixed 64k limits,
67 * the transfer segment sizes are set at run time.
70 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
72 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
74 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
76 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
78 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
80 * The APM segments have byte granularity and their bases
81 * are set at run time. All have 64k limits.
84 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
86 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
88 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
90 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
91 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
94 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
97 static int cachesize_override __cpuinitdata
= -1;
98 static int disable_x86_serial_nr __cpuinitdata
= 1;
100 static int __init
cachesize_setup(char *str
)
102 get_option(&str
, &cachesize_override
);
105 __setup("cachesize=", cachesize_setup
);
107 static int __init
x86_fxsr_setup(char *s
)
109 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
110 setup_clear_cpu_cap(X86_FEATURE_XMM
);
113 __setup("nofxsr", x86_fxsr_setup
);
115 static int __init
x86_sep_setup(char *s
)
117 setup_clear_cpu_cap(X86_FEATURE_SEP
);
120 __setup("nosep", x86_sep_setup
);
122 /* Standard macro to see if a specific flag is changeable */
123 static inline int flag_is_changeable_p(u32 flag
)
137 : "=&r" (f1
), "=&r" (f2
)
140 return ((f1
^f2
) & flag
) != 0;
143 /* Probe for the CPUID instruction */
144 static int __cpuinit
have_cpuid_p(void)
146 return flag_is_changeable_p(X86_EFLAGS_ID
);
149 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
151 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
152 /* Disable processor serial number */
153 unsigned long lo
, hi
;
154 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
156 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
157 printk(KERN_NOTICE
"CPU serial number disabled.\n");
158 clear_cpu_cap(c
, X86_FEATURE_PN
);
160 /* Disabling the serial number may affect the cpuid level */
161 c
->cpuid_level
= cpuid_eax(0);
165 static int __init
x86_serial_nr_setup(char *s
)
167 disable_x86_serial_nr
= 0;
170 __setup("serialnumber", x86_serial_nr_setup
);
172 static inline int flag_is_changeable_p(u32 flag
)
176 /* Probe for the CPUID instruction */
177 static inline int have_cpuid_p(void)
181 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
187 * Naming convention should be: <Name> [(<Codename>)]
188 * This table only is used unless init_<vendor>() below doesn't set it;
189 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
193 /* Look up CPU names by table lookup. */
194 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
196 struct cpu_model_info
*info
;
198 if (c
->x86_model
>= 16)
199 return NULL
; /* Range check */
204 info
= this_cpu
->c_models
;
206 while (info
&& info
->family
) {
207 if (info
->family
== c
->x86
)
208 return info
->model_names
[c
->x86_model
];
211 return NULL
; /* Not found */
214 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
216 /* Current gdt points %fs at the "master" per-cpu area: after this,
217 * it's on the real one. */
218 void switch_to_new_gdt(void)
220 struct desc_ptr gdt_descr
;
222 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
223 gdt_descr
.size
= GDT_SIZE
- 1;
224 load_gdt(&gdt_descr
);
226 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU
) : "memory");
230 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
232 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
235 display_cacheinfo(c
);
237 /* Not much we can do here... */
238 /* Check if at least it has cpuid */
239 if (c
->cpuid_level
== -1) {
240 /* No cpuid. It must be an ancient CPU */
242 strcpy(c
->x86_model_id
, "486");
243 else if (c
->x86
== 3)
244 strcpy(c
->x86_model_id
, "386");
249 static struct cpu_dev __cpuinitdata default_cpu
= {
250 .c_init
= default_init
,
251 .c_vendor
= "Unknown",
252 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
255 static void __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
260 if (c
->extended_cpuid_level
< 0x80000004)
263 v
= (unsigned int *) c
->x86_model_id
;
264 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
265 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
266 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
267 c
->x86_model_id
[48] = 0;
269 /* Intel chips right-justify this string for some dumb reason;
270 undo that brain damage */
271 p
= q
= &c
->x86_model_id
[0];
277 while (q
<= &c
->x86_model_id
[48])
278 *q
++ = '\0'; /* Zero-pad the rest */
282 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
284 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
286 n
= c
->extended_cpuid_level
;
288 if (n
>= 0x80000005) {
289 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
290 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
291 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
292 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
294 /* On K8 L1 TLB is inclusive, so don't count it */
299 if (n
< 0x80000006) /* Some chips just has a large L1. */
302 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
306 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
308 /* do processor-specific cache resizing */
309 if (this_cpu
->c_size_cache
)
310 l2size
= this_cpu
->c_size_cache(c
, l2size
);
312 /* Allow user to override all this if necessary. */
313 if (cachesize_override
!= -1)
314 l2size
= cachesize_override
;
317 return; /* Again, no L2 cache is possible */
320 c
->x86_cache_size
= l2size
;
322 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
326 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
329 u32 eax
, ebx
, ecx
, edx
;
330 int index_msb
, core_bits
;
332 if (!cpu_has(c
, X86_FEATURE_HT
))
335 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
338 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
341 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
343 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
345 if (smp_num_siblings
== 1) {
346 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
347 } else if (smp_num_siblings
> 1) {
349 if (smp_num_siblings
> NR_CPUS
) {
350 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
352 smp_num_siblings
= 1;
356 index_msb
= get_count_order(smp_num_siblings
);
358 c
->phys_proc_id
= phys_pkg_id(index_msb
);
360 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
363 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
365 index_msb
= get_count_order(smp_num_siblings
);
367 core_bits
= get_count_order(c
->x86_max_cores
);
370 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
371 ((1 << core_bits
) - 1);
373 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
374 ((1 << core_bits
) - 1);
379 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
380 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
382 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
388 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
390 char *v
= c
->x86_vendor_id
;
394 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
398 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
399 (cpu_devs
[i
]->c_ident
[1] &&
400 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
401 this_cpu
= cpu_devs
[i
];
402 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
409 printk(KERN_ERR
"CPU: vendor_id '%s' unknown, using generic init.\n", v
);
410 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
413 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
414 this_cpu
= &default_cpu
;
417 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
419 /* Get vendor name */
420 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
421 (unsigned int *)&c
->x86_vendor_id
[0],
422 (unsigned int *)&c
->x86_vendor_id
[8],
423 (unsigned int *)&c
->x86_vendor_id
[4]);
426 /* Intel-defined flags: level 0x00000001 */
427 if (c
->cpuid_level
>= 0x00000001) {
428 u32 junk
, tfms
, cap0
, misc
;
429 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
430 c
->x86
= (tfms
>> 8) & 0xf;
431 c
->x86_model
= (tfms
>> 4) & 0xf;
432 c
->x86_mask
= tfms
& 0xf;
434 c
->x86
+= (tfms
>> 20) & 0xff;
436 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
437 if (cap0
& (1<<19)) {
438 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
439 c
->x86_cache_alignment
= c
->x86_clflush_size
;
444 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
449 /* Intel-defined flags: level 0x00000001 */
450 if (c
->cpuid_level
>= 0x00000001) {
451 u32 capability
, excap
;
452 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
453 c
->x86_capability
[0] = capability
;
454 c
->x86_capability
[4] = excap
;
457 /* AMD-defined flags: level 0x80000001 */
458 xlvl
= cpuid_eax(0x80000000);
459 c
->extended_cpuid_level
= xlvl
;
460 if ((xlvl
& 0xffff0000) == 0x80000000) {
461 if (xlvl
>= 0x80000001) {
462 c
->x86_capability
[1] = cpuid_edx(0x80000001);
463 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
468 if (c
->extended_cpuid_level
>= 0x80000008) {
469 u32 eax
= cpuid_eax(0x80000008);
471 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
472 c
->x86_phys_bits
= eax
& 0xff;
476 if (c
->extended_cpuid_level
>= 0x80000007)
477 c
->x86_power
= cpuid_edx(0x80000007);
481 static void __cpuinit
identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
487 * First of all, decide if this is a 486 or higher
488 * It's a 486 if we can modify the AC flag
490 if (flag_is_changeable_p(X86_EFLAGS_AC
))
495 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
496 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
497 c
->x86_vendor_id
[0] = 0;
498 cpu_devs
[i
]->c_identify(c
);
499 if (c
->x86_vendor_id
[0]) {
508 * Do minimum CPU detection early.
509 * Fields really needed: vendor, cpuid_level, family, model, mask,
511 * The others are not touched to avoid unwanted side effects.
513 * WARNING: this function is only called on the BP. Don't add code here
514 * that is supposed to run on all CPUs.
516 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
519 c
->x86_clflush_size
= 64;
521 c
->x86_clflush_size
= 32;
523 c
->x86_cache_alignment
= c
->x86_clflush_size
;
525 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
526 c
->extended_cpuid_level
= 0;
529 identify_cpu_without_cpuid(c
);
531 /* cyrix could have cpuid enabled via c_identify()*/
541 if (this_cpu
->c_early_init
)
542 this_cpu
->c_early_init(c
);
544 validate_pat_support(c
);
547 void __init
early_cpu_init(void)
549 struct cpu_dev
**cdev
;
552 printk("KERNEL supported cpus:\n");
553 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
554 struct cpu_dev
*cpudev
= *cdev
;
557 if (count
>= X86_VENDOR_NUM
)
559 cpu_devs
[count
] = cpudev
;
562 for (j
= 0; j
< 2; j
++) {
563 if (!cpudev
->c_ident
[j
])
565 printk(" %s %s\n", cpudev
->c_vendor
,
570 early_identify_cpu(&boot_cpu_data
);
574 * The NOPL instruction is supposed to exist on all CPUs with
575 * family >= 6; unfortunately, that's not true in practice because
576 * of early VIA chips and (more importantly) broken virtualizers that
577 * are not easy to detect. In the latter case it doesn't even *fail*
578 * reliably, so probing for it doesn't even work. Disable it completely
579 * unless we can find a reliable way to detect all the broken cases.
581 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
583 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
586 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
588 c
->extended_cpuid_level
= 0;
591 identify_cpu_without_cpuid(c
);
593 /* cyrix could have cpuid enabled via c_identify()*/
603 if (c
->cpuid_level
>= 0x00000001) {
604 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
606 # ifdef CONFIG_X86_HT
607 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
609 c
->apicid
= c
->initial_apicid
;
614 c
->phys_proc_id
= c
->initial_apicid
;
618 get_model_name(c
); /* Default name */
620 init_scattered_cpuid_features(c
);
625 * This does the hard work of actually picking apart the CPU stuff...
627 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
631 c
->loops_per_jiffy
= loops_per_jiffy
;
632 c
->x86_cache_size
= -1;
633 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
634 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
635 c
->x86_vendor_id
[0] = '\0'; /* Unset */
636 c
->x86_model_id
[0] = '\0'; /* Unset */
637 c
->x86_max_cores
= 1;
638 c
->x86_coreid_bits
= 0;
640 c
->x86_clflush_size
= 64;
642 c
->cpuid_level
= -1; /* CPUID not detected */
643 c
->x86_clflush_size
= 32;
645 c
->x86_cache_alignment
= c
->x86_clflush_size
;
646 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
650 if (this_cpu
->c_identify
)
651 this_cpu
->c_identify(c
);
654 c
->apicid
= phys_pkg_id(0);
658 * Vendor-specific initialization. In this section we
659 * canonicalize the feature flags, meaning if there are
660 * features a certain CPU supports which CPUID doesn't
661 * tell us, CPUID claiming incorrect flags, or other bugs,
662 * we handle them here.
664 * At the end of this section, c->x86_capability better
665 * indicate the features this CPU genuinely supports!
667 if (this_cpu
->c_init
)
670 /* Disable the PN if appropriate */
671 squash_the_stupid_serial_number(c
);
674 * The vendor-specific functions might have changed features. Now
675 * we do "generic changes."
678 /* If the model name is still unset, do table lookup. */
679 if (!c
->x86_model_id
[0]) {
681 p
= table_lookup_model(c
);
683 strcpy(c
->x86_model_id
, p
);
686 sprintf(c
->x86_model_id
, "%02x/%02x",
687 c
->x86
, c
->x86_model
);
695 * On SMP, boot_cpu_data holds the common feature set between
696 * all CPUs; so make sure that we indicate which features are
697 * common between the CPUs. The first time this routine gets
698 * executed, c == &boot_cpu_data.
700 if (c
!= &boot_cpu_data
) {
701 /* AND the already accumulated flags with these */
702 for (i
= 0; i
< NCAPINTS
; i
++)
703 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
706 /* Clear all flags overriden by options */
707 for (i
= 0; i
< NCAPINTS
; i
++)
708 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
710 #ifdef CONFIG_X86_MCE
711 /* Init Machine Check Exception if available. */
715 select_idle_routine(c
);
717 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
718 numa_add_cpu(smp_processor_id());
722 void __init
identify_boot_cpu(void)
724 identify_cpu(&boot_cpu_data
);
731 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
733 BUG_ON(c
== &boot_cpu_data
);
746 static struct msr_range msr_range_array
[] __cpuinitdata
= {
747 { 0x00000000, 0x00000418},
748 { 0xc0000000, 0xc000040b},
749 { 0xc0010000, 0xc0010142},
750 { 0xc0011000, 0xc001103b},
753 static void __cpuinit
print_cpu_msr(void)
758 unsigned index_min
, index_max
;
760 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
761 index_min
= msr_range_array
[i
].min
;
762 index_max
= msr_range_array
[i
].max
;
763 for (index
= index_min
; index
< index_max
; index
++) {
764 if (rdmsrl_amd_safe(index
, &val
))
766 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
771 static int show_msr __cpuinitdata
;
772 static __init
int setup_show_msr(char *arg
)
776 get_option(&arg
, &num
);
782 __setup("show_msr=", setup_show_msr
);
784 static __init
int setup_noclflush(char *arg
)
786 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
789 __setup("noclflush", setup_noclflush
);
791 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
795 if (c
->x86_vendor
< X86_VENDOR_NUM
)
796 vendor
= this_cpu
->c_vendor
;
797 else if (c
->cpuid_level
>= 0)
798 vendor
= c
->x86_vendor_id
;
800 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
801 printk(KERN_CONT
"%s ", vendor
);
803 if (c
->x86_model_id
[0])
804 printk(KERN_CONT
"%s", c
->x86_model_id
);
806 printk(KERN_CONT
"%d86", c
->x86
);
808 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
809 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
811 printk(KERN_CONT
"\n");
814 if (c
->cpu_index
< show_msr
)
822 static __init
int setup_disablecpuid(char *arg
)
825 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
826 setup_clear_cpu_cap(bit
);
831 __setup("clearcpuid=", setup_disablecpuid
);
833 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
836 struct x8664_pda
**_cpu_pda __read_mostly
;
837 EXPORT_SYMBOL(_cpu_pda
);
839 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
841 char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
843 void __cpuinit
pda_init(int cpu
)
845 struct x8664_pda
*pda
= cpu_pda(cpu
);
847 /* Setup up data that may be needed in __get_free_pages early */
850 /* Memory clobbers used to order PDA accessed */
852 wrmsrl(MSR_GS_BASE
, pda
);
855 pda
->cpunumber
= cpu
;
857 pda
->kernelstack
= (unsigned long)stack_thread_info() -
858 PDA_STACKOFFSET
+ THREAD_SIZE
;
859 pda
->active_mm
= &init_mm
;
863 /* others are initialized in smpboot.c */
864 pda
->pcurrent
= &init_task
;
865 pda
->irqstackptr
= boot_cpu_stack
;
866 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
868 if (!pda
->irqstackptr
) {
869 pda
->irqstackptr
= (char *)
870 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
871 if (!pda
->irqstackptr
)
872 panic("cannot allocate irqstack for cpu %d",
874 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
877 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
878 pda
->nodenumber
= cpu_to_node(cpu
);
882 char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
883 DEBUG_STKSZ
] __page_aligned_bss
;
885 extern asmlinkage
void ignore_sysret(void);
887 /* May not be marked __init: used by software suspend */
888 void syscall_init(void)
891 * LSTAR and STAR live in a bit strange symbiosis.
892 * They both write to the same internal register. STAR allows to
893 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
895 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
896 wrmsrl(MSR_LSTAR
, system_call
);
897 wrmsrl(MSR_CSTAR
, ignore_sysret
);
899 #ifdef CONFIG_IA32_EMULATION
900 syscall32_cpu_init();
903 /* Flags to clear on syscall */
904 wrmsrl(MSR_SYSCALL_MASK
,
905 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
908 unsigned long kernel_eflags
;
911 * Copies of the original ist values from the tss are only accessed during
912 * debugging, no special alignment required.
914 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
918 /* Make sure %fs is initialized properly in idle threads */
919 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
921 memset(regs
, 0, sizeof(struct pt_regs
));
922 regs
->fs
= __KERNEL_PERCPU
;
928 * cpu_init() initializes state that is per-CPU. Some data is already
929 * initialized (naturally) in the bootstrap process, such as the GDT
930 * and IDT. We reload them nevertheless, this function acts as a
931 * 'CPU state barrier', nothing should get across.
932 * A lot of state is already set up in PDA init for 64 bit
935 void __cpuinit
cpu_init(void)
937 int cpu
= stack_smp_processor_id();
938 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
939 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
941 char *estacks
= NULL
;
942 struct task_struct
*me
;
945 /* CPU 0 is initialised in head64.c */
949 estacks
= boot_exception_stacks
;
953 if (cpu_test_and_set(cpu
, cpu_initialized
))
954 panic("CPU#%d already initialized!\n", cpu
);
956 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
958 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
961 * Initialize the per-CPU GDT with the boot GDT,
962 * and set up the GDT descriptor:
966 load_idt((const struct desc_ptr
*)&idt_descr
);
968 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
971 wrmsrl(MSR_FS_BASE
, 0);
972 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
976 if (cpu
!= 0 && x2apic
)
980 * set up and load the per-CPU TSS
982 if (!orig_ist
->ist
[0]) {
983 static const unsigned int order
[N_EXCEPTION_STACKS
] = {
984 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STACK_ORDER
,
985 [DEBUG_STACK
- 1] = DEBUG_STACK_ORDER
987 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
989 estacks
= (char *)__get_free_pages(GFP_ATOMIC
, order
[v
]);
991 panic("Cannot allocate exception "
992 "stack %ld %d\n", v
, cpu
);
994 estacks
+= PAGE_SIZE
<< order
[v
];
995 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
996 (unsigned long)estacks
;
1000 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1002 * <= is required because the CPU will access up to
1003 * 8 bits beyond the end of the IO permission bitmap.
1005 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1006 t
->io_bitmap
[i
] = ~0UL;
1008 atomic_inc(&init_mm
.mm_count
);
1009 me
->active_mm
= &init_mm
;
1012 enter_lazy_tlb(&init_mm
, me
);
1014 load_sp0(t
, ¤t
->thread
);
1015 set_tss_desc(cpu
, t
);
1017 load_LDT(&init_mm
.context
);
1021 * If the kgdb is connected no debug regs should be altered. This
1022 * is only applicable when KGDB and a KGDB I/O module are built
1023 * into the kernel and you are using early debugging with
1024 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1026 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
1027 arch_kgdb_ops
.correct_hw_break();
1031 * Clear all 6 debug registers:
1034 set_debugreg(0UL, 0);
1035 set_debugreg(0UL, 1);
1036 set_debugreg(0UL, 2);
1037 set_debugreg(0UL, 3);
1038 set_debugreg(0UL, 6);
1039 set_debugreg(0UL, 7);
1041 /* If the kgdb is connected no debug regs should be altered. */
1047 raw_local_save_flags(kernel_eflags
);
1055 void __cpuinit
cpu_init(void)
1057 int cpu
= smp_processor_id();
1058 struct task_struct
*curr
= current
;
1059 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1060 struct thread_struct
*thread
= &curr
->thread
;
1062 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
1063 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1064 for (;;) local_irq_enable();
1067 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1069 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1070 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1072 load_idt(&idt_descr
);
1073 switch_to_new_gdt();
1076 * Set up and load the per-CPU TSS and LDT
1078 atomic_inc(&init_mm
.mm_count
);
1079 curr
->active_mm
= &init_mm
;
1082 enter_lazy_tlb(&init_mm
, curr
);
1084 load_sp0(t
, thread
);
1085 set_tss_desc(cpu
, t
);
1087 load_LDT(&init_mm
.context
);
1089 #ifdef CONFIG_DOUBLEFAULT
1090 /* Set up doublefault TSS pointer in the GDT */
1091 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1095 asm volatile ("mov %0, %%gs" : : "r" (0));
1097 /* Clear all 6 debug registers: */
1106 * Force FPU initialization:
1109 current_thread_info()->status
= TS_XSAVE
;
1111 current_thread_info()->status
= 0;
1113 mxcsr_feature_mask_init();
1116 * Boot processor to setup the FP and extended state context info.
1118 if (!smp_processor_id())
1119 init_thread_xstate();