1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/processor.h>
12 #include <asm/mmu_context.h>
17 #ifdef CONFIG_X86_LOCAL_APIC
18 #include <asm/mpspec.h>
20 #include <mach_apic.h>
25 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
26 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
27 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
28 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
29 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
31 * Segments used for calling PnP BIOS have byte granularity.
32 * They code segments and data segments have fixed 64k limits,
33 * the transfer segment sizes are set at run time.
36 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
38 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
40 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
42 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
44 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
46 * The APM segments have byte granularity and their bases
47 * are set at run time. All have 64k limits.
50 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
52 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
54 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
56 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
57 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
59 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
61 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
63 static int cachesize_override __cpuinitdata
= -1;
64 static int disable_x86_serial_nr __cpuinitdata
= 1;
66 struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
68 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
70 /* Not much we can do here... */
71 /* Check if at least it has cpuid */
72 if (c
->cpuid_level
== -1) {
73 /* No cpuid. It must be an ancient CPU */
75 strcpy(c
->x86_model_id
, "486");
77 strcpy(c
->x86_model_id
, "386");
81 static struct cpu_dev __cpuinitdata default_cpu
= {
82 .c_init
= default_init
,
83 .c_vendor
= "Unknown",
85 static struct cpu_dev
*this_cpu __cpuinitdata
= &default_cpu
;
87 static int __init
cachesize_setup(char *str
)
89 get_option(&str
, &cachesize_override
);
92 __setup("cachesize=", cachesize_setup
);
94 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
99 if (cpuid_eax(0x80000000) < 0x80000004)
102 v
= (unsigned int *) c
->x86_model_id
;
103 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
104 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
105 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
106 c
->x86_model_id
[48] = 0;
108 /* Intel chips right-justify this string for some dumb reason;
109 undo that brain damage */
110 p
= q
= &c
->x86_model_id
[0];
116 while (q
<= &c
->x86_model_id
[48])
117 *q
++ = '\0'; /* Zero-pad the rest */
124 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
126 unsigned int n
, dummy
, ecx
, edx
, l2size
;
128 n
= cpuid_eax(0x80000000);
130 if (n
>= 0x80000005) {
131 cpuid(0x80000005, &dummy
, &dummy
, &ecx
, &edx
);
132 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
133 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
134 c
->x86_cache_size
= (ecx
>>24)+(edx
>>24);
137 if (n
< 0x80000006) /* Some chips just has a large L1. */
140 ecx
= cpuid_ecx(0x80000006);
143 /* do processor-specific cache resizing */
144 if (this_cpu
->c_size_cache
)
145 l2size
= this_cpu
->c_size_cache(c
, l2size
);
147 /* Allow user to override all this if necessary. */
148 if (cachesize_override
!= -1)
149 l2size
= cachesize_override
;
152 return; /* Again, no L2 cache is possible */
154 c
->x86_cache_size
= l2size
;
156 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
161 * Naming convention should be: <Name> [(<Codename>)]
162 * This table only is used unless init_<vendor>() below doesn't set it;
163 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
167 /* Look up CPU names by table lookup. */
168 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
170 struct cpu_model_info
*info
;
172 if (c
->x86_model
>= 16)
173 return NULL
; /* Range check */
178 info
= this_cpu
->c_models
;
180 while (info
&& info
->family
) {
181 if (info
->family
== c
->x86
)
182 return info
->model_names
[c
->x86_model
];
185 return NULL
; /* Not found */
189 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
, int early
)
191 char *v
= c
->x86_vendor_id
;
195 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
197 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
198 (cpu_devs
[i
]->c_ident
[1] &&
199 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
202 this_cpu
= cpu_devs
[i
];
209 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
210 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
212 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
213 this_cpu
= &default_cpu
;
217 static int __init
x86_fxsr_setup(char *s
)
219 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
220 setup_clear_cpu_cap(X86_FEATURE_XMM
);
223 __setup("nofxsr", x86_fxsr_setup
);
226 static int __init
x86_sep_setup(char *s
)
228 setup_clear_cpu_cap(X86_FEATURE_SEP
);
231 __setup("nosep", x86_sep_setup
);
234 /* Standard macro to see if a specific flag is changeable */
235 static inline int flag_is_changeable_p(u32 flag
)
249 : "=&r" (f1
), "=&r" (f2
)
252 return ((f1
^f2
) & flag
) != 0;
256 /* Probe for the CPUID instruction */
257 static int __cpuinit
have_cpuid_p(void)
259 return flag_is_changeable_p(X86_EFLAGS_ID
);
262 void __init
cpu_detect(struct cpuinfo_x86
*c
)
264 /* Get vendor name */
265 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
266 (unsigned int *)&c
->x86_vendor_id
[0],
267 (unsigned int *)&c
->x86_vendor_id
[8],
268 (unsigned int *)&c
->x86_vendor_id
[4]);
271 if (c
->cpuid_level
>= 0x00000001) {
272 u32 junk
, tfms
, cap0
, misc
;
273 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
274 c
->x86
= (tfms
>> 8) & 15;
275 c
->x86_model
= (tfms
>> 4) & 15;
277 c
->x86
+= (tfms
>> 20) & 0xff;
279 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
280 c
->x86_mask
= tfms
& 15;
281 if (cap0
& (1<<19)) {
282 c
->x86_cache_alignment
= ((misc
>> 8) & 0xff) * 8;
283 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
287 static void __cpuinit
early_get_cap(struct cpuinfo_x86
*c
)
292 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
293 if (have_cpuid_p()) {
294 /* Intel-defined flags: level 0x00000001 */
295 if (c
->cpuid_level
>= 0x00000001) {
296 u32 capability
, excap
;
297 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
298 c
->x86_capability
[0] = capability
;
299 c
->x86_capability
[4] = excap
;
302 /* AMD-defined flags: level 0x80000001 */
303 xlvl
= cpuid_eax(0x80000000);
304 if ((xlvl
& 0xffff0000) == 0x80000000) {
305 if (xlvl
>= 0x80000001) {
306 c
->x86_capability
[1] = cpuid_edx(0x80000001);
307 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
316 * Do minimum CPU detection early.
317 * Fields really needed: vendor, cpuid_level, family, model, mask,
319 * The others are not touched to avoid unwanted side effects.
321 * WARNING: this function is only called on the BP. Don't add code here
322 * that is supposed to run on all CPUs.
324 static void __init
early_cpu_detect(void)
326 struct cpuinfo_x86
*c
= &boot_cpu_data
;
328 c
->x86_cache_alignment
= 32;
329 c
->x86_clflush_size
= 32;
336 get_cpu_vendor(c
, 1);
338 if (c
->x86_vendor
!= X86_VENDOR_UNKNOWN
&&
339 cpu_devs
[c
->x86_vendor
]->c_early_init
)
340 cpu_devs
[c
->x86_vendor
]->c_early_init(c
);
346 * The NOPL instruction is supposed to exist on all CPUs with
347 * family >= 6, unfortunately, that's not true in practice because
348 * of early VIA chips and (more importantly) broken virtualizers that
349 * are not easy to detect. Hence, probe for it based on first
352 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
354 const u32 nopl_signature
= 0x888c53b1; /* Random number */
355 u32 has_nopl
= nopl_signature
;
357 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
360 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
362 " .section .fixup,\"ax\"\n"
369 if (has_nopl
== nopl_signature
)
370 set_cpu_cap(c
, X86_FEATURE_NOPL
);
374 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
379 if (have_cpuid_p()) {
380 /* Get vendor name */
381 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
382 (unsigned int *)&c
->x86_vendor_id
[0],
383 (unsigned int *)&c
->x86_vendor_id
[8],
384 (unsigned int *)&c
->x86_vendor_id
[4]);
386 get_cpu_vendor(c
, 0);
387 /* Initialize the standard set of capabilities */
388 /* Note that the vendor-specific code below might override */
389 /* Intel-defined flags: level 0x00000001 */
390 if (c
->cpuid_level
>= 0x00000001) {
391 u32 capability
, excap
;
392 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
393 c
->x86_capability
[0] = capability
;
394 c
->x86_capability
[4] = excap
;
395 c
->x86
= (tfms
>> 8) & 15;
396 c
->x86_model
= (tfms
>> 4) & 15;
398 c
->x86
+= (tfms
>> 20) & 0xff;
400 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
401 c
->x86_mask
= tfms
& 15;
402 c
->initial_apicid
= (ebx
>> 24) & 0xFF;
404 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
405 c
->phys_proc_id
= c
->initial_apicid
;
407 c
->apicid
= c
->initial_apicid
;
409 if (test_cpu_cap(c
, X86_FEATURE_CLFLSH
))
410 c
->x86_clflush_size
= ((ebx
>> 8) & 0xff) * 8;
412 /* Have CPUID level 0 only - unheard of */
416 /* AMD-defined flags: level 0x80000001 */
417 xlvl
= cpuid_eax(0x80000000);
418 if ((xlvl
& 0xffff0000) == 0x80000000) {
419 if (xlvl
>= 0x80000001) {
420 c
->x86_capability
[1] = cpuid_edx(0x80000001);
421 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
423 if (xlvl
>= 0x80000004)
424 get_model_name(c
); /* Default name */
427 init_scattered_cpuid_features(c
);
432 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
434 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
435 /* Disable processor serial number */
436 unsigned long lo
, hi
;
437 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
439 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
440 printk(KERN_NOTICE
"CPU serial number disabled.\n");
441 clear_cpu_cap(c
, X86_FEATURE_PN
);
443 /* Disabling the serial number may affect the cpuid level */
444 c
->cpuid_level
= cpuid_eax(0);
448 static int __init
x86_serial_nr_setup(char *s
)
450 disable_x86_serial_nr
= 0;
453 __setup("serialnumber", x86_serial_nr_setup
);
458 * This does the hard work of actually picking apart the CPU stuff...
460 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
464 c
->loops_per_jiffy
= loops_per_jiffy
;
465 c
->x86_cache_size
= -1;
466 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
467 c
->cpuid_level
= -1; /* CPUID not detected */
468 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
469 c
->x86_vendor_id
[0] = '\0'; /* Unset */
470 c
->x86_model_id
[0] = '\0'; /* Unset */
471 c
->x86_max_cores
= 1;
472 c
->x86_clflush_size
= 32;
473 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
475 if (!have_cpuid_p()) {
477 * First of all, decide if this is a 486 or higher
478 * It's a 486 if we can modify the AC flag
480 if (flag_is_changeable_p(X86_EFLAGS_AC
))
488 if (this_cpu
->c_identify
)
489 this_cpu
->c_identify(c
);
492 * Vendor-specific initialization. In this section we
493 * canonicalize the feature flags, meaning if there are
494 * features a certain CPU supports which CPUID doesn't
495 * tell us, CPUID claiming incorrect flags, or other bugs,
496 * we handle them here.
498 * At the end of this section, c->x86_capability better
499 * indicate the features this CPU genuinely supports!
501 if (this_cpu
->c_init
)
504 /* Disable the PN if appropriate */
505 squash_the_stupid_serial_number(c
);
508 * The vendor-specific functions might have changed features. Now
509 * we do "generic changes."
512 /* If the model name is still unset, do table lookup. */
513 if (!c
->x86_model_id
[0]) {
515 p
= table_lookup_model(c
);
517 strcpy(c
->x86_model_id
, p
);
520 sprintf(c
->x86_model_id
, "%02x/%02x",
521 c
->x86
, c
->x86_model
);
525 * On SMP, boot_cpu_data holds the common feature set between
526 * all CPUs; so make sure that we indicate which features are
527 * common between the CPUs. The first time this routine gets
528 * executed, c == &boot_cpu_data.
530 if (c
!= &boot_cpu_data
) {
531 /* AND the already accumulated flags with these */
532 for (i
= 0 ; i
< NCAPINTS
; i
++)
533 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
536 /* Clear all flags overriden by options */
537 for (i
= 0; i
< NCAPINTS
; i
++)
538 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
540 /* Init Machine Check Exception if available. */
543 select_idle_routine(c
);
546 void __init
identify_boot_cpu(void)
548 identify_cpu(&boot_cpu_data
);
553 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
555 BUG_ON(c
== &boot_cpu_data
);
562 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
564 u32 eax
, ebx
, ecx
, edx
;
565 int index_msb
, core_bits
;
567 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
569 if (!cpu_has(c
, X86_FEATURE_HT
) || cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
572 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
574 if (smp_num_siblings
== 1) {
575 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
576 } else if (smp_num_siblings
> 1) {
578 if (smp_num_siblings
> NR_CPUS
) {
579 printk(KERN_WARNING
"CPU: Unsupported number of the "
580 "siblings %d", smp_num_siblings
);
581 smp_num_siblings
= 1;
585 index_msb
= get_count_order(smp_num_siblings
);
586 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
588 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
591 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
593 index_msb
= get_count_order(smp_num_siblings
) ;
595 core_bits
= get_count_order(c
->x86_max_cores
);
597 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
598 ((1 << core_bits
) - 1);
600 if (c
->x86_max_cores
> 1)
601 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
607 static __init
int setup_noclflush(char *arg
)
609 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
612 __setup("noclflush", setup_noclflush
);
614 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
618 if (c
->x86_vendor
< X86_VENDOR_NUM
)
619 vendor
= this_cpu
->c_vendor
;
620 else if (c
->cpuid_level
>= 0)
621 vendor
= c
->x86_vendor_id
;
623 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
624 printk("%s ", vendor
);
626 if (!c
->x86_model_id
[0])
627 printk("%d86", c
->x86
);
629 printk("%s", c
->x86_model_id
);
631 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
632 printk(" stepping %02x\n", c
->x86_mask
);
637 static __init
int setup_disablecpuid(char *arg
)
640 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
641 setup_clear_cpu_cap(bit
);
646 __setup("clearcpuid=", setup_disablecpuid
);
648 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
650 void __init
early_cpu_init(void)
652 struct cpu_vendor_dev
*cvdev
;
654 for (cvdev
= __x86cpuvendor_start
;
655 cvdev
< __x86cpuvendor_end
;
657 cpu_devs
[cvdev
->vendor
] = cvdev
->cpu_dev
;
660 validate_pat_support(&boot_cpu_data
);
663 /* Make sure %fs is initialized properly in idle threads */
664 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
666 memset(regs
, 0, sizeof(struct pt_regs
));
667 regs
->fs
= __KERNEL_PERCPU
;
671 /* Current gdt points %fs at the "master" per-cpu area: after this,
672 * it's on the real one. */
673 void switch_to_new_gdt(void)
675 struct desc_ptr gdt_descr
;
677 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
678 gdt_descr
.size
= GDT_SIZE
- 1;
679 load_gdt(&gdt_descr
);
680 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU
) : "memory");
684 * cpu_init() initializes state that is per-CPU. Some data is already
685 * initialized (naturally) in the bootstrap process, such as the GDT
686 * and IDT. We reload them nevertheless, this function acts as a
687 * 'CPU state barrier', nothing should get across.
689 void __cpuinit
cpu_init(void)
691 int cpu
= smp_processor_id();
692 struct task_struct
*curr
= current
;
693 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
694 struct thread_struct
*thread
= &curr
->thread
;
696 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
697 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
698 for (;;) local_irq_enable();
701 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
703 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
704 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
706 load_idt(&idt_descr
);
710 * Set up and load the per-CPU TSS and LDT
712 atomic_inc(&init_mm
.mm_count
);
713 curr
->active_mm
= &init_mm
;
716 enter_lazy_tlb(&init_mm
, curr
);
719 set_tss_desc(cpu
, t
);
721 load_LDT(&init_mm
.context
);
723 #ifdef CONFIG_DOUBLEFAULT
724 /* Set up doublefault TSS pointer in the GDT */
725 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
729 asm volatile ("mov %0, %%gs" : : "r" (0));
731 /* Clear all 6 debug registers: */
740 * Force FPU initialization:
743 current_thread_info()->status
= TS_XSAVE
;
745 current_thread_info()->status
= 0;
747 mxcsr_feature_mask_init();
750 * Boot processor to setup the FP and extended state context info.
752 if (!smp_processor_id())
753 init_thread_xstate();
758 #ifdef CONFIG_HOTPLUG_CPU
759 void __cpuinit
cpu_uninit(void)
761 int cpu
= raw_smp_processor_id();
762 cpu_clear(cpu
, cpu_initialized
);
765 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
766 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;